core_ck807.h 32 KB

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  1. /*
  2. * Copyright (C) 2017-2019 Alibaba Group Holding Limited
  3. */
  4. /******************************************************************************
  5. * @file core_ck807.h
  6. * @brief CSI CK807 Core Peripheral Access Layer Header File
  7. * @version V1.0
  8. * @date 26. Jan 2018
  9. ******************************************************************************/
  10. #ifndef __CORE_CK807_H_GENERIC
  11. #define __CORE_CK807_H_GENERIC
  12. #include <stdint.h>
  13. #ifdef __cplusplus
  14. extern "C" {
  15. #endif
  16. /*******************************************************************************
  17. * CSI definitions
  18. ******************************************************************************/
  19. /**
  20. \ingroup CK807
  21. @{
  22. */
  23. /* CSI CK807 definitions */
  24. #define __CK807_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
  25. #define __CK807_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
  26. #define __CK807_CSI_VERSION ((__CK807_CSI_VERSION_MAIN << 16U) | \
  27. __CK807_CSI_VERSION_SUB ) /*!< CSI HAL version number */
  28. #ifndef __CK807
  29. #define __CK807 (0x07U) /*!< CK807 Core */
  30. #endif
  31. /** __FPU_USED indicates whether an FPU is used or not.
  32. */
  33. #define __FPU_USED 1U
  34. #if defined ( __GNUC__ )
  35. #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  36. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  37. #endif
  38. #endif
  39. #ifdef __cplusplus
  40. }
  41. #endif
  42. #endif /* __CORE_CK807_H_GENERIC */
  43. #ifndef __CSI_GENERIC
  44. #ifndef __CORE_CK807_H_DEPENDANT
  45. #define __CORE_CK807_H_DEPENDANT
  46. #ifdef __cplusplus
  47. extern "C" {
  48. #endif
  49. /* check device defines and use defaults */
  50. #ifndef __CK807_REV
  51. #define __CK807_REV 0x0000U
  52. #endif
  53. #ifndef __GSR_GCR_PRESENT
  54. #define __GSR_GCR_PRESENT 0U
  55. #endif
  56. #ifndef __ICACHE_PRESENT
  57. #define __ICACHE_PRESENT 1U
  58. #endif
  59. #ifndef __DCACHE_PRESENT
  60. #define __DCACHE_PRESENT 1U
  61. #endif
  62. #include <csi_gcc.h>
  63. /* IO definitions (access restrictions to peripheral registers) */
  64. /**
  65. \defgroup CSI_glob_defs CSI Global Defines
  66. <strong>IO Type Qualifiers</strong> are used
  67. \li to specify the access to peripheral variables.
  68. \li for automatic generation of peripheral register debug information.
  69. */
  70. #ifdef __cplusplus
  71. #define __I volatile /*!< Defines 'read only' permissions */
  72. #else
  73. #define __I volatile const /*!< Defines 'read only' permissions */
  74. #endif
  75. #define __O volatile /*!< Defines 'write only' permissions */
  76. #define __IO volatile /*!< Defines 'read / write' permissions */
  77. /* following defines should be used for structure members */
  78. #define __IM volatile const /*! Defines 'read only' structure member permissions */
  79. #define __OM volatile /*! Defines 'write only' structure member permissions */
  80. #define __IOM volatile /*! Defines 'read / write' structure member permissions */
  81. /*@} end of group CK807 */
  82. /*******************************************************************************
  83. * Register Abstraction
  84. Core Register contain:
  85. - Core Register
  86. ******************************************************************************/
  87. /**
  88. \defgroup CSI_core_register Defines and Type Definitions
  89. \brief Type definitions and defines for CK807 processor based devices.
  90. */
  91. /**
  92. \ingroup CSI_core_register
  93. \defgroup CSI_CORE Status and Control Registers
  94. \brief Core Register type definitions.
  95. @{
  96. */
  97. /**
  98. \brief Access Processor Status Register(PSR)struct definition.
  99. */
  100. typedef union {
  101. struct {
  102. uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
  103. uint32_t _reserved0: 5; /*!< bit: 2.. 5 Reserved */
  104. uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
  105. uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
  106. uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
  107. uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
  108. uint32_t _reserved1: 6; /*!< bit: 10..15 Reserved */
  109. uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
  110. uint32_t _reserved2: 5; /*!< bit: 24..28 Reserved */
  111. uint32_t SP: 1; /*!< bit: 29 Secure pedning bit */
  112. uint32_t T: 1; /*!< bit: 30 TEE mode bit */
  113. uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
  114. } b; /*!< Structure Access by bit */
  115. uint32_t w; /*!< Type Access by whole register */
  116. } PSR_Type;
  117. /* PSR Register Definitions */
  118. #define PSR_S_Pos 31U /*!< PSR: S Position */
  119. #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
  120. #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
  121. #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
  122. #define PSR_MM_Pos 9U /*!< PSR: MM Position */
  123. #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
  124. #define PSR_EE_Pos 8U /*!< PSR: EE Position */
  125. #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
  126. #define PSR_IC_Pos 7U /*!< PSR: IC Position */
  127. #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
  128. #define PSR_IE_Pos 6U /*!< PSR: IE Position */
  129. #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
  130. #define PSR_C_Pos 0U /*!< PSR: C Position */
  131. #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
  132. /**
  133. \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
  134. */
  135. typedef union {
  136. struct {
  137. uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
  138. uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
  139. uint32_t DE: 1; /*!< bit: 3 Data cache enable */
  140. uint32_t WB: 1; /*!< bit: 4 Cache write back */
  141. uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
  142. uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
  143. uint32_t BE: 1; /*!< bit: 7 Endian mode */
  144. uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
  145. uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
  146. uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
  147. uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
  148. uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
  149. uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
  150. uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
  151. } b; /*!< Structure Access by bit */
  152. uint32_t w; /*!< Type Access by whole register */
  153. } CCR_Type;
  154. /* CCR Register Definitions */
  155. #define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
  156. #define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
  157. #define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
  158. #define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
  159. #define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
  160. #define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
  161. #define CCR_WA_Pos 12u /*!< CCR: WA Position */
  162. #define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
  163. #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
  164. #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
  165. #define CCR_BE_Pos 7U /*!< CCR: BE Position */
  166. #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
  167. #define CCR_Z_Pos 6U /*!< CCR: Z Position */
  168. #define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
  169. #define CCR_RS_Pos 5U /*!< CCR: RS Position */
  170. #define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
  171. #define CCR_WB_Pos 4U /*!< CCR: WB Position */
  172. #define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
  173. #define CCR_DE_Pos 3U /*!< CCR: DE Position */
  174. #define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
  175. #define CCR_IE_Pos 2U /*!< CCR: IE Position */
  176. #define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
  177. #define CCR_MP_Pos 0U /*!< CCR: MP Position */
  178. #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
  179. /**
  180. \brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
  181. */
  182. typedef union {
  183. struct {
  184. uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
  185. uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
  186. uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
  187. uint32_t P: 1; /*!< bit: 31 TLBP instruction */
  188. } b;
  189. uint32_t w;
  190. } MIR_Type;
  191. /* MIR Register Definitions */
  192. #define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
  193. #define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
  194. #define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
  195. #define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
  196. #define MIR_Index_Pos 0 /*!< PRSR: Index Position */
  197. #define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
  198. /**
  199. \brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
  200. */
  201. typedef union {
  202. struct {
  203. uint32_t G: 1; /*!< bit: 0 Global enbale bit */
  204. uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
  205. uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
  206. uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
  207. uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
  208. uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
  209. uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
  210. uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
  211. uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
  212. } b;
  213. uint32_t w;
  214. } MEL_Type;
  215. /* MEL Register Definitions */
  216. #define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
  217. #define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
  218. #define MEL_B_Pos 6 /*!< MEL: B Position */
  219. #define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
  220. #define MEL_SO_Pos 5 /*!< MEL: SO Position */
  221. #define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
  222. #define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
  223. #define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
  224. #define MEL_C_Pos 3 /*!< MEL: C Position */
  225. #define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
  226. #define MEL_D_Pos 2 /*!< MEL: D Position */
  227. #define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
  228. #define MEL_V_Pos 1 /*!< MEL: V Position */
  229. #define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
  230. #define MEL_G_Pos 0 /*!< MEL: G Position */
  231. #define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
  232. /**
  233. \brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
  234. */
  235. typedef union {
  236. struct {
  237. uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
  238. uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
  239. uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
  240. } b;
  241. uint32_t w;
  242. } MEH_Type;
  243. /* MEH Register Definitions */
  244. #define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
  245. #define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
  246. #define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
  247. #define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
  248. /**
  249. \brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
  250. */
  251. typedef union {
  252. struct {
  253. uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
  254. uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
  255. uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
  256. } b;
  257. uint32_t w;
  258. } MPR_Type;
  259. /* MPR Register Definitions */
  260. #define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
  261. #define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
  262. /**
  263. \brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
  264. */
  265. typedef union {
  266. struct {
  267. uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
  268. uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
  269. uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
  270. uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
  271. uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
  272. uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
  273. uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
  274. uint32_t TLBR: 1; /*!< bit: 30 TLBR */
  275. uint32_t TLBP: 1; /*!< bit: 31 TLBP */
  276. } b;
  277. uint32_t w;
  278. } MCIR_Type;
  279. /* MCIR Register Definitions */
  280. #define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
  281. #define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
  282. #define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
  283. #define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
  284. #define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
  285. #define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
  286. #define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
  287. #define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
  288. #define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
  289. #define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
  290. #define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
  291. #define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
  292. #define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
  293. #define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
  294. #define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
  295. #define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
  296. /*@} end of group CSI_CORE */
  297. /**
  298. \ingroup CSI_core_register
  299. \defgroup CSI_CACHE
  300. \brief Type definitions for the cache Registers
  301. @{
  302. */
  303. /**
  304. \brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
  305. */
  306. typedef union {
  307. struct {
  308. uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
  309. uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
  310. uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
  311. uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
  312. uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
  313. uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
  314. uint32_t _reserved1: 8; /*!< bit: 8..15 Reserved */
  315. uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
  316. uint32_t _reserved2: 14; /*!< bit: 17..30 Reserved */
  317. uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
  318. } b; /*!< Structure Access by bit */
  319. uint32_t w; /*!< Type Access by whole register */
  320. } CFR_Type;
  321. #define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
  322. #define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
  323. #define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
  324. #define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
  325. #define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
  326. #define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
  327. #define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
  328. #define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
  329. #define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
  330. #define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
  331. #define CFR_INV_Pos 4U /*!< CFR: INV Position */
  332. #define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
  333. #define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
  334. #define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
  335. /* CFR Register Definitions */
  336. /*@} end of group CSI_CACHE */
  337. /**
  338. \ingroup CSI_core_register
  339. \defgroup CSI_CACHE
  340. \brief Type definitions for the cache Registers
  341. @{
  342. */
  343. #define SSEG0_BASE_ADDR 0x80000000
  344. #define CACHE_RANGE_MAX_SIZE 0x80000
  345. #define INS_CACHE (1 << 0)
  346. #define DATA_CACHE (1 << 1)
  347. #define CACHE_INV (1 << 4)
  348. #define CACHE_CLR (1 << 5)
  349. #define CACHE_OMS (1 << 6)
  350. #define CACHE_ITS (1 << 7)
  351. #define CACHE_LICF (1 << 31)
  352. #define L1_CACHE_SHIFT 4 /* 16 Bytes */
  353. #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
  354. /**
  355. \brief Mask and shift a bit field value for use in a register bit range.
  356. \param[in] field Name of the register bit field.
  357. \param[in] value Value of the bit field.
  358. \return Masked and shifted value.
  359. */
  360. #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
  361. /**
  362. \brief Mask and shift a register value to extract a bit filed value.
  363. \param[in] field Name of the register bit field.
  364. \param[in] value Value of register.
  365. \return Masked and shifted bit field value.
  366. */
  367. #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
  368. /*@} end of group CSI_core_bitfield */
  369. /*******************************************************************************
  370. * Hardware Abstraction Layer
  371. Core Function Interface contains:
  372. - Core VIC Functions
  373. - Core CORET Functions
  374. - Core Register Access Functions
  375. ******************************************************************************/
  376. /* The following MACROS handle generation of the register offset and byte masks */
  377. #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
  378. #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
  379. /* ########################## Cache functions #################################### */
  380. /**
  381. \ingroup CSI_Core_FunctionInterface
  382. \defgroup CSI_Core_CacheFunctions Cache Functions
  383. \brief Functions that configure Instruction and Data cache.
  384. @{
  385. */
  386. /**
  387. \brief Enable I-Cache
  388. \details Turns on I-Cache
  389. */
  390. __STATIC_INLINE void csi_icache_enable (void)
  391. {
  392. __set_CCR(__get_CCR() | 0x00000004);
  393. }
  394. /**
  395. \brief Disable I-Cache
  396. \details Turns off I-Cache
  397. */
  398. __STATIC_INLINE void csi_icache_disable (void)
  399. {
  400. __set_CCR(__get_CCR() & 0xFFFFFFFB);
  401. }
  402. /**
  403. \brief Invalidate I-Cache
  404. \details Invalidates I-Cache
  405. */
  406. __STATIC_INLINE void csi_icache_invalid (void)
  407. {
  408. __set_CFR(0x11);
  409. __set_CFR(INS_CACHE | CACHE_INV);
  410. }
  411. /**
  412. \brief Enable D-Cache
  413. \details Turns on D-Cache
  414. \note I-Cache also turns on.
  415. */
  416. __STATIC_INLINE void csi_dcache_enable (void)
  417. {
  418. __set_CCR(__get_CCR() | 0x00000008);
  419. }
  420. /**
  421. \brief Disable D-Cache
  422. \details Turns off D-Cache
  423. \note I-Cache also turns off.
  424. */
  425. __STATIC_INLINE void csi_dcache_disable (void)
  426. {
  427. __set_CCR(__get_CCR() & 0xFFFFFFF7);
  428. }
  429. /**
  430. \brief Invalidate D-Cache
  431. \details Invalidates D-Cache
  432. \note I-Cache also invalid
  433. */
  434. __STATIC_INLINE void csi_dcache_invalid (void)
  435. {
  436. __set_CFR(DATA_CACHE | CACHE_INV);
  437. }
  438. /**
  439. \brief Clean D-Cache
  440. \details Cleans D-Cache
  441. \note I-Cache also cleans
  442. */
  443. __STATIC_INLINE void csi_dcache_clean (void)
  444. {
  445. __set_CFR(DATA_CACHE | CACHE_CLR);
  446. }
  447. /**
  448. \brief Clean & Invalidate D-Cache
  449. \details Cleans and Invalidates D-Cache
  450. \note I-Cache also flush.
  451. */
  452. __STATIC_INLINE void csi_dcache_clean_invalid (void)
  453. {
  454. __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
  455. }
  456. __STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
  457. {
  458. if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
  459. __set_CFR(value);
  460. }
  461. if (value & INS_CACHE) {
  462. csi_icache_disable();
  463. }
  464. uint32_t i;
  465. for (i = start; i < end; i += L1_CACHE_BYTES) {
  466. __set_CIR(i);
  467. __set_CFR(CACHE_OMS | value);
  468. }
  469. if (end & (L1_CACHE_BYTES-1)) {
  470. __set_CIR(end);
  471. __set_CFR(CACHE_OMS | value);
  472. }
  473. if (value & INS_CACHE) {
  474. csi_icache_enable();
  475. }
  476. }
  477. /**
  478. \brief D-Cache Invalidate by address
  479. \details Invalidates D-Cache for the given address
  480. \param[in] addr address (aligned to 16-byte boundary)
  481. \param[in] dsize size of memory block (in number of bytes)
  482. */
  483. __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
  484. {
  485. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
  486. }
  487. /**
  488. \brief D-Cache Clean by address
  489. \details Cleans D-Cache for the given address
  490. \param[in] addr address (aligned to 16-byte boundary)
  491. \param[in] dsize size of memory block (in number of bytes)
  492. */
  493. __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
  494. {
  495. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
  496. }
  497. /**
  498. \brief D-Cache Clean and Invalidate by address
  499. \details Cleans and invalidates D_Cache for the given address
  500. \param[in] addr address (aligned to 16-byte boundary)
  501. \param[in] dsize size of memory block (in number of bytes)
  502. */
  503. __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
  504. {
  505. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
  506. }
  507. /*@} end of CSI_Core_CacheFunctions */
  508. /* ########################## MMU functions #################################### */
  509. /**
  510. \ingroup CSI_Core_FunctionInterface
  511. \defgroup CSI_Core_MMUFunctions MMU Functions
  512. \brief Functions that configure MMU.
  513. @{
  514. */
  515. typedef struct {
  516. uint32_t global: 1; /* tlb page global access. */
  517. uint32_t valid: 1; /* tlb page valid */
  518. uint32_t writeable: 1; /* tlb page writeable */
  519. uint32_t cacheable: 1; /* tlb page cacheable*/
  520. uint32_t is_secure: 1; /* tlb page security access */
  521. uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
  522. uint32_t bufferable: 1; /* tlb page bufferable */
  523. } page_attr_t;
  524. typedef enum {
  525. PAGE_SIZE_4KB = 0x000,
  526. PAGE_SIZE_16KB = 0x003,
  527. PAGE_SIZE_64KB = 0x00F,
  528. PAGE_SIZE_256KB = 0x03F,
  529. PAGE_SIZE_1MB = 0x0FF,
  530. PAGE_SIZE_4MB = 0x3FF,
  531. PAGE_SIZE_16MB = 0xFFF
  532. } page_size_e;
  533. /**
  534. \brief enable mmu
  535. \details
  536. */
  537. __STATIC_INLINE void csi_mmu_enable(void)
  538. {
  539. __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
  540. }
  541. /**
  542. \brief disable mmu
  543. \details
  544. */
  545. __STATIC_INLINE void csi_mmu_disable(void)
  546. {
  547. __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
  548. }
  549. /**
  550. \brief create page with feature.
  551. \details
  552. \param [in] vaddr virtual address.
  553. \param [in] paddr physical address.
  554. \param [in] asid address sapce id (default: 0).
  555. \param [in] attr \ref page_attr_t. tlb page attribute.
  556. */
  557. __STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
  558. {
  559. MPR_Type pgmask;
  560. MEH_Type meh;
  561. MEL_Type mel;
  562. uint32_t vaddr_bit;
  563. uint32_t page_feature = 0;
  564. page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
  565. attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
  566. attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
  567. attr.bufferable << MEL_B_Pos;
  568. pgmask.w = __get_MPR();
  569. vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
  570. meh.b.ASID = (uint8_t)asid;
  571. meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
  572. __set_MEH(meh.w);
  573. __set_MCIR(1u << MCIR_TLBP_Pos);
  574. mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
  575. if (vaddr & (1 << vaddr_bit)) {
  576. __set_MEL1(mel.w);
  577. }
  578. else {
  579. __set_MEL0(mel.w);
  580. }
  581. if (__get_MIR() & (1 << MIR_P_Pos)) {
  582. __set_MCIR(1u << MCIR_TLBWR_Pos);
  583. } else {
  584. __set_MCIR(1u << MCIR_TLBWI_Pos);
  585. }
  586. }
  587. /**
  588. \brief enble mmu
  589. \details
  590. \param [in] size tlb page size.
  591. */
  592. __STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
  593. {
  594. MPR_Type pgmask;
  595. pgmask.b.page_mask = size;
  596. __set_MPR(pgmask.w);
  597. }
  598. /**
  599. \brief read MEH, MEL0, MEL1 by tlb index.
  600. \details
  601. \param [in] index tlb index(0, 1, 2, ...)
  602. \param [out] meh pointer to variable for retrieving MEH.
  603. \param [out] mel0 pointer to variable for retrieving MEL0.
  604. \param [out] mel1 pointer to variable for retrieving MEL1.
  605. */
  606. __STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
  607. {
  608. MIR_Type mir;
  609. if (meh == NULL || mel0 == NULL || mel1 == NULL) {
  610. return;
  611. }
  612. mir.b.Index = index;
  613. __set_MIR(mir.w);
  614. __set_MCIR(1u << MCIR_TLBR_Pos);
  615. *meh = __get_MEH();
  616. *mel0 = __get_MEL0();
  617. *mel1 = __get_MEL1();
  618. }
  619. /**
  620. \brief flush all mmu tlb.
  621. \details
  622. */
  623. __STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
  624. {
  625. __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
  626. }
  627. /**
  628. \brief flush mmu tlb by index.
  629. \details
  630. */
  631. __STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
  632. {
  633. MIR_Type mir;
  634. mir.b.Index = index;
  635. __set_MIR(mir.w);
  636. __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
  637. }
  638. /**
  639. \brief flush mmu tlb by virtual address.
  640. \details
  641. */
  642. __STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
  643. {
  644. __set_MEH(vaddr | (asid & MEH_ASID_Msk));
  645. __set_MCIR(1u << MCIR_TLBP_Pos);
  646. if (__get_MIR() & (1 << MIR_P_Pos)) {
  647. return;
  648. } else {
  649. __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
  650. }
  651. }
  652. /*@} end of CSI_Core_MMUFunctions */
  653. /* ################################## IRQ Functions ############################################ */
  654. /**
  655. \brief Save the Irq context
  656. \details save the psr result before disable irq.
  657. \param [in] irq_num External interrupt number. Value cannot be negative.
  658. */
  659. __STATIC_INLINE uint32_t csi_irq_save(void)
  660. {
  661. uint32_t result;
  662. result = __get_PSR();
  663. __disable_irq();
  664. return(result);
  665. }
  666. /**
  667. \brief Restore the Irq context
  668. \details restore saved primask state.
  669. \param [in] irq_state psr irq state.
  670. */
  671. __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
  672. {
  673. __set_PSR(irq_state);
  674. }
  675. /*@} end of IRQ Functions */
  676. #ifdef __cplusplus
  677. }
  678. #endif
  679. #endif /* __CORE_CK807_H_DEPENDANT */
  680. #endif /* __CSI_GENERIC */