core_ck610.h 35 KB

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  1. /*
  2. * Copyright (C) 2017-2019 Alibaba Group Holding Limited
  3. */
  4. /******************************************************************************
  5. * @file core_ck610.h
  6. * @brief CSI CK610 Core Peripheral Access Layer Header File
  7. * @version V1.0
  8. * @date 02. June 2017
  9. ******************************************************************************/
  10. #ifndef __CORE_CK610_H_GENERIC
  11. #define __CORE_CK610_H_GENERIC
  12. #include <stdint.h>
  13. #include <stdio.h>
  14. #ifdef __cplusplus
  15. extern "C" {
  16. #endif
  17. /*******************************************************************************
  18. * CSI definitions
  19. ******************************************************************************/
  20. /**
  21. \ingroup Ck610
  22. @{
  23. */
  24. /* CSI CK610 definitions */
  25. #define __CK610_CSI_VERSION_MAIN (0x01U) /*!< [31:16] CSI HAL main version */
  26. #define __CK610_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
  27. #define __CK610_CSI_VERSION ((__CK610_CSI_VERSION_MAIN << 16U) | \
  28. __CK610_CSI_VERSION_SUB ) /*!< CSI HAL version number */
  29. #define __CK610 (0x01U) /*!< CK610 Core */
  30. /** __FPU_USED indicates whether an FPU is used or not.
  31. This core does not support an FPU at all
  32. */
  33. #define __FPU_USED 1U
  34. #if defined ( __GNUC__ )
  35. #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  36. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  37. #endif
  38. #endif
  39. #ifdef __cplusplus
  40. }
  41. #endif
  42. #endif /* __CORE_CK610_H_GENERIC */
  43. #ifndef __CSI_GENERIC
  44. #ifndef __CORE_CK610_H_DEPENDANT
  45. #define __CORE_CK610_H_DEPENDANT
  46. #ifdef __cplusplus
  47. extern "C" {
  48. #endif
  49. /* check device defines and use defaults */
  50. #ifndef __CK610_REV
  51. #define __CK610_REV 0x0000U
  52. #endif
  53. #ifndef __GSR_GCR_PRESENT
  54. #define __GSR_GCR_PRESENT 0U
  55. #endif
  56. #ifndef __MPU_PRESENT
  57. #define __MPU_PRESENT 0U
  58. #endif
  59. #ifndef __ICACHE_PRESENT
  60. #define __ICACHE_PRESENT 1U
  61. #endif
  62. #ifndef __DCACHE_PRESENT
  63. #define __DCACHE_PRESENT 1U
  64. #endif
  65. #include <csi_gcc.h>
  66. /* IO definitions (access restrictions to peripheral registers) */
  67. /**
  68. \defgroup CSI_glob_defs CSI Global Defines
  69. <strong>IO Type Qualifiers</strong> are used
  70. \li to specify the access to peripheral variables.
  71. \li for automatic generation of peripheral register debug information.
  72. */
  73. #ifdef __cplusplus
  74. #define __I volatile /*!< Defines 'read only' permissions */
  75. #else
  76. #define __I volatile const /*!< Defines 'read only' permissions */
  77. #endif
  78. #define __O volatile /*!< Defines 'write only' permissions */
  79. #define __IO volatile /*!< Defines 'read / write' permissions */
  80. /* following defines should be used for structure members */
  81. #define __IM volatile const /*! Defines 'read only' structure member permissions */
  82. #define __OM volatile /*! Defines 'write only' structure member permissions */
  83. #define __IOM volatile /*! Defines 'read / write' structure member permissions */
  84. /*@} end of group CK610 */
  85. /*******************************************************************************
  86. * Register Abstraction
  87. Core Register contain:
  88. - Core Register
  89. - Core MGU Register
  90. - Core MMU Register
  91. ******************************************************************************/
  92. /**
  93. \defgroup CSI_core_register Defines and Type Definitions
  94. \brief Type definitions and defines for CK610 processor based devices.
  95. */
  96. /**
  97. \brief Access Processor Status Register(PSR)struct definition.
  98. */
  99. typedef union {
  100. struct {
  101. uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
  102. uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
  103. uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
  104. uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
  105. uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
  106. uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
  107. uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
  108. uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
  109. uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
  110. uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
  111. uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
  112. uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
  113. uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
  114. uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
  115. uint32_t CPID: 4; /*!< bit: 24..27 Number of processor currently running */
  116. uint32_t _reserved3: 3; /*!< bit: 28..30 Reserved */
  117. uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
  118. } b; /*!< Structure Access by bit */
  119. uint32_t w; /*!< Type Access by whole register */
  120. } PSR_Type;
  121. /* PSR Register Definitions */
  122. #define PSR_S_Pos 31U /*!< PSR: S Position */
  123. #define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
  124. #define PSR_CPID_Pos 24U /*!< PSR: CPID Position */
  125. #define PSR_CPID_Msk (0xFUL << PSR_CPID_Pos) /*!< PSR: CPID Mask */
  126. #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
  127. #define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
  128. #define PSR_TM_Pos 14U /*!< PSR: TM Position */
  129. #define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
  130. #define PSR_TP_Pos 13U /*!< PSR: TP Position */
  131. #define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
  132. #define PSR_TE_Pos 12U /*!< PSR: TE Position */
  133. #define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
  134. #define PSR_MM_Pos 9U /*!< PSR: MM Position */
  135. #define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
  136. #define PSR_EE_Pos 8U /*!< PSR: EE Position */
  137. #define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
  138. #define PSR_IC_Pos 7U /*!< PSR: IC Position */
  139. #define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
  140. #define PSR_IE_Pos 6U /*!< PSR: IE Position */
  141. #define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
  142. #define PSR_FE_Pos 4U /*!< PSR: FE Position */
  143. #define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
  144. #define PSR_AF_Pos 1U /*!< PSR: AF Position */
  145. #define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
  146. #define PSR_C_Pos 0U /*!< PSR: C Position */
  147. #define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
  148. /**
  149. \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
  150. */
  151. typedef union {
  152. struct {
  153. uint32_t MP: 2; /*!< bit: 0..1 Memory protection settings */
  154. uint32_t IE: 1; /*!< bit: 2 Endian mode */
  155. uint32_t DE: 1; /*!< bit: 3 Endian mode */
  156. uint32_t WB: 1; /*!< bit: 4 Endian mode */
  157. uint32_t RS: 1; /*!< bit: 5 Endian mode */
  158. uint32_t Z: 1; /*!< bit: 6 Endian mode */
  159. uint32_t BE: 1; /*!< bit: 7 Endian mode */
  160. uint32_t SCK: 3; /*!< bit: 8..10 The clock ratio of the system and the processor */
  161. uint32_t _reserved0: 21; /*!< bit: 11..31 Reserved */
  162. } b; /*!< Structure Access by bit */
  163. uint32_t w; /*!< Type Access by whole register */
  164. } CCR_Type;
  165. /* CCR Register Definitions */
  166. #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
  167. #define CCR_SCK_Msk (0x7UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
  168. #define CCR_BE_Pos 7U /*!< CCR: BE Position */
  169. #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
  170. #define CCR_Z_Pos 6U /*!< CCR: Z Position */
  171. #define CCR_Z_Msk (0x1UL << CCR_Z_Pos) /*!< CCR: Z Mask */
  172. #define CCR_RS_Pos 5U /*!< CCR: RS Position */
  173. #define CCR_RS_Msk (0x1UL << CCR_RS_Pos) /*!< CCR: RS Mask */
  174. #define CCR_WB_Pos 4U /*!< CCR: WB Position */
  175. #define CCR_WB_Msk (0x1UL << CCR_WB_Pos) /*!< CCR: WB Mask */
  176. #define CCR_DE_Pos 3U /*!< CCR: DE Position */
  177. #define CCR_DE_Msk (0x1UL << CCR_DE_Pos) /*!< CCR: DE Mask */
  178. #define CCR_IE_Pos 2U /*!< CCR: IE Position */
  179. #define CCR_IE_Msk (0x1UL << CCR_IE_Pos) /*!< CCR: IE Mask */
  180. #define CCR_MP_Pos 0U /*!< CCR: MP Position */
  181. #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
  182. /**
  183. \brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
  184. */
  185. typedef union {
  186. struct {
  187. uint32_t C0: 1; /*!< bit: 0 Cacheable setting */
  188. uint32_t C1: 1; /*!< bit: 1 Cacheable setting */
  189. uint32_t C2: 1; /*!< bit: 2 Cacheable setting */
  190. uint32_t C3: 1; /*!< bit: 3 Cacheable setting */
  191. uint32_t _reserved0: 4; /*!< bit: 4.. 7 Reserved */
  192. uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
  193. uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
  194. uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
  195. uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
  196. uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
  197. } b; /*!< Structure Access by bit */
  198. uint32_t w; /*!< Type Access by whole register */
  199. } CAPR_Type;
  200. /* CAPR Register Definitions */
  201. #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
  202. #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
  203. #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
  204. #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
  205. #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
  206. #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
  207. #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
  208. #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
  209. #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
  210. #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
  211. #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
  212. #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
  213. #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
  214. #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
  215. #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
  216. #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
  217. /**
  218. \brief Consortium definition for accessing control register(PACR, CR<20,0>).
  219. */
  220. typedef union {
  221. struct {
  222. uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
  223. uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
  224. uint32_t _reserved0: 6; /*!< bit: 6.. 11 Reserved */
  225. uint32_t base_addr: 20; /*!< bit: 10..31 The high position of the address of a protected area */
  226. } b; /*!< Structure Access by bit */
  227. uint32_t w; /*!< Type Access by whole register */
  228. } PACR_Type;
  229. /* PACR Register Definitions */
  230. #define PACR_BASE_ADDR_Pos 12U /*!< PACR: base_addr Position */
  231. #define PACR_BASE_ADDR_Msk (0xFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
  232. #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
  233. #define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
  234. #define PACR_E_Pos 0U /*!< PACR: E Position */
  235. #define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
  236. /**
  237. \brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
  238. */
  239. typedef union {
  240. struct {
  241. uint32_t RID: 2; /*!< bit: 0.. 1 Protected area index value */
  242. uint32_t _reserved0: 30; /*!< bit: 2..31 Reserved */
  243. } b; /*!< Structure Access by bit */
  244. uint32_t w; /*!< Type Access by whole register */
  245. } PRSR_Type;
  246. /* PRSR Register Definitions */
  247. #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
  248. #define PRSR_RID_Msk (0x3UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
  249. /**
  250. \brief Consortium definition for accessing mmu index register(MIR,CP15_CR0).
  251. */
  252. typedef union {
  253. struct {
  254. uint32_t Index: 10;
  255. uint32_t _reserved: 20;
  256. uint32_t TF: 1;
  257. uint32_t P: 1;
  258. } b;
  259. uint32_t w;
  260. } MIR_Type;
  261. /* MIR Register Definitions */
  262. #define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
  263. #define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
  264. #define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
  265. #define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
  266. #define MIR_Index_Pos 0 /*!< PRSR: Index Position */
  267. #define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
  268. /**
  269. \brief Consortium definition for accessing mmu entry of high physical address register(MEL, CP15_CR2 and CP15_CR3).
  270. */
  271. typedef union {
  272. struct {
  273. uint32_t G: 1;
  274. uint32_t V: 1;
  275. uint32_t D: 1;
  276. uint32_t C: 3;
  277. uint32_t PFN: 20;
  278. uint32_t _reserved: 6;
  279. } b;
  280. uint32_t w;
  281. } MEL_Type;
  282. /* MEL Register Definitions */
  283. #define MEL_PFN_Pos 6 /*!< MEL: PFN Position */
  284. #define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
  285. #define MEL_C_Pos 3 /*!< MEL: C Position */
  286. #define MEL_C_Msk (0x7UL << MEL_C_Pos) /*!< MEL: C Mask */
  287. #define MEL_D_Pos 2 /*!< MEL: D Position */
  288. #define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
  289. #define MEL_V_Pos 1 /*!< MEL: V Position */
  290. #define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
  291. #define MEL_G_Pos 0 /*!< MEL: G Position */
  292. #define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
  293. /**
  294. \brief Consortium definition for accessing mmu entry of high physical address register(MEH, CP15_CR4).
  295. */
  296. typedef union {
  297. struct {
  298. uint32_t ASID :8;
  299. uint32_t _reserved :4;
  300. uint32_t VPN :20;
  301. } b;
  302. uint32_t w;
  303. } MEH_Type;
  304. /* MEH Register Definitions */
  305. #define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
  306. #define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
  307. #define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
  308. #define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
  309. /**
  310. \brief Consortium definition for accessing mmu entry of high physical address register(MPR, CP15_CR6).
  311. */
  312. typedef union {
  313. struct {
  314. uint32_t _reserved0: 13;
  315. uint32_t page_mask: 12;
  316. uint32_t _reserved1: 7;
  317. } b;
  318. uint32_t w;
  319. } MPR_Type;
  320. /* MPR Register Definitions */
  321. #define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
  322. #define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
  323. /**
  324. \brief Consortium definition for accessing mmu entry of high physical address register(MCIR, CP15_CR8).
  325. */
  326. typedef union {
  327. struct {
  328. uint32_t ASID: 8;
  329. uint32_t _reserved: 17;
  330. uint32_t TLBINV_INDEX: 1;
  331. uint32_t TLBINV_ALL: 1;
  332. uint32_t TLBINV: 1;
  333. uint32_t TLBWR: 1;
  334. uint32_t TLBWI: 1;
  335. uint32_t TLBR: 1;
  336. uint32_t TLBP: 1;
  337. } b;
  338. uint32_t w;
  339. } MCIR_Type;
  340. /* MCIR Register Definitions */
  341. #define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
  342. #define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
  343. #define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
  344. #define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
  345. #define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
  346. #define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
  347. #define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
  348. #define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
  349. #define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
  350. #define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
  351. #define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
  352. #define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
  353. #define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
  354. #define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
  355. #define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
  356. #define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
  357. /*@} end of group CSI_CORE */
  358. /**
  359. \ingroup CSI_core_register
  360. \defgroup CSI_CACHE
  361. \brief Type definitions for the cache Registers
  362. @{
  363. */
  364. #define SSEG0_BASE_ADDR 0x80000000
  365. #define CACHE_RANGE_MAX_SIZE 0x80000
  366. #define INS_CACHE (1 << 0)
  367. #define DATA_CACHE (1 << 1)
  368. #define CACHE_INV (1 << 4)
  369. #define CACHE_CLR (1 << 5)
  370. #define CACHE_OMS (1 << 6)
  371. #define CACHE_ITS (1 << 7)
  372. #define CACHE_LICF (1 << 31)
  373. #define L1_CACHE_SHIFT 4 /* 16 Bytes */
  374. #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
  375. /**
  376. \brief Mask and shift a bit field value for use in a register bit range.
  377. \param[in] field Name of the register bit field.
  378. \param[in] value Value of the bit field.
  379. \return Masked and shifted value.
  380. */
  381. #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
  382. /**
  383. \brief Mask and shift a register value to extract a bit filed value.
  384. \param[in] field Name of the register bit field.
  385. \param[in] value Value of register.
  386. \return Masked and shifted bit field value.
  387. */
  388. #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
  389. /*@} end of group CSI_core_bitfield */
  390. /*******************************************************************************
  391. * Hardware Abstraction Layer
  392. Core Function Interface contains:
  393. - Core VIC Functions
  394. - Core CORET Functions
  395. - Core Register Access Functions
  396. ******************************************************************************/
  397. /* ########################## Cache functions #################################### */
  398. /**
  399. \ingroup CSI_Core_FunctionInterface
  400. \defgroup CSI_Core_CacheFunctions Cache Functions
  401. \brief Functions that configure Instruction and Data cache.
  402. @{
  403. */
  404. /**
  405. \brief Enable I-Cache
  406. \details Turns on I-Cache
  407. */
  408. __STATIC_INLINE void csi_icache_enable (void)
  409. {
  410. __set_CCR(__get_CCR() | 0x00000004);
  411. }
  412. /**
  413. \brief Disable I-Cache
  414. \details Turns off I-Cache
  415. */
  416. __STATIC_INLINE void csi_icache_disable (void)
  417. {
  418. __set_CCR(__get_CCR() & 0xFFFFFFFB);
  419. }
  420. /**
  421. \brief Invalidate I-Cache
  422. \details Invalidates I-Cache
  423. */
  424. __STATIC_INLINE void csi_icache_invalid (void)
  425. {
  426. __set_CFR(0x11);
  427. __set_CFR(INS_CACHE | CACHE_INV);
  428. }
  429. /**
  430. \brief Enable D-Cache
  431. \details Turns on D-Cache
  432. \note I-Cache also turns on.
  433. */
  434. __STATIC_INLINE void csi_dcache_enable (void)
  435. {
  436. __set_CCR(__get_CCR() | 0x00000008);
  437. }
  438. /**
  439. \brief Disable D-Cache
  440. \details Turns off D-Cache
  441. \note I-Cache also turns off.
  442. */
  443. __STATIC_INLINE void csi_dcache_disable (void)
  444. {
  445. __set_CCR(__get_CCR() & 0xFFFFFFF7);
  446. }
  447. /**
  448. \brief Invalidate D-Cache
  449. \details Invalidates D-Cache
  450. \note I-Cache also invalid
  451. */
  452. __STATIC_INLINE void csi_dcache_invalid (void)
  453. {
  454. __set_CFR(DATA_CACHE | CACHE_INV);
  455. }
  456. /**
  457. \brief Clean D-Cache
  458. \details Cleans D-Cache
  459. \note I-Cache also cleans
  460. */
  461. __STATIC_INLINE void csi_dcache_clean (void)
  462. {
  463. __set_CFR(DATA_CACHE | CACHE_CLR);
  464. }
  465. /**
  466. \brief Clean & Invalidate D-Cache
  467. \details Cleans and Invalidates D-Cache
  468. \note I-Cache also flush.
  469. */
  470. __STATIC_INLINE void csi_dcache_clean_invalid (void)
  471. {
  472. __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
  473. }
  474. __STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
  475. {
  476. if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
  477. __set_CFR(value);
  478. }
  479. if (value & INS_CACHE) {
  480. csi_icache_disable();
  481. }
  482. uint32_t i;
  483. for (i = start; i < end; i += L1_CACHE_BYTES) {
  484. __set_CIR(i);
  485. __set_CFR(CACHE_OMS | value);
  486. }
  487. if (end & (L1_CACHE_BYTES-1)) {
  488. __set_CIR(end);
  489. __set_CFR(CACHE_OMS | value);
  490. }
  491. if (value & INS_CACHE) {
  492. csi_icache_enable();
  493. }
  494. }
  495. /**
  496. \brief D-Cache Invalidate by address
  497. \details Invalidates D-Cache for the given address
  498. \param[in] addr address (aligned to 16-byte boundary)
  499. \param[in] dsize size of memory block (in number of bytes)
  500. */
  501. __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
  502. {
  503. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
  504. }
  505. /**
  506. \brief D-Cache Clean by address
  507. \details Cleans D-Cache for the given address
  508. \param[in] addr address (aligned to 16-byte boundary)
  509. \param[in] dsize size of memory block (in number of bytes)
  510. */
  511. __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
  512. {
  513. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
  514. }
  515. /**
  516. \brief D-Cache Clean and Invalidate by address
  517. \details Cleans and invalidates D_Cache for the given address
  518. \param[in] addr address (aligned to 16-byte boundary)
  519. \param[in] dsize size of memory block (in number of bytes)
  520. */
  521. __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
  522. {
  523. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
  524. }
  525. /*@} end of CSI_Core_CacheFunctions */
  526. /* ########################## MMU functions #################################### */
  527. /**
  528. \ingroup CSI_Core_FunctionInterface
  529. \defgroup CSI_Core_MMUFunctions MMU Functions
  530. \brief Functions that configure MMU.
  531. @{
  532. */
  533. typedef struct {
  534. uint32_t global: 1; /* tlb page global access. */
  535. uint32_t valid: 1; /* tlb page valid */
  536. uint32_t writeable: 1; /* tlb page writeable */
  537. uint32_t cacheable: 1; /* tlb page cacheable*/
  538. } page_attr_t;
  539. typedef enum {
  540. PAGE_SIZE_4KB = 0x000,
  541. PAGE_SIZE_16KB = 0x003,
  542. PAGE_SIZE_64KB = 0x00F,
  543. PAGE_SIZE_256KB = 0x03F,
  544. PAGE_SIZE_1MB = 0x0FF,
  545. PAGE_SIZE_4MB = 0x3FF,
  546. PAGE_SIZE_16MB = 0xFFF
  547. } page_size_e;
  548. /**
  549. \brief enable mmu
  550. \details
  551. */
  552. __STATIC_INLINE void csi_mmu_enable(void)
  553. {
  554. __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
  555. }
  556. /**
  557. \brief disable mmu
  558. \details
  559. */
  560. __STATIC_INLINE void csi_mmu_disable(void)
  561. {
  562. __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
  563. }
  564. /**
  565. \brief create page with feature.
  566. \details
  567. \param [in] vaddr virtual address.
  568. \param [in] paddr physical address.
  569. \param [in] asid address sapce id (default: 0).
  570. \param [in] attr \ref page_attr_t. tlb page attribute.
  571. */
  572. __STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
  573. {
  574. MPR_Type pgmask;
  575. MEL_Type mel;
  576. MEH_Type meh;
  577. uint32_t vaddr_bit = 0;
  578. uint32_t page_feature = 0;
  579. page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
  580. attr.writeable << MEL_D_Pos | (attr.cacheable | 0x2) << MEL_C_Pos;
  581. pgmask.w = __FF1(__get_MPR());
  582. vaddr_bit = (pgmask.w == 32 ? 12 : (31 - pgmask.w));
  583. meh.b.ASID = asid;
  584. meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
  585. __set_MEH(meh.w);
  586. __set_MCIR(1u << MCIR_TLBP_Pos);
  587. mel.w = (((paddr >> 6) & ~(pgmask.b.page_mask << 6)) | page_feature);
  588. if (vaddr & (1 << vaddr_bit)) {
  589. __set_MEL1(mel.w);
  590. } else {
  591. __set_MEL0(mel.w);
  592. }
  593. if (__get_MIR() & (1 << MIR_P_Pos)) {
  594. __set_MCIR(1u << MCIR_TLBWR_Pos);
  595. } else {
  596. __set_MCIR(1u << MCIR_TLBWI_Pos);
  597. }
  598. }
  599. /**
  600. \brief enble mmu
  601. \details
  602. \param [in] size tlb page size.
  603. */
  604. __STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
  605. {
  606. MPR_Type mpr;
  607. mpr.w = __get_MPR();
  608. mpr.b.page_mask = size;
  609. __set_MPR(mpr.w);
  610. }
  611. /**
  612. \brief read MEH, MEL0, MEL1 by tlb index.
  613. \details
  614. \param [in] index tlb index(0, 1, 2, ...)
  615. \param [out] meh pointer to variable for retrieving MEH.
  616. \param [out] mel0 pointer to variable for retrieving MEL0.
  617. \param [out] mel1 pointer to variable for retrieving MEL1.
  618. */
  619. __STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
  620. {
  621. MIR_Type mir;
  622. if (meh == NULL || mel0 == NULL || mel1 == NULL) {
  623. return;
  624. }
  625. mir.b.Index = index;
  626. __set_MIR(mir.w);
  627. __set_MCIR(1u << MCIR_TLBR_Pos);
  628. *meh = __get_MEH();
  629. *mel0 = __get_MEL0();
  630. *mel1 = __get_MEL1();
  631. }
  632. /**
  633. \brief flush all mmu tlb.
  634. \details
  635. */
  636. __STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
  637. {
  638. __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
  639. }
  640. /**
  641. \brief flush mmu tlb by index.
  642. \details
  643. */
  644. __STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
  645. {
  646. MIR_Type mir;
  647. mir.b.Index = index;
  648. __set_MIR(mir.w);
  649. __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
  650. }
  651. /**
  652. \brief flush mmu tlb by virtual address.
  653. \details
  654. */
  655. __STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
  656. {
  657. __set_MEH(vaddr | (asid & MEH_ASID_Msk));
  658. __set_MCIR(__get_MCIR() | (1 << MCIR_TLBP_Pos));
  659. if (__get_MIR() & (1 << MIR_P_Pos)) {
  660. return;
  661. } else {
  662. __set_MCIR(__get_MCIR() | (1 << MCIR_TLBINV_INDEX_Pos));
  663. }
  664. }
  665. /*@} end of CSI_Core_MMUFunctions */
  666. /* ########################## MPU functions #################################### */
  667. /**
  668. \ingroup CSI_Core_FunctionInterface
  669. \defgroup CSI_Core_MPUFunctions MPU Functions
  670. \brief Functions that configure MPU.
  671. @{
  672. */
  673. typedef enum {
  674. REGION_SIZE_4KB = 0xB,
  675. REGION_SIZE_8KB = 0xC,
  676. REGION_SIZE_16KB = 0xD,
  677. REGION_SIZE_32KB = 0xE,
  678. REGION_SIZE_64KB = 0xF,
  679. REGION_SIZE_128KB = 0x10,
  680. REGION_SIZE_256KB = 0x11,
  681. REGION_SIZE_512KB = 0x12,
  682. REGION_SIZE_1MB = 0x13,
  683. REGION_SIZE_2MB = 0x14,
  684. REGION_SIZE_4MB = 0x15,
  685. REGION_SIZE_8MB = 0x16,
  686. REGION_SIZE_16MB = 0x17,
  687. REGION_SIZE_32MB = 0x18,
  688. REGION_SIZE_64MB = 0x19,
  689. REGION_SIZE_128MB = 0x1A,
  690. REGION_SIZE_256MB = 0x1B,
  691. REGION_SIZE_512MB = 0x1C,
  692. REGION_SIZE_1GB = 0x1D,
  693. REGION_SIZE_2GB = 0x1E,
  694. REGION_SIZE_4GB = 0x1F
  695. } region_size_e;
  696. typedef enum {
  697. AP_BOTH_INACCESSIBLE = 0,
  698. AP_SUPER_RW_USER_INACCESSIBLE,
  699. AP_SUPER_RW_USER_RDONLY,
  700. AP_BOTH_RW
  701. } access_permission_e;
  702. typedef struct {
  703. access_permission_e ap: 2; /* super user and normal user access.*/
  704. uint32_t c: 1; /* cacheable */
  705. } mpu_region_attr_t;
  706. /**
  707. \brief enable mpu
  708. \details
  709. */
  710. __STATIC_INLINE void csi_mpu_enable(void)
  711. {
  712. __set_CCR(__get_CCR() | CCR_MP_Msk);
  713. }
  714. /**
  715. \brief disable mpu
  716. \details
  717. */
  718. __STATIC_INLINE void csi_mpu_disable(void)
  719. {
  720. __set_CCR(__get_CCR() & (~CCR_MP_Msk));
  721. }
  722. /**
  723. \brief configure memory protected region.
  724. \details
  725. \param [in] idx memory protected region (0, 1, 2, 3.).
  726. \param [in] base_addr base address must be aligned with page size.
  727. \param [in] size \ref region_size_e. memory protected region size.
  728. \param [in] attr \ref region_size_t. memory protected region attribute.
  729. \param [in] enable enable or disable memory protected region.
  730. */
  731. __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
  732. mpu_region_attr_t attr, uint32_t enable)
  733. {
  734. if (idx > 3) {
  735. return;
  736. }
  737. CAPR_Type capr;
  738. PACR_Type pacr;
  739. PRSR_Type prsr;
  740. capr.w = __get_CAPR();
  741. pacr.w = __get_PACR();
  742. prsr.w = __get_PRSR();
  743. pacr.b.base_addr = (base_addr >> PACR_BASE_ADDR_Pos) & (0xFFFFF);
  744. prsr.b.RID = idx;
  745. __set_PRSR(prsr.w);
  746. if (size != REGION_SIZE_4KB) {
  747. pacr.w &= ~(((1u << (size -11)) - 1) << 12);
  748. }
  749. pacr.b.size = size;
  750. capr.w = (0xFFFFFFFE & capr.w) | (attr.c << idx);
  751. capr.w = ((~((0x3) << (2*idx + 8))) & capr.w) | (attr.ap << (2*idx + 8));
  752. __set_CAPR(capr.w);
  753. pacr.b.E = enable;
  754. __set_PACR(pacr.w);
  755. }
  756. /**
  757. \brief enable mpu region by idx.
  758. \details
  759. \param [in] idx memory protected region (0, 1, 2, 3.).
  760. */
  761. __STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
  762. {
  763. if (idx > 3) {
  764. return;
  765. }
  766. __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
  767. __set_PACR(__get_PACR() | PACR_E_Msk);
  768. }
  769. /**
  770. \brief disable mpu region by idx.
  771. \details
  772. \param [in] idx memory protected region (0, 1, 2, 3.).
  773. */
  774. __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
  775. {
  776. if (idx > 3) {
  777. return;
  778. }
  779. __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
  780. __set_PACR(__get_PACR() & (~PACR_E_Msk));
  781. }
  782. /*@} end of CSI_Core_MMUFunctions */
  783. /*@} */
  784. #ifdef __cplusplus
  785. }
  786. #endif
  787. #endif /* __CORE_CK610_H_DEPENDANT */
  788. #endif /* __CSI_GENERIC */