core_810.h 35 KB

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  1. /*
  2. * Copyright (C) 2017-2019 Alibaba Group Holding Limited
  3. */
  4. /******************************************************************************
  5. * @file core_ck810.h
  6. * @brief CSI CK810 Core Peripheral Access Layer Header File
  7. * @version V1.0
  8. * @date 26. Jan 2018
  9. ******************************************************************************/
  10. #ifndef __CORE_CK810_H_GENERIC
  11. #define __CORE_CK810_H_GENERIC
  12. #include <stdint.h>
  13. #ifdef __cplusplus
  14. extern "C" {
  15. #endif
  16. /*******************************************************************************
  17. * CSI definitions
  18. ******************************************************************************/
  19. /**
  20. \ingroup CK810
  21. @{
  22. */
  23. /* CSI CK810 definitions */
  24. #define __CK810_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
  25. #define __CK810_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
  26. #define __CK810_CSI_VERSION ((__CK810_CSI_VERSION_MAIN << 16U) | \
  27. __CK810_CSI_VERSION_SUB ) /*!< CSI HAL version number */
  28. #ifndef __CK810
  29. #define __CK810 (0x0aU) /*!< CK810 Core */
  30. #endif
  31. /** __FPU_USED indicates whether an FPU is used or not.
  32. */
  33. #define __FPU_USED 1U
  34. #if defined ( __GNUC__ )
  35. #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  36. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  37. #endif
  38. #endif
  39. #ifdef __cplusplus
  40. }
  41. #endif
  42. #endif /* __CORE_CK810_H_GENERIC */
  43. #ifndef __CSI_GENERIC
  44. #ifndef __CORE_CK810_H_DEPENDANT
  45. #define __CORE_CK810_H_DEPENDANT
  46. #ifdef __cplusplus
  47. extern "C" {
  48. #endif
  49. /* check device defines and use defaults */
  50. #ifndef __CK810_REV
  51. #define __CK810_REV 0x0000U
  52. #endif
  53. #ifndef __GSR_GCR_PRESENT
  54. #define __GSR_GCR_PRESENT 0U
  55. #endif
  56. #ifndef __ICACHE_PRESENT
  57. #define __ICACHE_PRESENT 1U
  58. #endif
  59. #ifndef __DCACHE_PRESENT
  60. #define __DCACHE_PRESENT 1U
  61. #endif
  62. #include <core/csi_gcc.h>
  63. /* IO definitions (access restrictions to peripheral registers) */
  64. /**
  65. \defgroup CSI_glob_defs CSI Global Defines
  66. <strong>IO Type Qualifiers</strong> are used
  67. \li to specify the access to peripheral variables.
  68. \li for automatic generation of peripheral register debug information.
  69. */
  70. #ifdef __cplusplus
  71. #define __I volatile /*!< Defines 'read only' permissions */
  72. #else
  73. #define __I volatile const /*!< Defines 'read only' permissions */
  74. #endif
  75. #define __O volatile /*!< Defines 'write only' permissions */
  76. #define __IO volatile /*!< Defines 'read / write' permissions */
  77. /* following defines should be used for structure members */
  78. #define __IM volatile const /*! Defines 'read only' structure member permissions */
  79. #define __OM volatile /*! Defines 'write only' structure member permissions */
  80. #define __IOM volatile /*! Defines 'read / write' structure member permissions */
  81. /*@} end of group CK810 */
  82. /*******************************************************************************
  83. * Register Abstraction
  84. Core Register contain:
  85. - Core Register
  86. ******************************************************************************/
  87. /**
  88. \defgroup CSI_core_register Defines and Type Definitions
  89. \brief Type definitions and defines for CK810 processor based devices.
  90. */
  91. /**
  92. \ingroup CSI_core_register
  93. \defgroup CSI_CORE Status and Control Registers
  94. \brief Core Register type definitions.
  95. @{
  96. */
  97. /**
  98. \brief Access Processor Status Register(PSR)struct definition.
  99. */
  100. typedef union {
  101. struct {
  102. uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
  103. uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
  104. uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
  105. uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
  106. uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
  107. uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
  108. uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
  109. uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
  110. uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
  111. uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
  112. uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
  113. uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
  114. uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
  115. uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
  116. uint32_t _reserved3: 7; /*!< bit: 24..30 Reserved */
  117. uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
  118. } b; /*!< Structure Access by bit */
  119. uint32_t w; /*!< Type Access by whole register */
  120. } PSR_Type;
  121. /* PSR Register Definitions */
  122. #define PSR_S_Pos 31U /*!< PSR: S Position */
  123. #define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
  124. #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
  125. #define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
  126. #define PSR_TM_Pos 14U /*!< PSR: TM Position */
  127. #define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
  128. #define PSR_TP_Pos 13U /*!< PSR: TP Position */
  129. #define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
  130. #define PSR_TE_Pos 12U /*!< PSR: TE Position */
  131. #define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
  132. #define PSR_MM_Pos 9U /*!< PSR: MM Position */
  133. #define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
  134. #define PSR_EE_Pos 8U /*!< PSR: EE Position */
  135. #define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
  136. #define PSR_IC_Pos 7U /*!< PSR: IC Position */
  137. #define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
  138. #define PSR_IE_Pos 6U /*!< PSR: IE Position */
  139. #define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
  140. #define PSR_FE_Pos 4U /*!< PSR: FE Position */
  141. #define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
  142. #define PSR_AF_Pos 1U /*!< PSR: AF Position */
  143. #define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
  144. #define PSR_C_Pos 0U /*!< PSR: C Position */
  145. #define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
  146. /**
  147. \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
  148. */
  149. typedef union {
  150. struct {
  151. uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
  152. uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
  153. uint32_t DE: 1; /*!< bit: 3 Data cache enable */
  154. uint32_t WB: 1; /*!< bit: 4 Cache write back */
  155. uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
  156. uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
  157. uint32_t BE: 1; /*!< bit: 7 Endian mode */
  158. uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
  159. uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
  160. uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
  161. uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
  162. uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
  163. uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
  164. uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
  165. } b; /*!< Structure Access by bit */
  166. uint32_t w; /*!< Type Access by whole register */
  167. } CCR_Type;
  168. /* CCR Register Definitions */
  169. #define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
  170. #define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
  171. #define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
  172. #define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
  173. #define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
  174. #define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
  175. #define CCR_WA_Pos 12u /*!< CCR: WA Position */
  176. #define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
  177. #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
  178. #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
  179. #define CCR_BE_Pos 7U /*!< CCR: BE Position */
  180. #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
  181. #define CCR_Z_Pos 6U /*!< CCR: Z Position */
  182. #define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
  183. #define CCR_RS_Pos 5U /*!< CCR: RS Position */
  184. #define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
  185. #define CCR_WB_Pos 4U /*!< CCR: WB Position */
  186. #define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
  187. #define CCR_DE_Pos 3U /*!< CCR: DE Position */
  188. #define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
  189. #define CCR_IE_Pos 2U /*!< CCR: IE Position */
  190. #define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
  191. #define CCR_MP_Pos 0U /*!< CCR: MP Position */
  192. #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
  193. /**
  194. \brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
  195. */
  196. typedef union {
  197. struct {
  198. uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
  199. uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
  200. uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
  201. uint32_t P: 1; /*!< bit: 31 TLBP instruction */
  202. } b;
  203. uint32_t w;
  204. } MIR_Type;
  205. /* MIR Register Definitions */
  206. #define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
  207. #define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
  208. #define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
  209. #define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
  210. #define MIR_Index_Pos 0 /*!< PRSR: Index Position */
  211. #define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
  212. /**
  213. \brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
  214. */
  215. typedef union {
  216. struct {
  217. uint32_t G: 1; /*!< bit: 0 Global enbale bit */
  218. uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
  219. uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
  220. uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
  221. uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
  222. uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
  223. uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
  224. uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
  225. uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
  226. } b;
  227. uint32_t w;
  228. } MEL_Type;
  229. /* MEL Register Definitions */
  230. #define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
  231. #define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
  232. #define MEL_B_Pos 6 /*!< MEL: B Position */
  233. #define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
  234. #define MEL_SO_Pos 5 /*!< MEL: SO Position */
  235. #define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
  236. #define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
  237. #define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
  238. #define MEL_C_Pos 3 /*!< MEL: C Position */
  239. #define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
  240. #define MEL_D_Pos 2 /*!< MEL: D Position */
  241. #define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
  242. #define MEL_V_Pos 1 /*!< MEL: V Position */
  243. #define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
  244. #define MEL_G_Pos 0 /*!< MEL: G Position */
  245. #define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
  246. /**
  247. \brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
  248. */
  249. typedef union {
  250. struct {
  251. uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
  252. uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
  253. uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
  254. } b;
  255. uint32_t w;
  256. } MEH_Type;
  257. /* MEH Register Definitions */
  258. #define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
  259. #define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
  260. #define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
  261. #define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
  262. /**
  263. \brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
  264. */
  265. typedef union {
  266. struct {
  267. uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
  268. uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
  269. uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
  270. } b;
  271. uint32_t w;
  272. } MPR_Type;
  273. /* MPR Register Definitions */
  274. #define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
  275. #define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
  276. /**
  277. \brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
  278. */
  279. typedef union {
  280. struct {
  281. uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
  282. uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
  283. uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
  284. uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
  285. uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
  286. uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
  287. uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
  288. uint32_t TLBR: 1; /*!< bit: 30 TLBR */
  289. uint32_t TLBP: 1; /*!< bit: 31 TLBP */
  290. } b;
  291. uint32_t w;
  292. } MCIR_Type;
  293. /* MCIR Register Definitions */
  294. #define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
  295. #define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
  296. #define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
  297. #define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
  298. #define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
  299. #define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
  300. #define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
  301. #define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
  302. #define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
  303. #define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
  304. #define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
  305. #define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
  306. #define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
  307. #define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
  308. #define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
  309. #define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
  310. /*@} end of group CSI_CORE */
  311. /**
  312. \ingroup CSI_core_register
  313. \defgroup CSI_CACHE
  314. \brief Type definitions for the cache Registers
  315. @{
  316. */
  317. /**
  318. \brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
  319. */
  320. typedef union {
  321. struct {
  322. uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
  323. uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
  324. uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
  325. uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
  326. uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
  327. uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
  328. uint32_t UNLOCK: 1; /*!< bit: 8 Unclock data cache line. */
  329. uint32_t _reserved1: 7; /*!< bit: 9..15 Reserved */
  330. uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
  331. uint32_t BTB_INV: 1; /*!< bit: 17 Invalid data in branch table buffer */
  332. uint32_t _reserved2: 13; /*!< bit: 18..30 Reserved */
  333. uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
  334. } b; /*!< Structure Access by bit */
  335. uint32_t w; /*!< Type Access by whole register */
  336. } CFR_Type;
  337. #define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
  338. #define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
  339. #define CFR_BTB_INV_Pos 17U /*!< CFR: BTB Position */
  340. #define CFR_BTB_INV_Msk (0x1UL << CFR_BTB_INV_Pos) /*!< CFR: BTB Mask */
  341. #define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
  342. #define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
  343. #define CFR_UNLOCK_Pos 8U /*!< CFR: UNLOCK Position */
  344. #define CFR_UNLOCK_Msk (0x1UL << CFR_UNLOCK_Pos) /*!< CFR: UNLOCK Mask */
  345. #define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
  346. #define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
  347. #define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
  348. #define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
  349. #define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
  350. #define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
  351. #define CFR_INV_Pos 4U /*!< CFR: INV Position */
  352. #define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
  353. #define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
  354. #define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
  355. /* CFR Register Definitions */
  356. /*@} end of group CSI_CACHE */
  357. /**
  358. \ingroup CSI_core_register
  359. \defgroup CSI_CACHE
  360. \brief Type definitions for the cache Registers
  361. @{
  362. */
  363. #define SSEG0_BASE_ADDR 0x80000000
  364. #define CACHE_RANGE_MAX_SIZE 0x80000
  365. #define INS_CACHE (1 << 0)
  366. #define DATA_CACHE (1 << 1)
  367. #define CACHE_INV (1 << 4)
  368. #define CACHE_CLR (1 << 5)
  369. #define CACHE_OMS (1 << 6)
  370. #define CACHE_ITS (1 << 7)
  371. #define CACHE_LICF (1 << 31)
  372. #define L1_CACHE_SHIFT 4 /* 16 Bytes */
  373. #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
  374. /**
  375. \brief Mask and shift a bit field value for use in a register bit range.
  376. \param[in] field Name of the register bit field.
  377. \param[in] value Value of the bit field.
  378. \return Masked and shifted value.
  379. */
  380. #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
  381. /**
  382. \brief Mask and shift a register value to extract a bit filed value.
  383. \param[in] field Name of the register bit field.
  384. \param[in] value Value of register.
  385. \return Masked and shifted bit field value.
  386. */
  387. #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
  388. /*@} end of group CSI_core_bitfield */
  389. /*******************************************************************************
  390. * Hardware Abstraction Layer
  391. Core Function Interface contains:
  392. - Core VIC Functions
  393. - Core CORET Functions
  394. - Core Register Access Functions
  395. ******************************************************************************/
  396. /* The following MACROS handle generation of the register offset and byte masks */
  397. #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
  398. #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
  399. /* ########################## Cache functions #################################### */
  400. /**
  401. \ingroup CSI_Core_FunctionInterface
  402. \defgroup CSI_Core_CacheFunctions Cache Functions
  403. \brief Functions that configure Instruction and Data cache.
  404. @{
  405. */
  406. /**
  407. \brief Enable I-Cache
  408. \details Turns on I-Cache
  409. */
  410. __STATIC_INLINE void csi_icache_enable (void)
  411. {
  412. __set_CCR(__get_CCR() | 0x00000004);
  413. }
  414. /**
  415. \brief Disable I-Cache
  416. \details Turns off I-Cache
  417. */
  418. __STATIC_INLINE void csi_icache_disable (void)
  419. {
  420. __set_CCR(__get_CCR() & 0xFFFFFFFB);
  421. }
  422. /**
  423. \brief Invalidate I-Cache
  424. \details Invalidates I-Cache
  425. */
  426. __STATIC_INLINE void csi_icache_invalid (void)
  427. {
  428. __set_CFR(0x11);
  429. __set_CFR(INS_CACHE | CACHE_INV);
  430. }
  431. /**
  432. \brief Enable D-Cache
  433. \details Turns on D-Cache
  434. \note I-Cache also turns on.
  435. */
  436. __STATIC_INLINE void csi_dcache_enable (void)
  437. {
  438. __set_CCR(__get_CCR() | 0x00000008);
  439. }
  440. /**
  441. \brief Disable D-Cache
  442. \details Turns off D-Cache
  443. \note I-Cache also turns off.
  444. */
  445. __STATIC_INLINE void csi_dcache_disable (void)
  446. {
  447. __set_CCR(__get_CCR() & 0xFFFFFFF7);
  448. }
  449. /**
  450. \brief Invalidate D-Cache
  451. \details Invalidates D-Cache
  452. \note I-Cache also invalid
  453. */
  454. __STATIC_INLINE void csi_dcache_invalid (void)
  455. {
  456. __set_CFR(DATA_CACHE | CACHE_INV);
  457. }
  458. /**
  459. \brief Clean D-Cache
  460. \details Cleans D-Cache
  461. \note I-Cache also cleans
  462. */
  463. __STATIC_INLINE void csi_dcache_clean (void)
  464. {
  465. __set_CFR(DATA_CACHE | CACHE_CLR);
  466. }
  467. /**
  468. \brief Clean & Invalidate D-Cache
  469. \details Cleans and Invalidates D-Cache
  470. \note I-Cache also flush.
  471. */
  472. __STATIC_INLINE void csi_dcache_clean_invalid (void)
  473. {
  474. __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
  475. }
  476. __STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
  477. {
  478. if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
  479. __set_CFR(value);
  480. }
  481. if (value & INS_CACHE) {
  482. csi_icache_disable();
  483. }
  484. uint32_t i;
  485. for (i = start; i < end; i += L1_CACHE_BYTES) {
  486. __set_CIR(i);
  487. __set_CFR(CACHE_OMS | value);
  488. }
  489. if (end & (L1_CACHE_BYTES-1)) {
  490. __set_CIR(end);
  491. __set_CFR(CACHE_OMS | value);
  492. }
  493. if (value & INS_CACHE) {
  494. csi_icache_enable();
  495. }
  496. }
  497. /**
  498. \brief D-Cache Invalidate by address
  499. \details Invalidates D-Cache for the given address
  500. \param[in] addr address (aligned to 16-byte boundary)
  501. \param[in] dsize size of memory block (aligned to 16-byte boundary)
  502. */
  503. __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
  504. {
  505. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
  506. }
  507. /**
  508. \brief D-Cache Clean by address
  509. \details Cleans D-Cache for the given address
  510. \param[in] addr address (aligned to 16-byte boundary)
  511. \param[in] dsize size of memory block (aligned to 16-byte boundary)
  512. */
  513. __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
  514. {
  515. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
  516. }
  517. /**
  518. \brief D-Cache Clean and Invalidate by address
  519. \details Cleans and invalidates D_Cache for the given address
  520. \param[in] addr address (aligned to 16-byte boundary)
  521. \param[in] dsize size of memory block (aligned to 16-byte boundary)
  522. */
  523. __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
  524. {
  525. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
  526. }
  527. /*@} end of CSI_Core_CacheFunctions */
  528. /* ########################## MMU functions #################################### */
  529. /**
  530. \ingroup CSI_Core_FunctionInterface
  531. \defgroup CSI_Core_MMUFunctions MMU Functions
  532. \brief Functions that configure MMU.
  533. @{
  534. */
  535. typedef struct {
  536. uint32_t global: 1; /* tlb page global access. */
  537. uint32_t valid: 1; /* tlb page valid */
  538. uint32_t writeable: 1; /* tlb page writeable */
  539. uint32_t cacheable: 1; /* tlb page cacheable*/
  540. uint32_t is_secure: 1; /* tlb page security access */
  541. uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
  542. uint32_t bufferable: 1; /* tlb page bufferable */
  543. } page_attr_t;
  544. typedef enum {
  545. PAGE_SIZE_4KB = 0x000,
  546. PAGE_SIZE_16KB = 0x003,
  547. PAGE_SIZE_64KB = 0x00F,
  548. PAGE_SIZE_256KB = 0x03F,
  549. PAGE_SIZE_1MB = 0x0FF,
  550. PAGE_SIZE_4MB = 0x3FF,
  551. PAGE_SIZE_16MB = 0xFFF
  552. } page_size_e;
  553. /**
  554. \brief enable mmu
  555. \details
  556. */
  557. __STATIC_INLINE void csi_mmu_enable(void)
  558. {
  559. __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
  560. }
  561. /**
  562. \brief disable mmu
  563. \details
  564. */
  565. __STATIC_INLINE void csi_mmu_disable(void)
  566. {
  567. __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
  568. }
  569. /**
  570. \brief create page with feature.
  571. \details
  572. \param [in] vaddr virtual address.
  573. \param [in] paddr physical address.
  574. \param [in] asid address sapce id (default: 0).
  575. \param [in] attr \ref page_attr_t. tlb page attribute.
  576. */
  577. __STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
  578. {
  579. MPR_Type pgmask;
  580. MEH_Type meh;
  581. MEL_Type mel;
  582. uint32_t vaddr_bit;
  583. uint32_t page_feature = 0;
  584. page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
  585. attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
  586. attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
  587. attr.bufferable << MEL_B_Pos;
  588. pgmask.w = __get_MPR();
  589. vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
  590. meh.b.ASID = (uint8_t)asid;
  591. meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
  592. __set_MEH(meh.w);
  593. __set_MCIR(1u << MCIR_TLBP_Pos);
  594. mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
  595. if (vaddr & (1 << vaddr_bit)) {
  596. __set_MEL1(mel.w);
  597. }
  598. else {
  599. __set_MEL0(mel.w);
  600. }
  601. if (__get_MIR() & (1 << MIR_P_Pos)) {
  602. __set_MCIR(1u << MCIR_TLBWR_Pos);
  603. } else {
  604. __set_MCIR(1u << MCIR_TLBWI_Pos);
  605. }
  606. }
  607. /**
  608. \brief enble mmu
  609. \details
  610. \param [in] size tlb page size.
  611. */
  612. __STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
  613. {
  614. MPR_Type pgmask;
  615. pgmask.b.page_mask = size;
  616. __set_MPR(pgmask.w);
  617. }
  618. /**
  619. \brief read MEH, MEL0, MEL1 by tlb index.
  620. \details
  621. \param [in] index tlb index(0, 1, 2, ...)
  622. \param [out] meh pointer to variable for retrieving MEH.
  623. \param [out] mel0 pointer to variable for retrieving MEL0.
  624. \param [out] mel1 pointer to variable for retrieving MEL1.
  625. */
  626. __STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
  627. {
  628. MIR_Type mir;
  629. if (meh == NULL || mel0 == NULL || mel1 == NULL) {
  630. return;
  631. }
  632. mir.b.Index = index;
  633. __set_MIR(mir.w);
  634. __set_MCIR(1u << MCIR_TLBR_Pos);
  635. *meh = __get_MEH();
  636. *mel0 = __get_MEL0();
  637. *mel1 = __get_MEL1();
  638. }
  639. /**
  640. \brief flush all mmu tlb.
  641. \details
  642. */
  643. __STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
  644. {
  645. __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
  646. }
  647. /**
  648. \brief flush mmu tlb by index.
  649. \details
  650. */
  651. __STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
  652. {
  653. MIR_Type mir;
  654. mir.b.Index = index;
  655. __set_MIR(mir.w);
  656. __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
  657. }
  658. /**
  659. \brief flush mmu tlb by virtual address.
  660. \details
  661. */
  662. __STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
  663. {
  664. __set_MEH(vaddr | (asid & MEH_ASID_Msk));
  665. __set_MCIR(1u << MCIR_TLBP_Pos);
  666. if (__get_MIR() & (1 << MIR_P_Pos)) {
  667. return;
  668. } else {
  669. __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
  670. }
  671. }
  672. /*@} end of CSI_Core_MMUFunctions */
  673. /* ################################## IRQ Functions ############################################ */
  674. /**
  675. \brief Save the Irq context
  676. \details save the psr result before disable irq.
  677. \param [in] irq_num External interrupt number. Value cannot be negative.
  678. */
  679. __STATIC_INLINE uint32_t csi_irq_save(void)
  680. {
  681. uint32_t result;
  682. result = __get_PSR();
  683. __disable_irq();
  684. return(result);
  685. }
  686. /**
  687. \brief Restore the Irq context
  688. \details restore saved primask state.
  689. \param [in] irq_state psr irq state.
  690. */
  691. __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
  692. {
  693. __set_PSR(irq_state);
  694. }
  695. /*@} end of IRQ Functions */
  696. #ifdef __cplusplus
  697. }
  698. #endif
  699. #endif /* __CORE_CK810_H_DEPENDANT */
  700. #endif /* __CSI_GENERIC */