core_807.h 94 KB

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  1. /*
  2. * Copyright (C) 2017-2019 Alibaba Group Holding Limited
  3. */
  4. /******************************************************************************
  5. * @file core_ck807.h
  6. * @brief CSI CK807 Core Peripheral Access Layer Header File
  7. * @version V1.0
  8. * @date 26. Jan 2018
  9. ******************************************************************************/
  10. #ifndef __CORE_CK807_H_GENERIC
  11. #define __CORE_CK807_H_GENERIC
  12. #include <stdint.h>
  13. #ifdef __cplusplus
  14. extern "C" {
  15. #endif
  16. /*******************************************************************************
  17. * CSI definitions
  18. ******************************************************************************/
  19. /**
  20. \ingroup CK807
  21. @{
  22. */
  23. /* CSI CK807 definitions */
  24. #define __CK807_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
  25. #define __CK807_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
  26. #define __CK807_CSI_VERSION ((__CK807_CSI_VERSION_MAIN << 16U) | \
  27. __CK807_CSI_VERSION_SUB ) /*!< CSI HAL version number */
  28. #ifndef __CK807
  29. #define __CK807 (0x07U) /*!< CK807 Core */
  30. #endif
  31. /** __FPU_USED indicates whether an FPU is used or not.
  32. */
  33. #define __FPU_USED 1U
  34. #if defined ( __GNUC__ )
  35. #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  36. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  37. #endif
  38. #endif
  39. #ifdef __cplusplus
  40. }
  41. #endif
  42. #endif /* __CORE_CK807_H_GENERIC */
  43. #ifndef __CSI_GENERIC
  44. #ifndef __CORE_CK807_H_DEPENDANT
  45. #define __CORE_CK807_H_DEPENDANT
  46. #ifdef __cplusplus
  47. extern "C" {
  48. #endif
  49. /* check device defines and use defaults */
  50. #ifndef __CK807_REV
  51. #define __CK807_REV 0x0000U
  52. #endif
  53. #ifndef __GSR_GCR_PRESENT
  54. #define __GSR_GCR_PRESENT 0U
  55. #endif
  56. #ifndef __ICACHE_PRESENT
  57. #define __ICACHE_PRESENT 1U
  58. #endif
  59. #ifndef __DCACHE_PRESENT
  60. #define __DCACHE_PRESENT 1U
  61. #endif
  62. #include <core/csi_gcc.h>
  63. /* IO definitions (access restrictions to peripheral registers) */
  64. /**
  65. \defgroup CSI_glob_defs CSI Global Defines
  66. <strong>IO Type Qualifiers</strong> are used
  67. \li to specify the access to peripheral variables.
  68. \li for automatic generation of peripheral register debug information.
  69. */
  70. #ifdef __cplusplus
  71. #define __I volatile /*!< Defines 'read only' permissions */
  72. #else
  73. #define __I volatile const /*!< Defines 'read only' permissions */
  74. #endif
  75. #define __O volatile /*!< Defines 'write only' permissions */
  76. #define __IO volatile /*!< Defines 'read / write' permissions */
  77. /* following defines should be used for structure members */
  78. #define __IM volatile const /*! Defines 'read only' structure member permissions */
  79. #define __OM volatile /*! Defines 'write only' structure member permissions */
  80. #define __IOM volatile /*! Defines 'read / write' structure member permissions */
  81. /*@} end of group CK807 */
  82. /*******************************************************************************
  83. * Register Abstraction
  84. Core Register contain:
  85. - Core Register
  86. ******************************************************************************/
  87. /**
  88. \defgroup CSI_core_register Defines and Type Definitions
  89. \brief Type definitions and defines for CK807 processor based devices.
  90. */
  91. /**
  92. \ingroup CSI_core_register
  93. \defgroup CSI_CORE Status and Control Registers
  94. \brief Core Register type definitions.
  95. @{
  96. */
  97. /**
  98. \brief Access Processor Status Register(PSR)struct definition.
  99. */
  100. typedef union {
  101. struct {
  102. uint32_t C: 1; /*!< bit: 0 Conditional code/Carry flag */
  103. uint32_t AF: 1; /*!< bit: 1 Alternate register valid control bit */
  104. uint32_t _reserved0: 2; /*!< bit: 2.. 3 Reserved */
  105. uint32_t FE: 1; /*!< bit: 4 Fast interrupt enable control bit */
  106. uint32_t _reserved1: 1; /*!< bit: 5 Reserved */
  107. uint32_t IE: 1; /*!< bit: 6 Interrupt effective control bit */
  108. uint32_t IC: 1; /*!< bit: 7 Interrupt control bit */
  109. uint32_t EE: 1; /*!< bit: 8 Abnormally effective control bit */
  110. uint32_t MM: 1; /*!< bit: 9 Unsymmetrical masking bit */
  111. uint32_t _reserved2: 2; /*!< bit: 10..11 Reserved */
  112. uint32_t TE: 1; /*!< bit: 12 Trace transmission control bit */
  113. uint32_t TP: 1; /*!< bit: 13 Pending trace exception set bit */
  114. uint32_t TM: 2; /*!< bit: 14..15 Tracing mode bit */
  115. uint32_t VEC: 8; /*!< bit: 16..23 Abnormal event vector value */
  116. uint32_t _reserved3: 7; /*!< bit: 24..30 Reserved */
  117. uint32_t S: 1; /*!< bit: 31 Superuser mode set bit */
  118. } b; /*!< Structure Access by bit */
  119. uint32_t w; /*!< Type Access by whole register */
  120. } PSR_Type;
  121. /* PSR Register Definitions */
  122. #define PSR_S_Pos 31U /*!< PSR: S Position */
  123. #define PSR_S_Msk (0x1UL << PSR_S_Pos) /*!< PSR: S Mask */
  124. #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
  125. #define PSR_VEC_Msk (0xFFUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
  126. #define PSR_TM_Pos 14U /*!< PSR: TM Position */
  127. #define PSR_TM_Msk (0x3UL << PSR_TM_Pos) /*!< PSR: TM Mask */
  128. #define PSR_TP_Pos 13U /*!< PSR: TP Position */
  129. #define PSR_TP_Msk (0x1UL << PSR_TM_Pos) /*!< PSR: TP Mask */
  130. #define PSR_TE_Pos 12U /*!< PSR: TE Position */
  131. #define PSR_TE_Msk (0x1UL << PSR_TE_Pos) /*!< PSR: TE Mask */
  132. #define PSR_MM_Pos 9U /*!< PSR: MM Position */
  133. #define PSR_MM_Msk (0x1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
  134. #define PSR_EE_Pos 8U /*!< PSR: EE Position */
  135. #define PSR_EE_Msk (0x1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
  136. #define PSR_IC_Pos 7U /*!< PSR: IC Position */
  137. #define PSR_IC_Msk (0x1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
  138. #define PSR_IE_Pos 6U /*!< PSR: IE Position */
  139. #define PSR_IE_Msk (0x1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
  140. #define PSR_FE_Pos 4U /*!< PSR: FE Position */
  141. #define PSR_FE_Msk (0x1UL << PSR_FE_Pos) /*!< PSR: FE Mask */
  142. #define PSR_AF_Pos 1U /*!< PSR: AF Position */
  143. #define PSR_AF_Msk (0x1UL << PSR_AF_Pos) /*!< PSR: AF Mask */
  144. #define PSR_C_Pos 0U /*!< PSR: C Position */
  145. #define PSR_C_Msk (0x1UL << PSR_C_Pos) /*!< PSR: C Mask */
  146. /**
  147. \brief Consortium definition for accessing Cache Configuration Registers(CCR, CR<18, 0>).
  148. */
  149. typedef union {
  150. struct {
  151. uint32_t MP: 2; /*!< bit: 0.. 1 memory protection settings */
  152. uint32_t IE: 1; /*!< bit: 2 Instruction cache enable */
  153. uint32_t DE: 1; /*!< bit: 3 Data cache enable */
  154. uint32_t WB: 1; /*!< bit: 4 Cache write back */
  155. uint32_t RS: 1; /*!< bit: 5 Address return stack settings */
  156. uint32_t Z: 1; /*!< bit: 6 Allow predictive jump bit */
  157. uint32_t BE: 1; /*!< bit: 7 Endian mode */
  158. uint32_t SCK: 3; /*!< bit: 8..10 the clock ratio of the system and the processor */
  159. uint32_t _reserved0: 1; /*!< bit: 11 Reserved */
  160. uint32_t WA: 1; /*!< bit: 12 Write allocate enable */
  161. uint32_t E_V2: 1; /*!< bit: 13 V2 Endian mode */
  162. uint32_t BSTE: 1; /*!< bit: 14 Burst transmit enable */
  163. uint32_t IPE: 1; /*!< bit: 15 Indirect predict enable */
  164. uint32_t _reserved1: 16; /*!< bit: 16..31 Reserved */
  165. } b; /*!< Structure Access by bit */
  166. uint32_t w; /*!< Type Access by whole register */
  167. } CCR_Type;
  168. /* CCR Register Definitions */
  169. #define CCR_IPE_Pos 15u /*!< CCR: IPE Position */
  170. #define CCR_IPE_Msk (0x1UL << CCR_IPE_Pos) /*!< CCR: IPE Mask */
  171. #define CCR_BSTE_Pos 14u /*!< CCR: BSTE Position */
  172. #define CCR_BSTE_Msk (0x1UL << CCR_BSTE_Pos) /*!< CCR: BSTE Mask */
  173. #define CCR_E_V2_Pos 13U /*!< CCR: E_V2 Position */
  174. #define CCR_E_V2_Msk (0x1UL << CCR_E_V2_Pos) /*!< CCR: E_V2 Mask */
  175. #define CCR_WA_Pos 12u /*!< CCR: WA Position */
  176. #define CCR_WA_Msk (0x1UL << CCR_WA_Pos) /*!< CCR: WA Mask */
  177. #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
  178. #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
  179. #define CCR_BE_Pos 7U /*!< CCR: BE Position */
  180. #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
  181. #define CCR_Z_Pos 6U /*!< CCR: Z Position */
  182. #define CCR_Z_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: Z Mask */
  183. #define CCR_RS_Pos 5U /*!< CCR: RS Position */
  184. #define CCR_RS_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: RS Mask */
  185. #define CCR_WB_Pos 4U /*!< CCR: WB Position */
  186. #define CCR_WB_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: WB Mask */
  187. #define CCR_DE_Pos 3U /*!< CCR: DE Position */
  188. #define CCR_DE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: DE Mask */
  189. #define CCR_IE_Pos 2U /*!< CCR: IE Position */
  190. #define CCR_IE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: IE Mask */
  191. #define CCR_MP_Pos 0U /*!< CCR: MP Position */
  192. #define CCR_MP_Msk (0x3UL << CCR_MP_Pos) /*!< CCR: MP Mask */
  193. /**
  194. \brief Consortium definition for accessing high ease access permission configutation registers(CAPR, CR<19,0>)
  195. */
  196. typedef union {
  197. struct {
  198. uint32_t NX0: 1; /*!< bit: 0 Non executable attribute setting */
  199. uint32_t NX1: 1; /*!< bit: 1 Non executable attribute setting */
  200. uint32_t NX2: 1; /*!< bit: 2 Non executable attribute setting */
  201. uint32_t NX3: 1; /*!< bit: 3 Non executable attribute setting */
  202. uint32_t NX4: 1; /*!< bit: 4 Non executable attribute setting */
  203. uint32_t NX5: 1; /*!< bit: 5 Non executable attribute setting */
  204. uint32_t NX6: 1; /*!< bit: 6 Non executable attribute setting */
  205. uint32_t NX7: 1; /*!< bit: 7 Non executable attribute setting */
  206. uint32_t AP0: 2; /*!< bit: 8.. 9 access permissions settings bit */
  207. uint32_t AP1: 2; /*!< bit: 10..11 access permissions settings bit */
  208. uint32_t AP2: 2; /*!< bit: 12..13 access permissions settings bit */
  209. uint32_t AP3: 2; /*!< bit: 14..15 access permissions settings bit */
  210. uint32_t AP4: 2; /*!< bit: 16..17 access permissions settings bit */
  211. uint32_t AP5: 2; /*!< bit: 18..19 access permissions settings bit */
  212. uint32_t AP6: 2; /*!< bit: 20..21 access permissions settings bit */
  213. uint32_t AP7: 2; /*!< bit: 22..23 access permissions settings bit */
  214. uint32_t S0: 1; /*!< bit: 24 Security property settings */
  215. uint32_t S1: 1; /*!< bit: 25 Security property settings */
  216. uint32_t S2: 1; /*!< bit: 26 Security property settings */
  217. uint32_t S3: 1; /*!< bit: 27 Security property settings */
  218. uint32_t S4: 1; /*!< bit: 28 Security property settings */
  219. uint32_t S5: 1; /*!< bit: 29 Security property settings */
  220. uint32_t S6: 1; /*!< bit: 30 Security property settings */
  221. uint32_t S7: 1; /*!< bit: 31 Security property settings */
  222. } b; /*!< Structure Access by bit */
  223. uint32_t w; /*!< Type Access by whole register */
  224. } CAPR_Type;
  225. /* CAPR Register Definitions */
  226. #define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
  227. #define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
  228. #define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
  229. #define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
  230. #define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
  231. #define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
  232. #define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
  233. #define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
  234. #define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
  235. #define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
  236. #define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
  237. #define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
  238. #define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
  239. #define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
  240. #define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
  241. #define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
  242. #define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
  243. #define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
  244. #define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
  245. #define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
  246. #define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
  247. #define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
  248. #define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
  249. #define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
  250. #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
  251. #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
  252. #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
  253. #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
  254. #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
  255. #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
  256. #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
  257. #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
  258. #define CAPR_NX7_Pos 7U /*!< CAPR: NX7 Position */
  259. #define CAPR_NX7_Msk (0x1UL << CAPR_NX7_Pos) /*!< CAPR: NX7 Mask */
  260. #define CAPR_NX6_Pos 6U /*!< CAPR: NX6 Position */
  261. #define CAPR_NX6_Msk (0x1UL << CAPR_NX6_Pos) /*!< CAPR: NX6 Mask */
  262. #define CAPR_NX5_Pos 5U /*!< CAPR: NX5 Position */
  263. #define CAPR_NX5_Msk (0x1UL << CAPR_NX5_Pos) /*!< CAPR: NX5 Mask */
  264. #define CAPR_NX4_Pos 4U /*!< CAPR: NX4 Position */
  265. #define CAPR_NX4_Msk (0x1UL << CAPR_NX4_Pos) /*!< CAPR: NX4 Mask */
  266. #define CAPR_NX3_Pos 3U /*!< CAPR: NX3 Position */
  267. #define CAPR_NX3_Msk (0x1UL << CAPR_NX3_Pos) /*!< CAPR: NX3 Mask */
  268. #define CAPR_NX2_Pos 2U /*!< CAPR: NX2 Position */
  269. #define CAPR_NX2_Msk (0x1UL << CAPR_NX2_Pos) /*!< CAPR: NX2 Mask */
  270. #define CAPR_NX1_Pos 1U /*!< CAPR: NX1 Position */
  271. #define CAPR_NX1_Msk (0x1UL << CAPR_NX1_Pos) /*!< CAPR: NX1 Mask */
  272. #define CAPR_NX0_Pos 0U /*!< CAPR: NX0 Position */
  273. #define CAPR_NX0_Msk (0x1UL << CAPR_NX0_Pos) /*!< CAPR: NX0 Mask */
  274. /**
  275. \brief Consortium definition for accessing high ease access permission configutation registers(CAPR1, CR<16,0>)
  276. */
  277. typedef union {
  278. struct {
  279. uint32_t NX8: 1; /*!< bit: 0 Non executable attribute setting */
  280. uint32_t NX9: 1; /*!< bit: 1 Non executable attribute setting */
  281. uint32_t NX10: 1; /*!< bit: 2 Non executable attribute setting */
  282. uint32_t NX11: 1; /*!< bit: 3 Non executable attribute setting */
  283. uint32_t NX12: 1; /*!< bit: 4 Non executable attribute setting */
  284. uint32_t NX13: 1; /*!< bit: 5 Non executable attribute setting */
  285. uint32_t NX14: 1; /*!< bit: 6 Non executable attribute setting */
  286. uint32_t NX15: 1; /*!< bit: 7 Non executable attribute setting */
  287. uint32_t AP8: 2; /*!< bit: 8.. 9 access permissions settings bit */
  288. uint32_t AP9: 2; /*!< bit: 10..11 access permissions settings bit */
  289. uint32_t AP10: 2; /*!< bit: 12..13 access permissions settings bit */
  290. uint32_t AP11: 2; /*!< bit: 14..15 access permissions settings bit */
  291. uint32_t AP12: 2; /*!< bit: 16..17 access permissions settings bit */
  292. uint32_t AP13: 2; /*!< bit: 18..19 access permissions settings bit */
  293. uint32_t AP14: 2; /*!< bit: 20..21 access permissions settings bit */
  294. uint32_t AP15: 2; /*!< bit: 22..23 access permissions settings bit */
  295. uint32_t S8: 1; /*!< bit: 24 Security property settings */
  296. uint32_t S9: 1; /*!< bit: 25 Security property settings */
  297. uint32_t S10: 1; /*!< bit: 26 Security property settings */
  298. uint32_t S11: 1; /*!< bit: 27 Security property settings */
  299. uint32_t S12: 1; /*!< bit: 28 Security property settings */
  300. uint32_t S13: 1; /*!< bit: 29 Security property settings */
  301. uint32_t S14: 1; /*!< bit: 30 Security property settings */
  302. uint32_t S15: 1; /*!< bit: 31 Security property settings */
  303. } b; /*!< Structure Access by bit */
  304. uint32_t w; /*!< Type Access by whole register */
  305. } CAPR1_Type;
  306. /* CAPR1 Register Definitions */
  307. #define CAPR1_S15_Pos 31U /*!< CAPR1: S15 Position */
  308. #define CAPR1_S15_Msk (1UL << CAPR1_S15_Pos) /*!< CAPR1: S15 Mask */
  309. #define CAPR1_S14_Pos 30U /*!< CAPR1: S14 Position */
  310. #define CAPR1_S14_Msk (1UL << CAPR1_S14_Pos) /*!< CAPR1: S14 Mask */
  311. #define CAPR1_S13_Pos 29U /*!< CAPR1: S13 Position */
  312. #define CAPR1_S13_Msk (1UL << CAPR1_S13_Pos) /*!< CAPR1: S13 Mask */
  313. #define CAPR1_S12_Pos 28U /*!< CAPR1: S12 Position */
  314. #define CAPR1_S12_Msk (1UL << CAPR1_S12_Pos) /*!< CAPR1: S12 Mask */
  315. #define CAPR1_S11_Pos 27U /*!< CAPR1: S11 Position */
  316. #define CAPR1_S11_Msk (1UL << CAPR1_S11_Pos) /*!< CAPR1: S11 Mask */
  317. #define CAPR1_S10_Pos 26U /*!< CAPR1: S10 Position */
  318. #define CAPR1_S10_Msk (1UL << CAPR1_S10_Pos) /*!< CAPR1: S10 Mask */
  319. #define CAPR1_S9_Pos 25U /*!< CAPR1: S9 Position */
  320. #define CAPR1_S9_Msk (1UL << CAPR1_S9_Pos) /*!< CAPR1: S9 Mask */
  321. #define CAPR1_S8_Pos 24U /*!< CAPR1: S8 Position */
  322. #define CAPR1_S8_Msk (1UL << CAPR1_S8_Pos) /*!< CAPR1: S8 Mask */
  323. #define CAPR1_AP15_Pos 22U /*!< CAPR1: AP15 Position */
  324. #define CAPR1_AP15_Msk (0x3UL << CAPR1_AP15_Pos) /*!< CAPR1: AP15 Mask */
  325. #define CAPR1_AP14_Pos 20U /*!< CAPR1: AP14 Position */
  326. #define CAPR1_AP14_Msk (0x3UL << CAPR1_AP14_Pos) /*!< CAPR1: AP14 Mask */
  327. #define CAPR1_AP13_Pos 18U /*!< CAPR1: AP13 Position */
  328. #define CAPR1_AP13_Msk (0x3UL << CAPR1_AP13_Pos) /*!< CAPR1: AP13 Mask */
  329. #define CAPR1_AP12_Pos 16U /*!< CAPR1: AP12 Position */
  330. #define CAPR1_AP12_Msk (0x3UL << CAPR1_AP12_Pos) /*!< CAPR1: AP12 Mask */
  331. #define CAPR1_AP11_Pos 14U /*!< CAPR1: AP11 Position */
  332. #define CAPR1_AP11_Msk (0x3UL << CAPR1_AP11_Pos) /*!< CAPR1: AP11 Mask */
  333. #define CAPR1_AP10_Pos 12U /*!< CAPR1: AP10 Position */
  334. #define CAPR1_AP10_Msk (0x3UL << CAPR1_AP10_Pos) /*!< CAPR1: AP10 Mask */
  335. #define CAPR1_AP9_Pos 10U /*!< CAPR1: AP9 Position */
  336. #define CAPR1_AP9_Msk (0x3UL << CAPR1_AP9_Pos) /*!< CAPR1: AP9 Mask */
  337. #define CAPR1_AP8_Pos 8U /*!< CAPR1: AP8 Position */
  338. #define CAPR1_AP8_Msk (0x3UL << CAPR1_AP8_Pos) /*!< CAPR1: AP8 Mask */
  339. #define CAPR1_NX15_Pos 7U /*!< CAPR1: NX15 Position */
  340. #define CAPR1_NX15_Msk (0x1UL << CAPR1_NX15_Pos) /*!< CAPR1: NX15 Mask */
  341. #define CAPR1_NX14_Pos 6U /*!< CAPR1: NX14 Position */
  342. #define CAPR1_NX14_Msk (0x1UL << CAPR1_NX14_Pos) /*!< CAPR1: NX14 Mask */
  343. #define CAPR1_NX13_Pos 5U /*!< CAPR1: NX13 Position */
  344. #define CAPR1_NX13_Msk (0x1UL << CAPR1_NX13_Pos) /*!< CAPR1: NX13 Mask */
  345. #define CAPR1_NX12_Pos 4U /*!< CAPR1: NX12 Position */
  346. #define CAPR1_NX12_Msk (0x1UL << CAPR1_NX12_Pos) /*!< CAPR1: NX12 Mask */
  347. #define CAPR1_NX11_Pos 3U /*!< CAPR1: NX11 Position */
  348. #define CAPR1_NX11_Msk (0x1UL << CAPR1_NX11_Pos) /*!< CAPR1: NX11 Mask */
  349. #define CAPR1_NX10_Pos 2U /*!< CAPR1: NX10 Position */
  350. #define CAPR1_NX10_Msk (0x1UL << CAPR1_NX10_Pos) /*!< CAPR1: NX10 Mask */
  351. #define CAPR1_NX9_Pos 1U /*!< CAPR1: NX9 Position */
  352. #define CAPR1_NX9_Msk (0x1UL << CAPR1_NX9_Pos) /*!< CAPR1: NX9 Mask */
  353. #define CAPR1_NX8_Pos 0U /*!< CAPR1: NX8 Position */
  354. #define CAPR1_NX8_Msk (0x1UL << CAPR1_NX8_Pos) /*!< CAPR1: NX8 Mask */
  355. /**
  356. \brief Consortium definition for accessing control register(PACR, CR<20,0>).
  357. */
  358. typedef union {
  359. struct {
  360. uint32_t E: 1; /*!< bit: 0 Effective setting of protected area */
  361. uint32_t size: 5; /*!< bit: 1.. 5 Size of protected area */
  362. uint32_t base_addr: 26; /*!< bit: 6..31 The high position of the address of a protected area */
  363. } b; /*!< Structure Access by bit */
  364. uint32_t w; /*!< Type Access by whole register */
  365. } PACR_Type;
  366. /* PACR Register Definitions */
  367. #define PACR_BASE_ADDR_Pos 6U /*!< PACR: base_addr Position */
  368. #define PACR_BASE_ADDR_Msk (0x3FFFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
  369. #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
  370. #define PACR_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
  371. #define PACR_E_Pos 0U /*!< PACR: E Position */
  372. #define PACR_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
  373. /**
  374. \brief Consortium definition for accessing protection area selection register(PRSR,CR<21,0>).
  375. */
  376. typedef union {
  377. struct {
  378. uint32_t RID: 4; /*!< bit: 0.. 3 Protected area index value */
  379. uint32_t _reserved0: 28; /*!< bit: 2..28 Reserved */
  380. } b; /*!< Structure Access by bit */
  381. uint32_t w; /*!< Type Access by whole register */
  382. } PRSR_Type;
  383. /* PRSR Register Definitions */
  384. #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
  385. #define PRSR_RID_Msk (0x3UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
  386. /**
  387. \brief Consortium definition for accessing protection area selection register(ATTR0,CR<26,0>).
  388. */
  389. typedef union {
  390. struct {
  391. uint32_t Attr0_reserved: 1; /*!< bit: 0 Reserved */
  392. uint32_t Attr0_B: 1; /*!< bit: 1 Bufferable attribute setting */
  393. uint32_t Attr0_SO: 1; /*!< bit: 2 Strong-Order attribute setting */
  394. uint32_t Attr0_C: 1; /*!< bit: 3 Cacheable attribute setting */
  395. uint32_t Attr1_reserved: 1; /*!< bit: 4 Reserved */
  396. uint32_t Attr1_B: 1; /*!< bit: 5 Bufferable attribute setting */
  397. uint32_t Attr1_SO: 1; /*!< bit: 6 Strong-Order attribute setting */
  398. uint32_t Attr1_C: 1; /*!< bit: 7 Cacheable attribute setting */
  399. uint32_t Attr2_reserved: 1; /*!< bit: 8 Reserved */
  400. uint32_t Attr2_B: 1; /*!< bit: 9 Bufferable attribute setting */
  401. uint32_t Attr2_SO: 1; /*!< bit: 10 Strong-Order attribute setting */
  402. uint32_t Attr2_C: 1; /*!< bit: 11 Bufferable attribute setting */
  403. uint32_t Attr3_reserved: 1; /*!< bit: 12 Reserved */
  404. uint32_t Attr3_B: 1; /*!< bit: 13 Bufferable attribute setting */
  405. uint32_t Attr3_SO: 1; /*!< bit: 14 Strong-Order attribute setting */
  406. uint32_t Attr3_C: 1; /*!< bit: 15 Bufferable attribute setting */
  407. uint32_t Attr4_reserved: 1; /*!< bit: 16 Reserved */
  408. uint32_t Attr4_B: 1; /*!< bit: 17 Bufferable attribute setting */
  409. uint32_t Attr4_SO: 1; /*!< bit: 18 Strong-Order attribute setting */
  410. uint32_t Attr4_C: 1; /*!< bit: 19 Bufferable attribute setting */
  411. uint32_t Attr5_reserved: 1; /*!< bit: 20 Reserved */
  412. uint32_t Attr5_B: 1; /*!< bit: 21 Bufferable attribute setting */
  413. uint32_t Attr5_SO: 1; /*!< bit: 22 Strong-Order attribute setting */
  414. uint32_t Attr5_C: 1; /*!< bit: 23 Bufferable attribute setting */
  415. uint32_t Attr6_reserved: 1; /*!< bit: 24 Reserved */
  416. uint32_t Attr6_B: 1; /*!< bit: 25 Bufferable attribute setting */
  417. uint32_t Attr6_SO: 1; /*!< bit: 26 Strong-Order attribute setting */
  418. uint32_t Attr6_C: 1; /*!< bit: 27 Bufferable attribute setting */
  419. uint32_t Attr7_reserved: 1; /*!< bit: 28 Reserved */
  420. uint32_t Attr7_B: 1; /*!< bit: 29 Bufferable attribute setting */
  421. uint32_t Attr7_SO: 1; /*!< bit: 30 Strong-Order attribute setting */
  422. uint32_t Attr7_C: 1; /*!< bit: 31 Bufferable attribute setting */
  423. } b; /*!< Structure Access by bit */
  424. uint32_t w; /*!< Type Access by whole register */
  425. } ATTR0_Type;
  426. /* ATTR0 Register Definitions */
  427. #define ATTR0_RESERVED_Pos 0U /*!< ATTR0: RESERVED Position */
  428. #define ATTR0_RESERVED_Msk (0x1UL << ATTR0_RESERVED_Pos) /*!< ATTR0: RESERVED Mask */
  429. #define ATTR0_B_Pos 1U /*!< ATTR0: BUFFERABLE Position */
  430. #define ATTR0_B_Msk (0x1UL << ATTR0_B_Pos) /*!< ATTR0: BUFFERABLE Mask */
  431. #define ATTR0_SO_Pos 2U /*!< ATTR0: STRONG-ORDER Position */
  432. #define ATTR0_SO_Msk (0x1UL << ATTR0_SO_Pos) /*!< ATTR0: STRONG-ORDER Mask */
  433. #define ATTR0_C_Pos 3U /*!< ATTR0: CACHEABLE Position */
  434. #define ATTR0_C_Msk (0x1UL << ATTR0_C_Pos) /*!< ATTR0: CACHEABLE Mask */
  435. #define ATTR1_RESERVED_Pos 4U /*!< ATTR1: RESERVED Position */
  436. #define ATTR1_RESERVED_Msk (0x1UL << ATTR1_RESERVED_Pos) /*!< ATTR1: RESERVED Mask */
  437. #define ATTR1_B_Pos 5U /*!< ATTR1: BUFFERABLE Position */
  438. #define ATTR1_B_Msk (0x1UL << ATTR1_B_Pos) /*!< ATTR1: BUFFERABLE Mask */
  439. #define ATTR1_SO_Pos 6U /*!< ATTR1: STRONG-ORDER Position */
  440. #define ATTR1_SO_Msk (0x1UL << ATTR1_SO_Pos) /*!< ATTR1: STRONG-ORDER Mask */
  441. #define ATTR1_C_Pos 7U /*!< ATTR1: CACHEABLE Position */
  442. #define ATTR1_C_Msk (0x1UL << ATTR1_C_Pos) /*!< ATTR1: CACHEABLE Mask */
  443. #define ATTR2_RESERVED_Pos 8U /*!< ATTR2: RESERVED Position */
  444. #define ATTR2_RESERVED_Msk (0x1UL << ATTR2_RESERVED_Pos) /*!< ATTR2: RESERVED Mask */
  445. #define ATTR2_B_Pos 9U /*!< ATTR2: BUFFERABLE Position */
  446. #define ATTR2_B_Msk (0x1UL << ATTR2_B_Pos) /*!< ATTR2: BUFFERABLE Mask */
  447. #define ATTR2_SO_Pos 10U /*!< ATTR2: STRONG-ORDER Position */
  448. #define ATTR2_SO_Msk (0x1UL << ATTR2_SO_Pos) /*!< ATTR2: STRONG-ORDER Mask */
  449. #define ATTR2_C_Pos 11U /*!< ATTR2: CACHEABLE Position */
  450. #define ATTR2_C_Msk (0x1UL << ATTR2_C_Pos) /*!< ATTR2: CACHEABLE Mask */
  451. #define ATTR3_RESERVED_Pos 12U /*!< ATTR3: RESERVED Position */
  452. #define ATTR3_RESERVED_Msk (0x1UL << ATTR3_RESERVED_Pos) /*!< ATTR3: RESERVED Mask */
  453. #define ATTR3_B_Pos 13U /*!< ATTR3: BUFFERABLE Position */
  454. #define ATTR3_B_Msk (0x1UL << ATTR3_B_Pos) /*!< ATTR3: BUFFERABLE Mask */
  455. #define ATTR3_SO_Pos 14U /*!< ATTR3: STRONG-ORDER Position */
  456. #define ATTR3_SO_Msk (0x1UL << ATTR3_SO_Pos) /*!< ATTR3: STRONG-ORDER Mask */
  457. #define ATTR3_C_Pos 15U /*!< ATTR3: CACHEABLE Position */
  458. #define ATTR3_C_Msk (0x1UL << ATTR3_C_Pos) /*!< ATTR3: CACHEABLE Mask */
  459. #define ATTR4_RESERVED_Pos 16U /*!< ATTR4: RESERVED Position */
  460. #define ATTR4_RESERVED_Msk (0x1UL << ATTR4_RESERVED_Pos) /*!< ATTR4: RESERVED Mask */
  461. #define ATTR4_B_Pos 17U /*!< ATTR4: BUFFERABLE Position */
  462. #define ATTR4_B_Msk (0x1UL << ATTR4_B_Pos) /*!< ATTR4: BUFFERABLE Mask */
  463. #define ATTR4_SO_Pos 18U /*!< ATTR4: STRONG-ORDER Position */
  464. #define ATTR4_SO_Msk (0x1UL << ATTR4_SO_Pos /*!< ATTR4: STRONG-ORDER Mask */
  465. #define ATTR4_C_Pos 19U /*!< ATTR4: CACHEABLE Position */
  466. #define ATTR4_C_Msk (0x1UL << ATTR4_C_Pos) /*!< ATTR4: CACHEABLE Mask */
  467. #define ATTR5_RESERVED_Pos 20U /*!< ATTR5: RESERVED Position */
  468. #define ATTR5_RESERVED_Msk (0x1UL << ATTR5_RESERVED_Pos) /*!< ATTR5: RESERVED Mask */
  469. #define ATTR5_B_Pos 21U /*!< ATTR5: BUFFERABLE Position */
  470. #define ATTR5_B_Msk (0x1UL << ATTR5_B_Pos) /*!< ATTR5: BUFFERABLE Mask */
  471. #define ATTR5_SO_Pos 22U /*!< ATTR5: STRONG-ORDER Position */
  472. #define ATTR5_SO_Msk (0x1UL << ATTR5_SO_Pos) /*!< ATTR5: STRONG-ORDER Mask */
  473. #define ATTR5_C_Pos 23U /*!< ATTR5: CACHEABLE Position */
  474. #define ATTR5_C_Msk (0x1UL << ATTR5_C_Pos) /*!< ATTR5: CACHEABLE Mask */
  475. #define ATTR6_RESERVED_Pos 24U /*!< ATTR6: RESERVED Position */
  476. #define ATTR6_RESERVED_Msk (0x1UL << ATTR6_RESERVED_Pos) /*!< ATTR6: RESERVED Mask */
  477. #define ATTR6_B_Pos 25U /*!< ATTR6: BUFFERABLE Position */
  478. #define ATTR6_B_Msk (0x1UL << ATTR6_B_Pos) /*!< ATTR6: BUFFERABLE Mask */
  479. #define ATTR6_SO_Pos 26U /*!< ATTR6: STRONG-ORDER Position */
  480. #define ATTR6_SO_Msk (0x1UL << ATTR6_SO_Pos) /*!< ATTR6: STRONG-ORDER Mask */
  481. #define ATTR6_C_Pos 27U /*!< ATTR6: CACHEABLE Position */
  482. #define ATTR6_C_Msk (0x1UL << ATTR6_C_Pos) /*!< ATTR6: CACHEABLE Mask */
  483. #define ATTR7_RESERVED_Pos 28U /*!< ATTR7: RESERVED Position */
  484. #define ATTR7_RESERVED_Msk (0x1UL << ATTR7_RESERVED_Pos) /*!< ATTR7: RESERVED Mask */
  485. #define ATTR7_B_Pos 29U /*!< ATTR7: BUFFERABLE Position */
  486. #define ATTR7_B_Msk (0x1UL << ATTR7_B_Pos) /*!< ATTR7: BUFFERABLE Mask */
  487. #define ATTR7_SO_Pos 30U /*!< ATTR7: STRONG-ORDER Position */
  488. #define ATTR7_SO_Msk (0x1UL << ATTR7_SO_Pos) /*!< ATTR7: STRONG-ORDER Mask */
  489. #define ATTR7_C_Pos 31U /*!< ATTR7: CACHEABLE Position */
  490. #define ATTR7_C_Msk (0x1UL << ATTR7_C_Pos) /*!< ATTR7: CACHEABLE Mask */
  491. /**
  492. \brief Consortium definition for accessing protection area selection register(ATTR1,CR<27,0>).
  493. */
  494. typedef union {
  495. struct {
  496. uint32_t Attr8_reserved: 1; /*!< bit: 0 Reserved */
  497. uint32_t Attr8_B: 1; /*!< bit: 1 Bufferable attribute setting */
  498. uint32_t Attr8_SO: 1; /*!< bit: 2 Strong-Order attribute setting */
  499. uint32_t Attr8_C: 1; /*!< bit: 3 Cacheable attribute setting */
  500. uint32_t Attr9_reserved: 1; /*!< bit: 4 Reserved */
  501. uint32_t Attr9_B: 1; /*!< bit: 5 Bufferable attribute setting */
  502. uint32_t Attr9_SO: 1; /*!< bit: 6 Strong-Order attribute setting */
  503. uint32_t Attr9_C: 1; /*!< bit: 7 Cacheable attribute setting */
  504. uint32_t Attr10_reserved: 1; /*!< bit: 8 Reserved */
  505. uint32_t Attr10_B: 1; /*!< bit: 9 Bufferable attribute setting */
  506. uint32_t Attr10_SO: 1; /*!< bit: 10 Strong-Order attribute setting */
  507. uint32_t Attr10_C: 1; /*!< bit: 11 Bufferable attribute setting */
  508. uint32_t Attr11_reserved: 1; /*!< bit: 12 Reserved */
  509. uint32_t Attr11_B: 1; /*!< bit: 13 Bufferable attribute setting */
  510. uint32_t Attr11_SO: 1; /*!< bit: 14 Strong-Order attribute setting */
  511. uint32_t Attr11_C: 1; /*!< bit: 15 Bufferable attribute setting */
  512. uint32_t Attr12_reserved: 1; /*!< bit: 16 Reserved */
  513. uint32_t Attr12_B: 1; /*!< bit: 17 Bufferable attribute setting */
  514. uint32_t Attr12_SO: 1; /*!< bit: 18 Strong-Order attribute setting */
  515. uint32_t Attr12_C: 1; /*!< bit: 19 Bufferable attribute setting */
  516. uint32_t Attr13_reserved: 1; /*!< bit: 20 Reserved */
  517. uint32_t Attr13_B: 1; /*!< bit: 21 Bufferable attribute setting */
  518. uint32_t Attr13_SO: 1; /*!< bit: 22 Strong-Order attribute setting */
  519. uint32_t Attr13_C: 1; /*!< bit: 23 Bufferable attribute setting */
  520. uint32_t Attr14_reserved: 1; /*!< bit: 24 Reserved */
  521. uint32_t Attr14_B: 1; /*!< bit: 25 Bufferable attribute setting */
  522. uint32_t Attr14_SO: 1; /*!< bit: 26 Strong-Order attribute setting */
  523. uint32_t Attr14_C: 1; /*!< bit: 27 Bufferable attribute setting */
  524. uint32_t Attr15_reserved: 1; /*!< bit: 28 Reserved */
  525. uint32_t Attr15_B: 1; /*!< bit: 29 Bufferable attribute setting */
  526. uint32_t Attr15_SO: 1; /*!< bit: 30 Strong-Order attribute setting */
  527. uint32_t Attr15_C: 1; /*!< bit: 31 Bufferable attribute setting */
  528. } b; /*!< Structure Access by bit */
  529. uint32_t w; /*!< Type Access by whole register */
  530. } ATTR1_Type;
  531. /* ATTR0 Register Definitions */
  532. #define ATTR8_RESERVED_Pos 0U /*!< ATTR8: RESERVED Position */
  533. #define ATTR8_RESERVED_Msk (0x1UL << ATTR8_RESERVED_Pos) /*!< ATTR8: RESERVED Mask */
  534. #define ATTR8_B_Pos 1U /*!< ATTR8: BUFFERABLE Position */
  535. #define ATTR8_B_Msk (0x1UL << ATTR8_B_Pos) /*!< ATTR8: BUFFERABLE Mask */
  536. #define ATTR8_SO_Pos 2U /*!< ATTR8: STRONG-ORDER Position */
  537. #define ATTR8_SO_Msk (0x1UL << ATTR8_SO_Pos) /*!< ATTR8: STRONG-ORDER Mask */
  538. #define ATTR8_C_Pos 3U /*!< ATTR8: CACHEABLE Position */
  539. #define ATTR8_C_Msk (0x1UL << ATTR8_C_Pos) /*!< ATTR8: CACHEABLE Mask */
  540. #define ATTR9_RESERVED_Pos 4U /*!< ATTR9: RESERVED Position */
  541. #define ATTR9_RESERVED_Msk (0x1UL << ATTR9_RESERVED_Pos) /*!< ATTR9: RESERVED Mask */
  542. #define ATTR9_B_Pos 5U /*!< ATTR9: BUFFERABLE Position */
  543. #define ATTR9_B_Msk (0x1UL << ATTR9_B_Pos) /*!< ATTR9: BUFFERABLE Mask */
  544. #define ATTR9_SO_Pos 6U /*!< ATTR9: STRONG-ORDER Position */
  545. #define ATTR9_SO_Msk (0x1UL << ATTR9_SO_Pos) /*!< ATTR9: STRONG-ORDER Mask */
  546. #define ATTR9_C_Pos 7U /*!< ATTR9: CACHEABLE Position */
  547. #define ATTR9_C_Msk (0x1UL << ATTR9_C_Pos) /*!< ATTR9: CACHEABLE Mask */
  548. #define ATTR10_RESERVED_Pos 8U /*!< ATTR10: RESERVED Position */
  549. #define ATTR10_RESERVED_Msk (0x1UL << ATTR10_RESERVED_Pos) /*!< ATTR10: RESERVED Mask */
  550. #define ATTR10_B_Pos 9U /*!< ATTR10: BUFFERABLE Position */
  551. #define ATTR10_B_Msk (0x1UL << ATTR10_B_Pos) /*!< ATTR10: BUFFERABLE Mask */
  552. #define ATTR10_SO_Pos 10U /*!< ATTR10: STRONG-ORDER Position */
  553. #define ATTR10_SO_Msk (0x1UL << ATTR10_SO_Pos) /*!< ATTR10: STRONG-ORDER Mask */
  554. #define ATTR10_C_Pos 11U /*!< ATTR10: CACHEABLE Position */
  555. #define ATTR10_C_Msk (0x1UL << ATTR10_C_Pos) /*!< ATTR10: CACHEABLE Mask */
  556. #define ATTR11_RESERVED_Pos 12U /*!< ATTR11: RESERVED Position */
  557. #define ATTR11_RESERVED_Msk (0x1UL << ATTR11_RESERVED_Pos) /*!< ATTR11: RESERVED Mask */
  558. #define ATTR11_B_Pos 13U /*!< ATTR11: BUFFERABLE Position */
  559. #define ATTR11_B_Msk (0x1UL << ATTR11_B_Pos) /*!< ATTR11: BUFFERABLE Mask */
  560. #define ATTR11_SO_Pos 14U /*!< ATTR11: STRONG-ORDER Position */
  561. #define ATTR11_SO_Msk (0x1UL << ATTR11_SO_Pos) /*!< ATTR11: STRONG-ORDER Mask */
  562. #define ATTR11_C_Pos 15U /*!< ATTR11: CACHEABLE Position */
  563. #define ATTR11_C_Msk (0x1UL << ATTR11_C_Pos) /*!< ATTR11: CACHEABLE Mask */
  564. #define ATTR12_RESERVED_Pos 16U /*!< ATTR12: RESERVED Position */
  565. #define ATTR12_RESERVED_Msk (0x1UL << ATTR12_RESERVED_Pos) /*!< ATTR12: RESERVED Mask */
  566. #define ATTR12_B_Pos 17U /*!< ATTR12: BUFFERABLE Position */
  567. #define ATTR12_B_Msk (0x1UL << ATTR12_B_Pos) /*!< ATTR12: BUFFERABLE Mask */
  568. #define ATTR12_SO_Pos 18U /*!< ATTR12: STRONG-ORDER Position */
  569. #define ATTR12_SO_Msk (0x1UL << ATTR12_SO_Pos /*!< ATTR12: STRONG-ORDER Mask */
  570. #define ATTR12_C_Pos 19U /*!< ATTR12: CACHEABLE Position */
  571. #define ATTR12_C_Msk (0x1UL << ATTR12_C_Pos) /*!< ATTR12: CACHEABLE Mask */
  572. #define ATTR13_RESERVED_Pos 20U /*!< ATTR13: RESERVED Position */
  573. #define ATTR13_RESERVED_Msk (0x1UL << ATTR13_RESERVED_Pos) /*!< ATTR13: RESERVED Mask */
  574. #define ATTR13_B_Pos 21U /*!< ATTR13: BUFFERABLE Position */
  575. #define ATTR13_B_Msk (0x1UL << ATTR13_B_Pos) /*!< ATTR13: BUFFERABLE Mask */
  576. #define ATTR13_SO_Pos 22U /*!< ATTR13: STRONG-ORDER Position */
  577. #define ATTR13_SO_Msk (0x1UL << ATTR13_SO_Pos) /*!< ATTR13: STRONG-ORDER Mask */
  578. #define ATTR13_C_Pos 23U /*!< ATTR13: CACHEABLE Position */
  579. #define ATTR13_C_Msk (0x1UL << ATTR13_C_Pos) /*!< ATTR13: CACHEABLE Mask */
  580. #define ATTR14_RESERVED_Pos 24U /*!< ATTR14: RESERVED Position */
  581. #define ATTR14_RESERVED_Msk (0x1UL << ATTR14_RESERVED_Pos) /*!< ATTR14: RESERVED Mask */
  582. #define ATTR14_B_Pos 25U /*!< ATTR14: BUFFERABLE Position */
  583. #define ATTR14_B_Msk (0x1UL << ATTR14_B_Pos) /*!< ATTR14: BUFFERABLE Mask */
  584. #define ATTR14_SO_Pos 26U /*!< ATTR14: STRONG-ORDER Position */
  585. #define ATTR14_SO_Msk (0x1UL << ATTR14_SO_Pos) /*!< ATTR14: STRONG-ORDER Mask */
  586. #define ATTR14_C_Pos 27U /*!< ATTR14: CACHEABLE Position */
  587. #define ATTR14_C_Msk (0x1UL << ATTR14_C_Pos) /*!< ATTR14: CACHEABLE Mask */
  588. #define ATTR15_RESERVED_Pos 28U /*!< ATTR15: RESERVED Position */
  589. #define ATTR15_RESERVED_Msk (0x1UL << ATTR15_RESERVED_Pos) /*!< ATTR15: RESERVED Mask */
  590. #define ATTR15_B_Pos 29U /*!< ATTR15: BUFFERABLE Position */
  591. #define ATTR15_B_Msk (0x1UL << ATTR15_B_Pos) /*!< ATTR15: BUFFERABLE Mask */
  592. #define ATTR15_SO_Pos 30U /*!< ATTR15: STRONG-ORDER Position */
  593. #define ATTR15_SO_Msk (0x1UL << ATTR15_SO_Pos) /*!< ATTR15: STRONG-ORDER Mask */
  594. #define ATTR15_C_Pos 31U /*!< ATTR15: CACHEABLE Position */
  595. #define ATTR15_C_Msk (0x1UL << ATTR15_C_Pos) /*!< ATTR15: CACHEABLE Mask */
  596. /* CCR2 Register Definitions */
  597. #define CCR2_CRECC_Pos 7U /*!< CCR2: CRECC Position */
  598. #define CCR2_CRECC_Msk (0x1UL << CCR2_CRECC_Pos) /*!< CCR2: CRECC Mask */
  599. #define CCR2_ECC_Pos 6U /*!< CCR2: ECC Position */
  600. #define CCR2_ECC_Msk (0x1UL << CCR2_ECC_Pos) /*!< CCR2: ECC Mask */
  601. /**
  602. \brief Consortium definition for accessing mmu index register(MIR,CR<0,15>).
  603. */
  604. typedef union {
  605. struct {
  606. uint32_t Index: 10; /*!< bit: 0.. 9 TLB index */
  607. uint32_t _reserved: 20; /*!< bit: 10.. 29 Reserved */
  608. uint32_t TF: 1; /*!< bit: 30 TLB fatal error */
  609. uint32_t P: 1; /*!< bit: 31 TLBP instruction */
  610. } b;
  611. uint32_t w;
  612. } MIR_Type;
  613. /* MIR Register Definitions */
  614. #define MIR_P_Pos 31 /*!< PRSR: P(TLBP instruction) Position */
  615. #define MIR_P_Msk (0x1UL << MIR_P_Pos) /*!< PRSR: P(TLBP instruction) Mask */
  616. #define MIR_TF_Pos 30 /*!< PRSR: Tfatal Position */
  617. #define MIR_TF_Msk (0x1UL << MIR_TF_Pos) /*!< PRSR: Tfatal Mask */
  618. #define MIR_Index_Pos 0 /*!< PRSR: Index Position */
  619. #define MIR_Index_Msk (0x3ffUL << MIR_Index_Pos) /*!< PRSR: Index Mask */
  620. /**
  621. \brief Consortium definition for accessing mmu entry of high physical address register(MEL, CR<2,15> and CR<3,15>).
  622. */
  623. typedef union {
  624. struct {
  625. uint32_t G: 1; /*!< bit: 0 Global enbale bit */
  626. uint32_t V: 1; /*!< bit: 1 TLB mapping valid bit */
  627. uint32_t D: 1; /*!< bit: 2 TLB Page dirty bit */
  628. uint32_t C: 1; /*!< bit: 3 TLB Page cacheable bit */
  629. uint32_t SEC: 1; /*!< bit: 4 TLB Page security bit */
  630. uint32_t SO: 1; /*!< bit: 2 Strong order enable bit */
  631. uint32_t B: 1; /*!< bit: 2 TLB Page bufferable bit */
  632. uint32_t _reserved: 5; /*!< bit: 7.. 11 Reserved */
  633. uint32_t PFN: 20; /*!< bit: 12.. 31 Physical frame number */
  634. } b;
  635. uint32_t w;
  636. } MEL_Type;
  637. /* MEL Register Definitions */
  638. #define MEL_PFN_Pos 12 /*!< MEL: PFN Position */
  639. #define MEL_PFN_Msk (0xFFFFFUL << MEL_PFN_Pos) /*!< MEL: PFN Mask */
  640. #define MEL_B_Pos 6 /*!< MEL: B Position */
  641. #define MEL_B_Msk (0x1UL << MEL_B_Pos) /*!< MEL: B Mask */
  642. #define MEL_SO_Pos 5 /*!< MEL: SO Position */
  643. #define MEL_SO_Msk (0x1UL << MEL_SO_Pos) /*!< MEL: SO Mask */
  644. #define MEL_SEC_Pos 4 /*!< MEL: SEC Position */
  645. #define MEL_SEC_Msk (0x1UL << MEL_SEC_Pos) /*!< MEL: SEC Mask */
  646. #define MEL_C_Pos 3 /*!< MEL: C Position */
  647. #define MEL_C_Msk (0x1UL << MEL_C_Pos) /*!< MEL: C Mask */
  648. #define MEL_D_Pos 2 /*!< MEL: D Position */
  649. #define MEL_D_Msk (0x1UL << MIR_D_Pos) /*!< MEL: D Mask */
  650. #define MEL_V_Pos 1 /*!< MEL: V Position */
  651. #define MEL_V_Msk (0x1UL << MIR_V_Pos) /*!< MEL: V Mask */
  652. #define MEL_G_Pos 0 /*!< MEL: G Position */
  653. #define MEL_G_Msk (0x1UL << MIR_G_Pos) /*!< MEL: G Mask */
  654. /**
  655. \brief Consortium definition for accessing mmu entry of high physical address register(MEH, CR<4,15>).
  656. */
  657. typedef union {
  658. struct {
  659. uint32_t ASID :8; /*!< bit: 0.. 7 ASID */
  660. uint32_t _reserved :4; /*!< bit: 7.. 10 Reserved */
  661. uint32_t VPN :20; /*!< bit: 11.. 31 Virtual page number */
  662. } b;
  663. uint32_t w;
  664. } MEH_Type;
  665. /* MEH Register Definitions */
  666. #define MEH_VPN_Pos 12 /*!< MEH: VPN Position */
  667. #define MEH_VPN_Msk (0xFFFFFUL << MEH_VPN_Pos) /*!< MEH: VPN Mask */
  668. #define MEH_ASID_Pos 0 /*!< MEH: ASID Position */
  669. #define MEH_ASID_Msk (0xFFUL << MEH_ASID_Pos) /*!< MEH: ASID Mask */
  670. /**
  671. \brief Consortium definition for accessing mmu entry of high physical address register(MPR, CR<6,15>).
  672. */
  673. typedef union {
  674. struct {
  675. uint32_t _reserved0: 13; /*!< bit: 0.. 12 Reserved */
  676. uint32_t page_mask: 12; /*!< bit: 13.. 24 Page mask */
  677. uint32_t _reserved1: 7; /*!< bit: 25.. 31 Reserved */
  678. } b;
  679. uint32_t w;
  680. } MPR_Type;
  681. /* MPR Register Definitions */
  682. #define MPR_PAGE_MASK_Pos 13 /*!< MPR: PAGE_MASK Position */
  683. #define MPR_PAGE_MASK_Msk (0xFFFUL << MPR_PAGE_MASK_Pos) /*!< MPR: PAGE_MASK Mask */
  684. /**
  685. \brief Consortium definition for accessing mmu entry of high physical address register(CR<8,15>).
  686. */
  687. typedef union {
  688. struct {
  689. uint32_t ASID: 8; /*!< bit: 0.. 7 ASID */
  690. uint32_t _reserved: 17; /*!< bit: 8.. 24 Reserved */
  691. uint32_t TLBINV_INDEX: 1; /*!< bit: 25 TLBINV_INDEX */
  692. uint32_t TLBINV_ALL: 1; /*!< bit: 26 TLBINV_ALL */
  693. uint32_t TLBINV: 1; /*!< bit: 27 TLBINV */
  694. uint32_t TLBWR: 1; /*!< bit: 28 TLBWR */
  695. uint32_t TLBWI: 1; /*!< bit: 29 TLBWI */
  696. uint32_t TLBR: 1; /*!< bit: 30 TLBR */
  697. uint32_t TLBP: 1; /*!< bit: 31 TLBP */
  698. } b;
  699. uint32_t w;
  700. } MCIR_Type;
  701. /* MCIR Register Definitions */
  702. #define MCIR_TLBP_Pos 31 /*!< MCIR: TLBP Position */
  703. #define MCIR_TLBP_Msk (0x1UL << MCIR_TLBP_Pos) /*!< MCIR: TLBP Mask */
  704. #define MCIR_TLBR_Pos 30 /*!< MCIR: TLBR Position */
  705. #define MCIR_TLBR_Msk (0x1UL << MCIR_TLBR_Pos) /*!< MCIR: TLBR Mask */
  706. #define MCIR_TLBWI_Pos 29 /*!< MCIR: TLBWI Position */
  707. #define MCIR_TLBWI_Msk (0x1UL << MCIR_TLBWI_Pos) /*!< MCIR: TLBWI Mask */
  708. #define MCIR_TLBWR_Pos 28 /*!< MCIR: TLBWR Position */
  709. #define MCIR_TLBWR_Msk (0x1UL << MCIR_TLBWR_Pos) /*!< MCIR: TLBWR Mask */
  710. #define MCIR_TLBINV_Pos 27 /*!< MCIR: TLBINV Position */
  711. #define MCIR_TLBINV_Msk (0x1UL << MCIR_TLBINV_Pos) /*!< MCIR: TLBINV Mask */
  712. #define MCIR_TLBINV_ALL_Pos 26 /*!< MCIR: TLBINV_ALL Position */
  713. #define MCIR_TLBINV_ALL_Msk (0x1UL << MCIR_TLBINV_ALL_Pos) /*!< MCIR: TLBINV_ALL Mask */
  714. #define MCIR_TLBINV_INDEX_Pos 25 /*!< MCIR: TLBINV_INDEX Position */
  715. #define MCIR_TLBINV_INDEX_Msk (0x1UL << MCIR_TLBINV_INDEX_Pos) /*!< MCIR: TLBINV_INDEX Mask */
  716. #define MCIR_ASID_Pos 0 /*!< MCIR: ASID Position */
  717. #define MCIR_ASID_Msk (0xFFUL << MCIR_ASID_Pos) /*!< MCIR: ASID Mask */
  718. /*@} end of group CSI_CORE */
  719. /**
  720. \ingroup CSI_core_register
  721. \defgroup CSI_CACHE
  722. \brief Type definitions for the cache Registers
  723. @{
  724. */
  725. /**
  726. \brief Consortium definition for accessing protection area selection register(CFR,CR<17,0>).
  727. */
  728. typedef union {
  729. struct {
  730. uint32_t CACHE_SEL: 2; /*!< bit: 0..1 Instruction and data cache selection */
  731. uint32_t _reserved0: 2; /*!< bit: 2..3 Reserved */
  732. uint32_t INV: 1; /*!< bit: 4 Invalid data in cache */
  733. uint32_t CLR: 1; /*!< bit: 5 Clear the dirty tlb table */
  734. uint32_t OMS: 1; /*!< bit: 6 Cache invalid and clear operation mode (one line or all line)*/
  735. uint32_t ITS: 1; /*!< bit: 7 Cache invalid and clear operation mode (CIR used as virtual index or SET/WAY/LEVE index)*/
  736. uint32_t _reserved1: 8; /*!< bit: 8..15 Reserved */
  737. uint32_t BHT_INV: 1; /*!< bit: 16 Invalid data in branch history table */
  738. uint32_t _reserved2: 14; /*!< bit: 17..30 Reserved */
  739. uint32_t LICF: 1; /*!< bit: 31 Failure of clearing or invalid cache line */
  740. } b; /*!< Structure Access by bit */
  741. uint32_t w; /*!< Type Access by whole register */
  742. } CFR_Type;
  743. #define CFR_LICF_Pos 31U /*!< CFR: LICF Position */
  744. #define CFR_LICF_Msk (0x1UL << CFR_LICF_Pos) /*!< CFR: LICF Mask */
  745. #define CFR_BHT_INV_Pos 16U /*!< CFR: BHT Position */
  746. #define CFR_BHT_INV_Msk (0x1UL << CFR_BHT_INV_Pos) /*!< CFR: BHT Mask */
  747. #define CFR_ITS_Pos 7U /*!< CFR: ITS Position */
  748. #define CFR_ITS_Msk (0x1UL << CFR_ITS_Pos) /*!< CFR: ITS Mask */
  749. #define CFR_OMS_Pos 6U /*!< CFR: OMS Position */
  750. #define CFR_OMS_Msk (0x1UL << CFR_OMS_Pos) /*!< CFR: OMS Mask */
  751. #define CFR_CLR_Pos 5U /*!< CFR: CLR Position */
  752. #define CFR_CLR_Msk (0x1UL << CFR_CLR_Pos) /*!< CFR: CLR Mask */
  753. #define CFR_INV_Pos 4U /*!< CFR: INV Position */
  754. #define CFR_INV_Msk (0x1UL << CFR_INV_Pos) /*!< CFR: INV Mask */
  755. #define CFR_CACHE_SEL_Pos 0 /*!< CFR: CACHE_SEL Position */
  756. #define CFR_CACHE_SEL_Msk (0x3UL << CFR_CACHE_SEL_Pos) /*!< CFR: CACHE_SEL Masok */
  757. /* CFR Register Definitions */
  758. /*@} end of group CSI_CACHE */
  759. /**
  760. \ingroup CSI_core_register
  761. \defgroup CSI_CACHE
  762. \brief Type definitions for the cache Registers
  763. @{
  764. */
  765. #define SSEG0_BASE_ADDR 0x80000000
  766. #define CACHE_RANGE_MAX_SIZE 0x80000
  767. #define INS_CACHE (1 << 0)
  768. #define DATA_CACHE (1 << 1)
  769. #define CACHE_INV (1 << 4)
  770. #define CACHE_CLR (1 << 5)
  771. #define CACHE_OMS (1 << 6)
  772. #define CACHE_ITS (1 << 7)
  773. #define CACHE_LICF (1 << 31)
  774. #define L1_CACHE_SHIFT 4 /* 16 Bytes */
  775. #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
  776. /**
  777. \brief Mask and shift a bit field value for use in a register bit range.
  778. \param[in] field Name of the register bit field.
  779. \param[in] value Value of the bit field.
  780. \return Masked and shifted value.
  781. */
  782. #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
  783. /**
  784. \brief Mask and shift a register value to extract a bit filed value.
  785. \param[in] field Name of the register bit field.
  786. \param[in] value Value of register.
  787. \return Masked and shifted bit field value.
  788. */
  789. #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
  790. /*@} end of group CSI_core_bitfield */
  791. /**
  792. \ingroup CSI_tcm_register
  793. \defgroup CSI_TCM
  794. \brief Type definitions for the tcm Registers
  795. @{
  796. */
  797. /**
  798. \brief Consortium definition for accessing protection area selection register(ITCMCR,CR<22,1>).
  799. */
  800. typedef union {
  801. struct {
  802. uint32_t EN: 1; /*!< bit: 0 Instruction Tightly-Coupled Memory enable */
  803. uint32_t _reserved0: 1; /*!< bit: 1 Reserved */
  804. uint32_t SIF: 1; /*!< bit: 2 Slave interface access ITCM */
  805. uint32_t _reserved1: 1; /*!< bit: 3 Reserved */
  806. uint32_t Size: 4; /*!< bit: 4..7 Size of ITCM */
  807. uint32_t _reserved2: 1; /*!< bit: 8 Reserved */
  808. uint32_t Delay: 1; /*!< bit: 9 The time from access ITCM to data come back. */
  809. uint32_t _reserved3: 2; /*!< bit: 10..11 Reserved */
  810. uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of DTCM */
  811. } b; /*!< Structure Access by bit */
  812. uint32_t w; /*!< Type Access by whole register */
  813. } ITCMCR_Type;
  814. #define ITCMCR_Base_Address_Pos 12U /*!< ITCMCR: Base_Address Position */
  815. #define ITCMCR_Base_Address_Msk (0xfffffUL << ITCMCR_Base_Address_Pos) /*!< ITCMCR: Base_Address Mask */
  816. #define ITCMCR_Delay_Pos 9U /*!< ITCMCR: Delay Position */
  817. #define ITCMCR_Delay_Msk (0x1UL << ITCMCR_Delay_Pos) /*!< ITCMCR: Delay Mask */
  818. #define ITCMCR_Size_Pos 4U /*!< ITCMCR: Size Position */
  819. #define ITCMCR_Size_Msk (0xfUL << ITCMCR_Size_Pos) /*!< ITCMCR: Size Mask */
  820. #define ITCMCR_SIF_Pos 2U /*!< ITCMCR: SIF Position */
  821. #define ITCMCR_SIF_Msk (0x1UL << ITCMCR_SIF_Pos) /*!< ITCMCR: SIF Mask */
  822. #define ITCMCR_EN_Pos 0U /*!< ITCMCR: EN Position */
  823. #define ITCMCR_EN_Msk (0x1UL << ITCMCR_EN_Pos) /*!< ITCMCR: EN Mask */
  824. /**
  825. \brief Consortium definition for accessing protection area selection register(DTCMCR,CR<23,1>).
  826. */
  827. typedef union {
  828. struct {
  829. uint32_t EN: 1; /*!< bit: 0 Data Tightly-Coupled Memory enable */
  830. uint32_t _reserved0: 1; /*!< bit: 1 Reserved */
  831. uint32_t SIF: 1; /*!< bit: 2 Slave interface access DTCM */
  832. uint32_t _reserved1: 1; /*!< bit: 3 Reserved */
  833. uint32_t Size: 4; /*!< bit: 4..7 Size of DTCM */
  834. uint32_t _reserved2: 1; /*!< bit: 8 Reserved */
  835. uint32_t Delay: 1; /*!< bit: 9 The time from access DTCM to data come back.*/
  836. uint32_t _reserved3: 2; /*!< bit: 10..11 Reserved */
  837. uint32_t Base_Address: 20; /*!< bit: 12..31 Base address of DTCM */
  838. } b; /*!< Structure Access by bit */
  839. uint32_t w; /*!< Type Access by whole register */
  840. } DTCMCR_Type;
  841. #define DTCMCR_Base_Address_Pos 12U /*!< DTCMCR: Base_Address Position */
  842. #define DTCMCR_Base_Address_Msk (0xfffffUL << DTCMCR_Base_Address_Pos) /*!< DTCMCR: Base_Address Mask */
  843. #define DTCMCR_Delay_Pos 9U /*!< DTCMCR: Delay Position */
  844. #define DTCMCR_Delay_Msk (0x1UL << DTCMCR_Delay_Pos) /*!< DTCMCR: Delay Mask */
  845. #define DTCMCR_Size_Pos 4U /*!< DTCMCR: Size Position */
  846. #define DTCMCR_Size_Msk (0xfUL << DTCMCR_Size_Pos) /*!< DTCMCR: Size Mask */
  847. #define DTCMCR_SIF_Pos 2U /*!< DTCMCR: SIF Position */
  848. #define DTCMCR_SIF_Msk (0x1UL << DTCMCR_SIF_Pos) /*!< DTCMCR: SIF Mask */
  849. #define DTCMCR_EN_Pos 0U /*!< DTCMCR: EN Position */
  850. #define DTCMCR_EN_Msk (0x1UL << DTCMCR_EN_Pos) /*!< DTCMCR: EN Mask */
  851. /*@} end of group CSI_TCM_bitfield */
  852. /**
  853. \ingroup CSI_ECC_register
  854. \defgroup CSI_ECC
  855. \brief Type definitions for the ECC Registers
  856. @{
  857. */
  858. typedef union {
  859. struct {
  860. uint32_t Index: 17; /*!< bit: 0..16 RAM index */
  861. uint32_t _reserved0: 1; /*!< bit: 2..23 Reserved */
  862. uint32_t Way: 2; /*!< bit: 18..19 ICACHE/DCACHE WAY */
  863. uint32_t _reserved1: 2; /*!< bit: 20..21 Reserved */
  864. uint32_t RAMID: 8; /*!< bit: 22..29 ECC RAM ID */
  865. uint32_t ERR_TYPE: 2; /*!< bit: 30..31 ECC ERR TYPE */
  866. } b;
  867. uint32_t w;
  868. } ERRLC_Type;
  869. #define ERRLC_ERR_TYPE_Pos 30U /*!< ERRLC: ERR_TYPE Position */
  870. #define ERRLC_ERR_TYPE_Msk (0x3UL << ERRLC_ERR_TYPE_Pos) /*!< ERRLC: ERR_TYPE Mask */
  871. #define ERRLC_RAMID_Pos 22U /*!< ERRLC: RAMID Position */
  872. #define ERRLC_RAMID_Msk (0xFFUL << ERRLC_RAMID_Pos) /*!< ERRLC: RAMID Mask */
  873. #define ERRLC_Way_Pos 18U /*!< ERRLC: Way Position */
  874. #define ERRLC_Way_Msk (0x3UL << ERRLC_Way_Pos) /*!< ERRLC: Way Mask */
  875. #define ERRLC_Index_Pos 0U /*!< ERRLC: Index Position */
  876. #define ERRLC_Index_Msk (0x1FFFFUL << ERRLC_Index_Pos) /*!< ERRLC: Index Mask */
  877. typedef union {
  878. struct {
  879. uint32_t INJ_EN: 1; /*!< bit: 0 ECC inject enable */
  880. uint32_t ERR_TYPE: 1; /*!< bit: 1 ECC error type */
  881. uint32_t _reserved0: 22; /*!< bit: 2..23 Reserved */
  882. uint32_t RAMID: 8; /*!< bit: 24..31 ECC RAMID */
  883. } b; /*!< Structure Access by bit */
  884. uint32_t w; /*!< Type Access by whole register */
  885. } ERRINJCR_Type;
  886. #define ERRINJCR_RAMID_Pos 24U /*!< ERRINJCR: RAMID Position */
  887. #define ERRINJCR_RAMID_Msk (0xFFUL << ERRINJCR_RAMID_Pos) /*!< ERRINJCR: RAMID Mask */
  888. #define ERRINJCR_ERR_TYPE_Pos 1U /*!< ERRINJCR: ERR_TYPE Position */
  889. #define ERRINJCR_ERR_TYPE_Msk (0x1UL << ERRINJCR_ERR_TYPE_Pos) /*!< ERRINJCR: ERR_TYPE Mask */
  890. #define ERRINJCR_INJ_EN_Pos 0U /*!< ERRINJCR: INJ_EN Position */
  891. #define ERRINJCR_INJ_EN_Msk (0x1UL << ERRINJCR_INJ_EN_Pos) /*!< ERRINJCR: INJ_EN Mask */
  892. /*@} end of group CSI_ECC_bitfield */
  893. /*******************************************************************************
  894. * Hardware Abstraction Layer
  895. Core Function Interface contains:
  896. - Core VIC Functions
  897. - Core CORET Functions
  898. - Core Register Access Functions
  899. ******************************************************************************/
  900. /* The following MACROS handle generation of the register offset and byte masks */
  901. #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
  902. #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
  903. /* ########################## Cache functions #################################### */
  904. /**
  905. \ingroup CSI_Core_FunctionInterface
  906. \defgroup CSI_Core_CacheFunctions Cache Functions
  907. \brief Functions that configure Instruction and Data cache.
  908. @{
  909. */
  910. /**
  911. \brief Enable I-Cache
  912. \details Turns on I-Cache
  913. */
  914. __STATIC_INLINE void csi_icache_enable (void)
  915. {
  916. __set_CCR(__get_CCR() | 0x00000004);
  917. }
  918. /**
  919. \brief Disable I-Cache
  920. \details Turns off I-Cache
  921. */
  922. __STATIC_INLINE void csi_icache_disable (void)
  923. {
  924. __set_CCR(__get_CCR() & 0xFFFFFFFB);
  925. }
  926. /**
  927. \brief Invalidate I-Cache
  928. \details Invalidates I-Cache
  929. */
  930. __STATIC_INLINE void csi_icache_invalid (void)
  931. {
  932. __set_CFR(0x11);
  933. __set_CFR(INS_CACHE | CACHE_INV);
  934. }
  935. /**
  936. \brief Enable D-Cache
  937. \details Turns on D-Cache
  938. \note I-Cache also turns on.
  939. */
  940. __STATIC_INLINE void csi_dcache_enable (void)
  941. {
  942. __set_CCR(__get_CCR() | 0x00000008);
  943. }
  944. /**
  945. \brief Disable D-Cache
  946. \details Turns off D-Cache
  947. \note I-Cache also turns off.
  948. */
  949. __STATIC_INLINE void csi_dcache_disable (void)
  950. {
  951. __set_CCR(__get_CCR() & 0xFFFFFFF7);
  952. }
  953. /**
  954. \brief Invalidate D-Cache
  955. \details Invalidates D-Cache
  956. \note I-Cache also invalid
  957. */
  958. __STATIC_INLINE void csi_dcache_invalid (void)
  959. {
  960. __set_CFR(DATA_CACHE | CACHE_INV);
  961. }
  962. /**
  963. \brief Clean D-Cache
  964. \details Cleans D-Cache
  965. \note I-Cache also cleans
  966. */
  967. __STATIC_INLINE void csi_dcache_clean (void)
  968. {
  969. __set_CFR(DATA_CACHE | CACHE_CLR);
  970. }
  971. /**
  972. \brief Clean & Invalidate D-Cache
  973. \details Cleans and Invalidates D-Cache
  974. \note I-Cache also flush.
  975. */
  976. __STATIC_INLINE void csi_dcache_clean_invalid (void)
  977. {
  978. __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV);
  979. }
  980. __STATIC_INLINE void set_cache_range (uint32_t start, uint32_t end, uint32_t value)
  981. {
  982. if (!(start & SSEG0_BASE_ADDR) || (end - start) &~(CACHE_RANGE_MAX_SIZE - 1)) {
  983. __set_CFR(value);
  984. }
  985. if (value & INS_CACHE) {
  986. csi_icache_disable();
  987. }
  988. uint32_t i;
  989. for (i = start; i < end; i += L1_CACHE_BYTES) {
  990. __set_CIR(i);
  991. __set_CFR(CACHE_OMS | value);
  992. }
  993. if (end & (L1_CACHE_BYTES-1)) {
  994. __set_CIR(end);
  995. __set_CFR(CACHE_OMS | value);
  996. }
  997. if (value & INS_CACHE) {
  998. csi_icache_enable();
  999. }
  1000. }
  1001. /**
  1002. \brief D-Cache Invalidate by address
  1003. \details Invalidates D-Cache for the given address
  1004. \param[in] addr address (aligned to 16-byte boundary)
  1005. \param[in] dsize size of memory block (aligned to 16-byte boundary)
  1006. */
  1007. __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
  1008. {
  1009. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV));
  1010. }
  1011. /**
  1012. \brief D-Cache Clean by address
  1013. \details Cleans D-Cache for the given address
  1014. \param[in] addr address (aligned to 16-byte boundary)
  1015. \param[in] dsize size of memory block (aligned to 16-byte boundary)
  1016. */
  1017. __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
  1018. {
  1019. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR));
  1020. }
  1021. /**
  1022. \brief D-Cache Clean and Invalidate by address
  1023. \details Cleans and invalidates D_Cache for the given address
  1024. \param[in] addr address (aligned to 16-byte boundary)
  1025. \param[in] dsize size of memory block (aligned to 16-byte boundary)
  1026. */
  1027. __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
  1028. {
  1029. set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV));
  1030. }
  1031. /*@} end of CSI_Core_CacheFunctions */
  1032. /* ########################## MMU functions #################################### */
  1033. /**
  1034. \ingroup CSI_Core_FunctionInterface
  1035. \defgroup CSI_Core_MMUFunctions MMU Functions
  1036. \brief Functions that configure MMU.
  1037. @{
  1038. */
  1039. typedef struct {
  1040. uint32_t global: 1; /* tlb page global access. */
  1041. uint32_t valid: 1; /* tlb page valid */
  1042. uint32_t writeable: 1; /* tlb page writeable */
  1043. uint32_t cacheable: 1; /* tlb page cacheable*/
  1044. uint32_t is_secure: 1; /* tlb page security access */
  1045. uint32_t strong_order: 1; /* the sequence of accessing data on tlb page is corresponding to the program flow? */
  1046. uint32_t bufferable: 1; /* tlb page bufferable */
  1047. } page_attr_t;
  1048. typedef enum {
  1049. PAGE_SIZE_4KB = 0x000,
  1050. PAGE_SIZE_16KB = 0x003,
  1051. PAGE_SIZE_64KB = 0x00F,
  1052. PAGE_SIZE_256KB = 0x03F,
  1053. PAGE_SIZE_1MB = 0x0FF,
  1054. PAGE_SIZE_4MB = 0x3FF,
  1055. PAGE_SIZE_16MB = 0xFFF
  1056. } page_size_e;
  1057. /**
  1058. \brief enable mmu
  1059. \details
  1060. */
  1061. __STATIC_INLINE void csi_mmu_enable(void)
  1062. {
  1063. __set_CCR(__get_CCR() | (1u << CCR_MP_Pos));
  1064. }
  1065. /**
  1066. \brief disable mmu
  1067. \details
  1068. */
  1069. __STATIC_INLINE void csi_mmu_disable(void)
  1070. {
  1071. __set_CCR(__get_CCR() & (~(1u << CCR_MP_Pos)));
  1072. }
  1073. /**
  1074. \brief create page with feature.
  1075. \details
  1076. \param [in] vaddr virtual address.
  1077. \param [in] paddr physical address.
  1078. \param [in] asid address sapce id (default: 0).
  1079. \param [in] attr \ref page_attr_t. tlb page attribute.
  1080. */
  1081. __STATIC_INLINE void csi_mmu_set_tlb(uint32_t vaddr, uint32_t paddr, uint32_t asid, page_attr_t attr)
  1082. {
  1083. MPR_Type pgmask;
  1084. MEH_Type meh;
  1085. MEL_Type mel;
  1086. uint32_t vaddr_bit;
  1087. uint32_t page_feature = 0;
  1088. page_feature |= attr.global << MEL_G_Pos | attr.valid << MEL_V_Pos |
  1089. attr.writeable << MEL_D_Pos | attr.cacheable << MEL_C_Pos |
  1090. attr.is_secure << MEL_SEC_Pos | attr.strong_order << MEL_SO_Pos |
  1091. attr.bufferable << MEL_B_Pos;
  1092. pgmask.w = __get_MPR();
  1093. vaddr_bit = 44 - __FF0(~((uint32_t)pgmask.b.page_mask));
  1094. meh.b.ASID = (uint8_t)asid;
  1095. meh.b.VPN = (vaddr & ((~pgmask.w | 0xFE000000) & 0xFFFFE000)) >> MEH_VPN_Pos;
  1096. __set_MEH(meh.w);
  1097. __set_MCIR(1u << MCIR_TLBP_Pos);
  1098. mel.w = ((paddr & ~(pgmask.b.page_mask << 12)) | page_feature);
  1099. if (vaddr & (1 << vaddr_bit)) {
  1100. __set_MEL1(mel.w);
  1101. }
  1102. else {
  1103. __set_MEL0(mel.w);
  1104. }
  1105. if (__get_MIR() & (1 << MIR_P_Pos)) {
  1106. __set_MCIR(1u << MCIR_TLBWR_Pos);
  1107. } else {
  1108. __set_MCIR(1u << MCIR_TLBWI_Pos);
  1109. }
  1110. }
  1111. /**
  1112. \brief enble mmu
  1113. \details
  1114. \param [in] size tlb page size.
  1115. */
  1116. __STATIC_INLINE void csi_mmu_set_pagesize(page_size_e size)
  1117. {
  1118. MPR_Type pgmask;
  1119. pgmask.b.page_mask = size;
  1120. __set_MPR(pgmask.w);
  1121. }
  1122. /**
  1123. \brief read MEH, MEL0, MEL1 by tlb index.
  1124. \details
  1125. \param [in] index tlb index(0, 1, 2, ...)
  1126. \param [out] meh pointer to variable for retrieving MEH.
  1127. \param [out] mel0 pointer to variable for retrieving MEL0.
  1128. \param [out] mel1 pointer to variable for retrieving MEL1.
  1129. */
  1130. __STATIC_INLINE void csi_mmu_read_by_index(uint32_t index, uint32_t *meh, uint32_t *mel0, uint32_t *mel1)
  1131. {
  1132. MIR_Type mir;
  1133. if (meh == NULL || mel0 == NULL || mel1 == NULL) {
  1134. return;
  1135. }
  1136. mir.b.Index = index;
  1137. __set_MIR(mir.w);
  1138. __set_MCIR(1u << MCIR_TLBR_Pos);
  1139. *meh = __get_MEH();
  1140. *mel0 = __get_MEL0();
  1141. *mel1 = __get_MEL1();
  1142. }
  1143. /**
  1144. \brief flush all mmu tlb.
  1145. \details
  1146. */
  1147. __STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
  1148. {
  1149. __set_MCIR(1u << MCIR_TLBINV_ALL_Pos);
  1150. }
  1151. /**
  1152. \brief flush mmu tlb by index.
  1153. \details
  1154. */
  1155. __STATIC_INLINE void csi_mmu_invalid_tlb_by_index(uint32_t index)
  1156. {
  1157. MIR_Type mir;
  1158. mir.b.Index = index;
  1159. __set_MIR(mir.w);
  1160. __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
  1161. }
  1162. /**
  1163. \brief flush mmu tlb by virtual address.
  1164. \details
  1165. */
  1166. __STATIC_INLINE void csi_mmu_invalid_tlb_by_vaddr(uint32_t vaddr, uint32_t asid)
  1167. {
  1168. __set_MEH(vaddr | (asid & MEH_ASID_Msk));
  1169. __set_MCIR(1u << MCIR_TLBP_Pos);
  1170. if (__get_MIR() & (1 << MIR_P_Pos)) {
  1171. return;
  1172. } else {
  1173. __set_MCIR(1u << MCIR_TLBINV_INDEX_Pos);
  1174. }
  1175. }
  1176. /*@} end of CSI_Core_MMUFunctions */
  1177. /* ########################## MPU functions #################################### */
  1178. /**
  1179. \ingroup CSI_Core_FunctionInterface
  1180. \defgroup CSI_Core_MPUFunctions MPU Functions
  1181. \brief Functions that configure MPU.
  1182. @{
  1183. */
  1184. typedef enum {
  1185. REGION_SIZE_128B = 0x6,
  1186. REGION_SIZE_256B = 0x7,
  1187. REGION_SIZE_512B = 0x8,
  1188. REGION_SIZE_1KB = 0x9,
  1189. REGION_SIZE_2KB = 0xA,
  1190. REGION_SIZE_4KB = 0xB,
  1191. REGION_SIZE_8KB = 0xC,
  1192. REGION_SIZE_16KB = 0xD,
  1193. REGION_SIZE_32KB = 0xE,
  1194. REGION_SIZE_64KB = 0xF,
  1195. REGION_SIZE_128KB = 0x10,
  1196. REGION_SIZE_256KB = 0x11,
  1197. REGION_SIZE_512KB = 0x12,
  1198. REGION_SIZE_1MB = 0x13,
  1199. REGION_SIZE_2MB = 0x14,
  1200. REGION_SIZE_4MB = 0x15,
  1201. REGION_SIZE_8MB = 0x16,
  1202. REGION_SIZE_16MB = 0x17,
  1203. REGION_SIZE_32MB = 0x18,
  1204. REGION_SIZE_64MB = 0x19,
  1205. REGION_SIZE_128MB = 0x1A,
  1206. REGION_SIZE_256MB = 0x1B,
  1207. REGION_SIZE_512MB = 0x1C,
  1208. REGION_SIZE_1GB = 0x1D,
  1209. REGION_SIZE_2GB = 0x1E,
  1210. REGION_SIZE_4GB = 0x1F
  1211. } region_size_e;
  1212. typedef enum {
  1213. AP_BOTH_INACCESSIBLE = 0,
  1214. AP_SUPER_RW_USER_INACCESSIBLE,
  1215. AP_SUPER_RW_USER_RDONLY,
  1216. AP_BOTH_RW
  1217. } access_permission_e;
  1218. typedef struct {
  1219. uint32_t nx: 1;
  1220. access_permission_e ap: 2; /* super user and normal user access.*/
  1221. uint32_t s: 1;
  1222. uint32_t c: 1; /* cacheable */
  1223. uint32_t so: 1;
  1224. uint32_t b: 1;
  1225. } mpu_region_attr_t;
  1226. /**
  1227. \brief enable mpu
  1228. \details
  1229. */
  1230. __STATIC_INLINE void csi_mpu_enable(void)
  1231. {
  1232. __set_CCR(__get_CCR() | CCR_MP_Msk);
  1233. }
  1234. /**
  1235. \brief disable mpu
  1236. \details
  1237. */
  1238. __STATIC_INLINE void csi_mpu_disable(void)
  1239. {
  1240. __set_CCR(__get_CCR() & (~CCR_MP_Msk));
  1241. }
  1242. /**
  1243. \brief configure memory protected region.
  1244. \details
  1245. \param [in] idx memory protected region (0, 1, 2, 3.).
  1246. \param [in] base_addr base address must be aligned with page size.
  1247. \param [in] size \ref region_size_e. memory protected region size.
  1248. \param [in] attr \ref region_size_t. memory protected region attribute.
  1249. \param [in] enable enable or disable memory protected region.
  1250. */
  1251. __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
  1252. mpu_region_attr_t attr, uint32_t enable)
  1253. {
  1254. uint32_t op_idx;
  1255. if (idx > 15) {
  1256. return;
  1257. }
  1258. CAPR_Type capr;
  1259. PACR_Type pacr;
  1260. PRSR_Type prsr;
  1261. ATTR0_Type reg_attr;
  1262. if (idx <= 7) {
  1263. capr.w = __get_CAPR();
  1264. reg_attr.w = __get_ATTR0();
  1265. op_idx = idx;
  1266. } else {
  1267. capr.w = __get_CAPR1();
  1268. reg_attr.w = __get_ATTR1();
  1269. op_idx = idx - 8;
  1270. }
  1271. pacr.w = __get_PACR();
  1272. prsr.w = __get_PRSR();
  1273. pacr.w = (base_addr & PACR_BASE_ADDR_Msk) | (size << PACR_SIZE_Pos);
  1274. pacr.w &= ~(((1u << (size - 6)) - 1) << 7);
  1275. pacr.b.E = enable;
  1276. prsr.b.RID = idx;
  1277. __set_PRSR(prsr.w);
  1278. capr.w &= ~((0x1 << op_idx) | (0x3 << (op_idx * 2 + 8)) | (0x1 << (op_idx + 24)));
  1279. capr.w = (capr.w | (attr.nx << op_idx) | (attr.ap << (op_idx * 2 + 8)) | (attr.s << (op_idx + 24)));
  1280. reg_attr.w &= ~(0x7 << (op_idx << 2));
  1281. reg_attr.w |= ((attr.c | (attr.so << 1) | (attr.b << 2)) << (op_idx << 2));
  1282. if (idx <= 7) {
  1283. __set_CAPR(capr.w);
  1284. __set_ATTR0(reg_attr.w);
  1285. } else {
  1286. __set_CAPR1(capr.w);
  1287. __set_ATTR1(reg_attr.w);
  1288. }
  1289. __set_PACR(pacr.w);
  1290. }
  1291. /**
  1292. \brief enable mpu region by idx.
  1293. \details
  1294. \param [in] idx memory protected region (0, 1, 2, 3.).
  1295. */
  1296. __STATIC_INLINE void csi_mpu_enable_region(uint32_t idx)
  1297. {
  1298. if (idx > 15) {
  1299. return;
  1300. }
  1301. __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
  1302. __set_PACR(__get_PACR() | PACR_E_Msk);
  1303. }
  1304. /**
  1305. \brief disable mpu region by idx.
  1306. \details
  1307. \param [in] idx memory protected region (0, 1, 2, 3.).
  1308. */
  1309. __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
  1310. {
  1311. if (idx > 15) {
  1312. return;
  1313. }
  1314. __set_PRSR((__get_PRSR() & (~PRSR_RID_Msk)) | idx);
  1315. __set_PACR(__get_PACR() & (~PACR_E_Msk));
  1316. }
  1317. /*@} end of CSI_Core_MPUFunctions */
  1318. /* ########################## TCM functions #################################### */
  1319. /**
  1320. \ingroup CSI_Core_FunctionInterface
  1321. \defgroup CSI_Core_TCMFunctions TCM Functions
  1322. \brief Functions that configure TCM.
  1323. @{
  1324. */
  1325. /**
  1326. \brief Enable ITCM
  1327. \details Turns on ITCM
  1328. */
  1329. __STATIC_INLINE void csi_itcm_enable (void)
  1330. {
  1331. __set_ITCMCR(__get_ITCMCR() | ITCMCR_EN_Msk);
  1332. }
  1333. /**
  1334. \brief Enable DTCM
  1335. \details Turns on DTCM
  1336. */
  1337. __STATIC_INLINE void csi_dtcm_enable (void)
  1338. {
  1339. __set_DTCMCR(__get_DTCMCR() | DTCMCR_EN_Msk);
  1340. }
  1341. /**
  1342. \brief Enable ITCM
  1343. \details Turns on ITCM
  1344. */
  1345. __STATIC_INLINE void csi_itcm_disable (void)
  1346. {
  1347. __set_ITCMCR(__get_ITCMCR() & (~ITCMCR_EN_Msk));
  1348. }
  1349. /**
  1350. \brief Enable DTCM
  1351. \details Turns on DTCM
  1352. */
  1353. __STATIC_INLINE void csi_dtcm_disable (void)
  1354. {
  1355. __set_DTCMCR(__get_DTCMCR() & (~DTCMCR_EN_Msk));
  1356. }
  1357. /**
  1358. \brief Enable ITCM slave interface access
  1359. \details Enable ITCM slave interface access
  1360. */
  1361. __STATIC_INLINE void csi_itcm_enable_slave_access(void)
  1362. {
  1363. __set_ITCMCR(__get_ITCMCR() | ITCMCR_SIF_Msk);
  1364. }
  1365. /**
  1366. \brief Disable ITCM slave interface access
  1367. \details Disable ITCM slave interface access
  1368. */
  1369. __STATIC_INLINE void csi_itcm_disable_slave_access(void)
  1370. {
  1371. __set_ITCMCR(__get_ITCMCR() & (~ITCMCR_SIF_Msk));
  1372. }
  1373. /**
  1374. \brief Enable DTCM slave interface access
  1375. \details Enable DTCM slave interface access
  1376. */
  1377. __STATIC_INLINE void csi_dtcm_enable_slave_access(void)
  1378. {
  1379. __set_DTCMCR(__get_DTCMCR() | DTCMCR_SIF_Msk);
  1380. }
  1381. /**
  1382. \brief Disable DTCM slave interface access
  1383. \details Disable DTCM slave interface access
  1384. */
  1385. __STATIC_INLINE void csi_dtcm_disable_slave_access(void)
  1386. {
  1387. __set_DTCMCR(__get_DTCMCR() & (~DTCMCR_SIF_Msk));
  1388. }
  1389. /**
  1390. \brief Get ITCM Size
  1391. \details Get ITCM Size
  1392. \return ITCM size (bytes).
  1393. */
  1394. __STATIC_INLINE uint32_t csi_itcm_get_size(void)
  1395. {
  1396. ITCMCR_Type sizemask;
  1397. uint32_t ret;
  1398. sizemask.w = __get_ITCMCR();
  1399. ret = sizemask.b.Size;
  1400. return (1 << ret) << 10;
  1401. }
  1402. /**
  1403. \brief Get DTCM Size
  1404. \details Get DTCM Size
  1405. \return DTCM size (bytes).
  1406. */
  1407. __STATIC_INLINE uint32_t csi_dtcm_get_size(void)
  1408. {
  1409. DTCMCR_Type sizemask;
  1410. uint32_t ret;
  1411. sizemask.w = __get_DTCMCR();
  1412. ret = sizemask.b.Size;
  1413. return (1 << ret) << 10;
  1414. }
  1415. /**
  1416. \brief Get ITCM Delay
  1417. \details Get ITCM Delay
  1418. \return delay time.
  1419. */
  1420. __STATIC_INLINE uint32_t csi_itcm_get_delay(void)
  1421. {
  1422. ITCMCR_Type delaymask;
  1423. uint32_t ret;
  1424. delaymask.w = __get_ITCMCR();
  1425. ret = delaymask.b.Delay;
  1426. return ret;
  1427. }
  1428. /**
  1429. \brief Get DTCM Delay
  1430. \details Get DTCM Delay
  1431. \return delay time.
  1432. */
  1433. __STATIC_INLINE uint32_t csi_dtcm_get_delay(void)
  1434. {
  1435. DTCMCR_Type delaymask;
  1436. uint32_t ret;
  1437. delaymask.w = __get_DTCMCR();
  1438. ret = delaymask.b.Delay;
  1439. return ret;
  1440. }
  1441. /**
  1442. \brief Set ITCM Base Address
  1443. \details Set ITCM Base Address
  1444. \param [in] base_addr itcm base address.
  1445. */
  1446. __STATIC_INLINE void csi_itcm_set_base_addr(uint32_t base_addr)
  1447. {
  1448. __set_ITCMCR((__get_ITCMCR() & (~ITCMCR_Base_Address_Msk)) | (base_addr & ITCMCR_Base_Address_Msk));
  1449. }
  1450. /**
  1451. \brief Set DTCM Base Address
  1452. \details Set DTCM Base Address
  1453. \param [in] base_addr dtcm base address.
  1454. */
  1455. __STATIC_INLINE void csi_dtcm_set_base_addr(uint32_t base_addr)
  1456. {
  1457. __set_DTCMCR((__get_DTCMCR() & (~DTCMCR_Base_Address_Msk)) | (base_addr & DTCMCR_Base_Address_Msk));
  1458. }
  1459. /*@} end of CSI_Core_TCMFunctions */
  1460. /* ########################## ECC functions #################################### */
  1461. /**
  1462. \ingroup CSI_Core_FunctionInterface
  1463. \defgroup CSI_Core_ECCFunctions ECC Functions
  1464. \brief Functions that configure ECC.
  1465. @{
  1466. */
  1467. typedef enum {
  1468. ECC_ERROR_CORRECTABLE = 0,
  1469. ECC_ERROR_FATAL = 1
  1470. } ecc_error_type_e;
  1471. typedef enum {
  1472. ECC_DTCM_RAM = 0,
  1473. ECC_ITCM_RAM = 1,
  1474. ECC_DCACHE_DATA_RAM = 4,
  1475. ECC_DCACHE_TAG_RAM = 5,
  1476. ECC_ICACHE_DATA_RAM = 6,
  1477. ECC_ICACHE_TAG_RAM = 7
  1478. } ecc_ramid_e;
  1479. typedef struct {
  1480. uint32_t erraddr;
  1481. uint32_t index;
  1482. uint8_t way;
  1483. ecc_ramid_e ramid: 8;
  1484. ecc_error_type_e err_type: 8;
  1485. } ecc_error_info_t;
  1486. /**
  1487. \brief Enable ECC
  1488. \details Turns on ECC
  1489. */
  1490. __STATIC_INLINE void csi_ecc_enable (void)
  1491. {
  1492. __set_CCR2(__get_CCR2() | CCR2_ECC_Msk);
  1493. }
  1494. /**
  1495. \brief Disable ECC
  1496. \details Turns off ECC
  1497. */
  1498. __STATIC_INLINE void csi_ecc_disable (void)
  1499. {
  1500. __set_CCR2(__get_CCR2() & ~CCR2_ECC_Msk);
  1501. }
  1502. /**
  1503. \brief Enable ECC error fix function
  1504. \details Turns on ECC error fix function
  1505. */
  1506. __STATIC_INLINE void csi_ecc_enable_error_fix (void)
  1507. {
  1508. __set_CCR2(__get_CCR2() | CCR2_CRECC_Msk);
  1509. }
  1510. /**
  1511. \brief Disable ECC error fix function
  1512. \details Turns off ECC error fix function
  1513. */
  1514. __STATIC_INLINE void csi_ecc_disable_error_fix (void)
  1515. {
  1516. __set_CCR2(__get_CCR2() & ~CCR2_CRECC_Msk);
  1517. }
  1518. /**
  1519. \brief Inject ECC error
  1520. \details Inject ECC error
  1521. \param [in] type ECC error type.
  1522. \param [in] ramid ECC ram id.
  1523. */
  1524. __STATIC_INLINE void csi_ecc_inject_error(ecc_error_type_e type, ecc_ramid_e ramid)
  1525. {
  1526. ERRINJCR_Type errinjcr;
  1527. errinjcr.b.ERR_TYPE = type;
  1528. errinjcr.b.RAMID = (1U << ramid);
  1529. errinjcr.b.INJ_EN = 1U;
  1530. errinjcr.b._reserved0 = 0;
  1531. __set_ERRINJCR(errinjcr.w);
  1532. }
  1533. /**
  1534. \brief Get ECC error info
  1535. \details Inject ECC error info
  1536. \param [out] info ECC error info
  1537. */
  1538. __STATIC_INLINE void csi_ecc_get_error_info(ecc_error_info_t *info)
  1539. {
  1540. ERRLC_Type errlc;
  1541. if (info != NULL) {
  1542. errlc.w = __get_ERRLC();
  1543. info->erraddr = __get_ERRADDR();
  1544. info->index = errlc.b.Index;
  1545. info->way = errlc.b.Way;
  1546. info->ramid = 31 - __FF1(errlc.b.RAMID);
  1547. info->err_type = errlc.b.ERR_TYPE;
  1548. }
  1549. }
  1550. /*@} end of CSI_Core_ECCFunctions */
  1551. /* ################################## IRQ Functions ############################################ */
  1552. /**
  1553. \brief Save the Irq context
  1554. \details save the psr result before disable irq.
  1555. \param [in] irq_num External interrupt number. Value cannot be negative.
  1556. */
  1557. __STATIC_INLINE uint32_t csi_irq_save(void)
  1558. {
  1559. uint32_t result;
  1560. result = __get_PSR();
  1561. __disable_irq();
  1562. return(result);
  1563. }
  1564. /**
  1565. \brief Restore the Irq context
  1566. \details restore saved primask state.
  1567. \param [in] irq_state psr irq state.
  1568. */
  1569. __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
  1570. {
  1571. __set_PSR(irq_state);
  1572. }
  1573. /*@} end of IRQ Functions */
  1574. #ifdef __cplusplus
  1575. }
  1576. #endif
  1577. #endif /* __CORE_CK807_H_DEPENDANT */
  1578. #endif /* __CSI_GENERIC */