cmsis_gcc.h 59 KB

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  1. /**************************************************************************//**
  2. * @file cmsis_gcc.h
  3. * @brief CMSIS compiler GCC header file
  4. * @version V5.1.0
  5. * @date 20. December 2018
  6. ******************************************************************************/
  7. /*
  8. * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  9. *
  10. * SPDX-License-Identifier: Apache-2.0
  11. *
  12. * Licensed under the Apache License, Version 2.0 (the License); you may
  13. * not use this file except in compliance with the License.
  14. * You may obtain a copy of the License at
  15. *
  16. * www.apache.org/licenses/LICENSE-2.0
  17. *
  18. * Unless required by applicable law or agreed to in writing, software
  19. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21. * See the License for the specific language governing permissions and
  22. * limitations under the License.
  23. */
  24. #ifndef __CMSIS_GCC_H
  25. #define __CMSIS_GCC_H
  26. /* ignore some GCC warnings */
  27. #pragma GCC diagnostic push
  28. #pragma GCC diagnostic ignored "-Wsign-conversion"
  29. #pragma GCC diagnostic ignored "-Wconversion"
  30. #pragma GCC diagnostic ignored "-Wunused-parameter"
  31. /* Fallback for __has_builtin */
  32. #ifndef __has_builtin
  33. #define __has_builtin(x) (0)
  34. #endif
  35. /* CMSIS compiler specific defines */
  36. #ifndef __ASM
  37. #define __ASM __asm
  38. #endif
  39. #ifndef __INLINE
  40. #define __INLINE inline
  41. #endif
  42. #ifndef __STATIC_INLINE
  43. #define __STATIC_INLINE static inline
  44. #endif
  45. #ifndef __STATIC_FORCEINLINE
  46. #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
  47. #endif
  48. #ifndef __NO_RETURN
  49. #define __NO_RETURN __attribute__((__noreturn__))
  50. #endif
  51. #ifndef __USED
  52. #define __USED __attribute__((used))
  53. #endif
  54. #ifndef __WEAK
  55. #define __WEAK __attribute__((weak))
  56. #endif
  57. #ifndef __PACKED
  58. #define __PACKED __attribute__((packed, aligned(1)))
  59. #endif
  60. #ifndef __PACKED_STRUCT
  61. #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
  62. #endif
  63. #ifndef __PACKED_UNION
  64. #define __PACKED_UNION union __attribute__((packed, aligned(1)))
  65. #endif
  66. #ifndef __UNALIGNED_UINT32 /* deprecated */
  67. #pragma GCC diagnostic push
  68. #pragma GCC diagnostic ignored "-Wpacked"
  69. #pragma GCC diagnostic ignored "-Wattributes"
  70. struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  71. #pragma GCC diagnostic pop
  72. #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
  73. #endif
  74. #ifndef __UNALIGNED_UINT16_WRITE
  75. #pragma GCC diagnostic push
  76. #pragma GCC diagnostic ignored "-Wpacked"
  77. #pragma GCC diagnostic ignored "-Wattributes"
  78. __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  79. #pragma GCC diagnostic pop
  80. #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
  81. #endif
  82. #ifndef __UNALIGNED_UINT16_READ
  83. #pragma GCC diagnostic push
  84. #pragma GCC diagnostic ignored "-Wpacked"
  85. #pragma GCC diagnostic ignored "-Wattributes"
  86. __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  87. #pragma GCC diagnostic pop
  88. #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
  89. #endif
  90. #ifndef __UNALIGNED_UINT32_WRITE
  91. #pragma GCC diagnostic push
  92. #pragma GCC diagnostic ignored "-Wpacked"
  93. #pragma GCC diagnostic ignored "-Wattributes"
  94. __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  95. #pragma GCC diagnostic pop
  96. #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
  97. #endif
  98. #ifndef __UNALIGNED_UINT32_READ
  99. #pragma GCC diagnostic push
  100. #pragma GCC diagnostic ignored "-Wpacked"
  101. #pragma GCC diagnostic ignored "-Wattributes"
  102. __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
  103. #pragma GCC diagnostic pop
  104. #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
  105. #endif
  106. #ifndef __ALIGNED
  107. #define __ALIGNED(x) __attribute__((aligned(x)))
  108. #endif
  109. #ifndef __RESTRICT
  110. #define __RESTRICT __restrict
  111. #endif
  112. /* ########################### Core Function Access ########################### */
  113. /** \ingroup CMSIS_Core_FunctionInterface
  114. \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  115. @{
  116. */
  117. /**
  118. \brief Enable IRQ Interrupts
  119. \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
  120. Can only be executed in Privileged modes.
  121. */
  122. __STATIC_FORCEINLINE void __enable_irq(void)
  123. {
  124. __ASM volatile ("cpsie i" : : : "memory");
  125. }
  126. /**
  127. \brief Disable IRQ Interrupts
  128. \details Disables IRQ interrupts by setting the I-bit in the CPSR.
  129. Can only be executed in Privileged modes.
  130. */
  131. __STATIC_FORCEINLINE void __disable_irq(void)
  132. {
  133. __ASM volatile ("cpsid i" : : : "memory");
  134. }
  135. /**
  136. \brief Get Control Register
  137. \details Returns the content of the Control Register.
  138. \return Control Register value
  139. */
  140. __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
  141. {
  142. uint32_t result;
  143. __ASM volatile ("MRS %0, control" : "=r" (result) );
  144. return(result);
  145. }
  146. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  147. /**
  148. \brief Get Control Register (non-secure)
  149. \details Returns the content of the non-secure Control Register when in secure mode.
  150. \return non-secure Control Register value
  151. */
  152. __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
  153. {
  154. uint32_t result;
  155. __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
  156. return(result);
  157. }
  158. #endif
  159. /**
  160. \brief Set Control Register
  161. \details Writes the given value to the Control Register.
  162. \param [in] control Control Register value to set
  163. */
  164. __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
  165. {
  166. __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
  167. }
  168. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  169. /**
  170. \brief Set Control Register (non-secure)
  171. \details Writes the given value to the non-secure Control Register when in secure state.
  172. \param [in] control Control Register value to set
  173. */
  174. __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
  175. {
  176. __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
  177. }
  178. #endif
  179. /**
  180. \brief Get IPSR Register
  181. \details Returns the content of the IPSR Register.
  182. \return IPSR Register value
  183. */
  184. __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
  185. {
  186. uint32_t result;
  187. __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
  188. return(result);
  189. }
  190. /**
  191. \brief Get APSR Register
  192. \details Returns the content of the APSR Register.
  193. \return APSR Register value
  194. */
  195. __STATIC_FORCEINLINE uint32_t __get_APSR(void)
  196. {
  197. uint32_t result;
  198. __ASM volatile ("MRS %0, apsr" : "=r" (result) );
  199. return(result);
  200. }
  201. /**
  202. \brief Get xPSR Register
  203. \details Returns the content of the xPSR Register.
  204. \return xPSR Register value
  205. */
  206. __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
  207. {
  208. uint32_t result;
  209. __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
  210. return(result);
  211. }
  212. /**
  213. \brief Get Process Stack Pointer
  214. \details Returns the current value of the Process Stack Pointer (PSP).
  215. \return PSP Register value
  216. */
  217. __STATIC_FORCEINLINE uint32_t __get_PSP(void)
  218. {
  219. uint32_t result;
  220. __ASM volatile ("MRS %0, psp" : "=r" (result) );
  221. return(result);
  222. }
  223. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  224. /**
  225. \brief Get Process Stack Pointer (non-secure)
  226. \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
  227. \return PSP Register value
  228. */
  229. __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
  230. {
  231. uint32_t result;
  232. __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
  233. return(result);
  234. }
  235. #endif
  236. /**
  237. \brief Set Process Stack Pointer
  238. \details Assigns the given value to the Process Stack Pointer (PSP).
  239. \param [in] topOfProcStack Process Stack Pointer value to set
  240. */
  241. __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
  242. {
  243. __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
  244. }
  245. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  246. /**
  247. \brief Set Process Stack Pointer (non-secure)
  248. \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
  249. \param [in] topOfProcStack Process Stack Pointer value to set
  250. */
  251. __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
  252. {
  253. __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
  254. }
  255. #endif
  256. /**
  257. \brief Get Main Stack Pointer
  258. \details Returns the current value of the Main Stack Pointer (MSP).
  259. \return MSP Register value
  260. */
  261. __STATIC_FORCEINLINE uint32_t __get_MSP(void)
  262. {
  263. uint32_t result;
  264. __ASM volatile ("MRS %0, msp" : "=r" (result) );
  265. return(result);
  266. }
  267. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  268. /**
  269. \brief Get Main Stack Pointer (non-secure)
  270. \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
  271. \return MSP Register value
  272. */
  273. __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
  274. {
  275. uint32_t result;
  276. __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
  277. return(result);
  278. }
  279. #endif
  280. /**
  281. \brief Set Main Stack Pointer
  282. \details Assigns the given value to the Main Stack Pointer (MSP).
  283. \param [in] topOfMainStack Main Stack Pointer value to set
  284. */
  285. __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
  286. {
  287. __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
  288. }
  289. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  290. /**
  291. \brief Set Main Stack Pointer (non-secure)
  292. \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
  293. \param [in] topOfMainStack Main Stack Pointer value to set
  294. */
  295. __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
  296. {
  297. __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
  298. }
  299. #endif
  300. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  301. /**
  302. \brief Get Stack Pointer (non-secure)
  303. \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
  304. \return SP Register value
  305. */
  306. __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
  307. {
  308. uint32_t result;
  309. __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
  310. return(result);
  311. }
  312. /**
  313. \brief Set Stack Pointer (non-secure)
  314. \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
  315. \param [in] topOfStack Stack Pointer value to set
  316. */
  317. __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
  318. {
  319. __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
  320. }
  321. #endif
  322. /**
  323. \brief Get Priority Mask
  324. \details Returns the current state of the priority mask bit from the Priority Mask Register.
  325. \return Priority Mask value
  326. */
  327. __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
  328. {
  329. uint32_t result;
  330. __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
  331. return(result);
  332. }
  333. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  334. /**
  335. \brief Get Priority Mask (non-secure)
  336. \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
  337. \return Priority Mask value
  338. */
  339. __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
  340. {
  341. uint32_t result;
  342. __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
  343. return(result);
  344. }
  345. #endif
  346. /**
  347. \brief Set Priority Mask
  348. \details Assigns the given value to the Priority Mask Register.
  349. \param [in] priMask Priority Mask
  350. */
  351. __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
  352. {
  353. __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
  354. }
  355. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  356. /**
  357. \brief Set Priority Mask (non-secure)
  358. \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
  359. \param [in] priMask Priority Mask
  360. */
  361. __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
  362. {
  363. __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
  364. }
  365. #endif
  366. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  367. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  368. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  369. /**
  370. \brief Enable FIQ
  371. \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
  372. Can only be executed in Privileged modes.
  373. */
  374. __STATIC_FORCEINLINE void __enable_fault_irq(void)
  375. {
  376. __ASM volatile ("cpsie f" : : : "memory");
  377. }
  378. /**
  379. \brief Disable FIQ
  380. \details Disables FIQ interrupts by setting the F-bit in the CPSR.
  381. Can only be executed in Privileged modes.
  382. */
  383. __STATIC_FORCEINLINE void __disable_fault_irq(void)
  384. {
  385. __ASM volatile ("cpsid f" : : : "memory");
  386. }
  387. /**
  388. \brief Get Base Priority
  389. \details Returns the current value of the Base Priority register.
  390. \return Base Priority register value
  391. */
  392. __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
  393. {
  394. uint32_t result;
  395. __ASM volatile ("MRS %0, basepri" : "=r" (result) );
  396. return(result);
  397. }
  398. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  399. /**
  400. \brief Get Base Priority (non-secure)
  401. \details Returns the current value of the non-secure Base Priority register when in secure state.
  402. \return Base Priority register value
  403. */
  404. __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
  405. {
  406. uint32_t result;
  407. __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
  408. return(result);
  409. }
  410. #endif
  411. /**
  412. \brief Set Base Priority
  413. \details Assigns the given value to the Base Priority register.
  414. \param [in] basePri Base Priority value to set
  415. */
  416. __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
  417. {
  418. __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
  419. }
  420. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  421. /**
  422. \brief Set Base Priority (non-secure)
  423. \details Assigns the given value to the non-secure Base Priority register when in secure state.
  424. \param [in] basePri Base Priority value to set
  425. */
  426. __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
  427. {
  428. __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
  429. }
  430. #endif
  431. /**
  432. \brief Set Base Priority with condition
  433. \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
  434. or the new value increases the BASEPRI priority level.
  435. \param [in] basePri Base Priority value to set
  436. */
  437. __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
  438. {
  439. __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
  440. }
  441. /**
  442. \brief Get Fault Mask
  443. \details Returns the current value of the Fault Mask register.
  444. \return Fault Mask register value
  445. */
  446. __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
  447. {
  448. uint32_t result;
  449. __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
  450. return(result);
  451. }
  452. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  453. /**
  454. \brief Get Fault Mask (non-secure)
  455. \details Returns the current value of the non-secure Fault Mask register when in secure state.
  456. \return Fault Mask register value
  457. */
  458. __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
  459. {
  460. uint32_t result;
  461. __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
  462. return(result);
  463. }
  464. #endif
  465. /**
  466. \brief Set Fault Mask
  467. \details Assigns the given value to the Fault Mask register.
  468. \param [in] faultMask Fault Mask value to set
  469. */
  470. __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
  471. {
  472. __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
  473. }
  474. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  475. /**
  476. \brief Set Fault Mask (non-secure)
  477. \details Assigns the given value to the non-secure Fault Mask register when in secure state.
  478. \param [in] faultMask Fault Mask value to set
  479. */
  480. __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
  481. {
  482. __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
  483. }
  484. #endif
  485. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  486. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  487. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
  488. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  489. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  490. /**
  491. \brief Get Process Stack Pointer Limit
  492. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  493. Stack Pointer Limit register hence zero is returned always in non-secure
  494. mode.
  495. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
  496. \return PSPLIM Register value
  497. */
  498. __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
  499. {
  500. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  501. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  502. // without main extensions, the non-secure PSPLIM is RAZ/WI
  503. return 0U;
  504. #else
  505. uint32_t result;
  506. __ASM volatile ("MRS %0, psplim" : "=r" (result) );
  507. return result;
  508. #endif
  509. }
  510. #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
  511. /**
  512. \brief Get Process Stack Pointer Limit (non-secure)
  513. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  514. Stack Pointer Limit register hence zero is returned always.
  515. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
  516. \return PSPLIM Register value
  517. */
  518. __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
  519. {
  520. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
  521. // without main extensions, the non-secure PSPLIM is RAZ/WI
  522. return 0U;
  523. #else
  524. uint32_t result;
  525. __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
  526. return result;
  527. #endif
  528. }
  529. #endif
  530. /**
  531. \brief Set Process Stack Pointer Limit
  532. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  533. Stack Pointer Limit register hence the write is silently ignored in non-secure
  534. mode.
  535. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
  536. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
  537. */
  538. __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
  539. {
  540. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  541. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  542. // without main extensions, the non-secure PSPLIM is RAZ/WI
  543. (void)ProcStackPtrLimit;
  544. #else
  545. __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
  546. #endif
  547. }
  548. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  549. /**
  550. \brief Set Process Stack Pointer (non-secure)
  551. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  552. Stack Pointer Limit register hence the write is silently ignored.
  553. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
  554. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
  555. */
  556. __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
  557. {
  558. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
  559. // without main extensions, the non-secure PSPLIM is RAZ/WI
  560. (void)ProcStackPtrLimit;
  561. #else
  562. __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
  563. #endif
  564. }
  565. #endif
  566. /**
  567. \brief Get Main Stack Pointer Limit
  568. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  569. Stack Pointer Limit register hence zero is returned always in non-secure
  570. mode.
  571. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
  572. \return MSPLIM Register value
  573. */
  574. __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
  575. {
  576. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  577. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  578. // without main extensions, the non-secure MSPLIM is RAZ/WI
  579. return 0U;
  580. #else
  581. uint32_t result;
  582. __ASM volatile ("MRS %0, msplim" : "=r" (result) );
  583. return result;
  584. #endif
  585. }
  586. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  587. /**
  588. \brief Get Main Stack Pointer Limit (non-secure)
  589. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  590. Stack Pointer Limit register hence zero is returned always.
  591. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
  592. \return MSPLIM Register value
  593. */
  594. __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
  595. {
  596. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
  597. // without main extensions, the non-secure MSPLIM is RAZ/WI
  598. return 0U;
  599. #else
  600. uint32_t result;
  601. __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
  602. return result;
  603. #endif
  604. }
  605. #endif
  606. /**
  607. \brief Set Main Stack Pointer Limit
  608. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  609. Stack Pointer Limit register hence the write is silently ignored in non-secure
  610. mode.
  611. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
  612. \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
  613. */
  614. __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
  615. {
  616. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  617. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  618. // without main extensions, the non-secure MSPLIM is RAZ/WI
  619. (void)MainStackPtrLimit;
  620. #else
  621. __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
  622. #endif
  623. }
  624. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  625. /**
  626. \brief Set Main Stack Pointer Limit (non-secure)
  627. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  628. Stack Pointer Limit register hence the write is silently ignored.
  629. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
  630. \param [in] MainStackPtrLimit Main Stack Pointer value to set
  631. */
  632. __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
  633. {
  634. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
  635. // without main extensions, the non-secure MSPLIM is RAZ/WI
  636. (void)MainStackPtrLimit;
  637. #else
  638. __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
  639. #endif
  640. }
  641. #endif
  642. #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  643. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
  644. /**
  645. \brief Get FPSCR
  646. \details Returns the current value of the Floating Point Status/Control register.
  647. \return Floating Point Status/Control register value
  648. */
  649. __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
  650. {
  651. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  652. (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
  653. #if __has_builtin(__builtin_arm_get_fpscr)
  654. // Re-enable using built-in when GCC has been fixed
  655. // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
  656. /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
  657. return __builtin_arm_get_fpscr();
  658. #else
  659. uint32_t result;
  660. __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
  661. return(result);
  662. #endif
  663. #else
  664. return(0U);
  665. #endif
  666. }
  667. /**
  668. \brief Set FPSCR
  669. \details Assigns the given value to the Floating Point Status/Control register.
  670. \param [in] fpscr Floating Point Status/Control value to set
  671. */
  672. __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
  673. {
  674. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  675. (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
  676. #if __has_builtin(__builtin_arm_set_fpscr)
  677. // Re-enable using built-in when GCC has been fixed
  678. // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
  679. /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
  680. __builtin_arm_set_fpscr(fpscr);
  681. #else
  682. __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
  683. #endif
  684. #else
  685. (void)fpscr;
  686. #endif
  687. }
  688. /*@} end of CMSIS_Core_RegAccFunctions */
  689. /* ########################## Core Instruction Access ######################### */
  690. /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  691. Access to dedicated instructions
  692. @{
  693. */
  694. /* Define macros for porting to both thumb1 and thumb2.
  695. * For thumb1, use low register (r0-r7), specified by constraint "l"
  696. * Otherwise, use general registers, specified by constraint "r" */
  697. #if defined (__thumb__) && !defined (__thumb2__)
  698. #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
  699. #define __CMSIS_GCC_RW_REG(r) "+l" (r)
  700. #define __CMSIS_GCC_USE_REG(r) "l" (r)
  701. #else
  702. #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
  703. #define __CMSIS_GCC_RW_REG(r) "+r" (r)
  704. #define __CMSIS_GCC_USE_REG(r) "r" (r)
  705. #endif
  706. /**
  707. \brief No Operation
  708. \details No Operation does nothing. This instruction can be used for code alignment purposes.
  709. */
  710. #define __NOP() __ASM volatile ("nop")
  711. /**
  712. \brief Wait For Interrupt
  713. \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
  714. */
  715. #define __WFI() __ASM volatile ("wfi")
  716. /**
  717. \brief Wait For Event
  718. \details Wait For Event is a hint instruction that permits the processor to enter
  719. a low-power state until one of a number of events occurs.
  720. */
  721. #define __WFE() __ASM volatile ("wfe")
  722. /**
  723. \brief Send Event
  724. \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  725. */
  726. #define __SEV() __ASM volatile ("sev")
  727. /**
  728. \brief Instruction Synchronization Barrier
  729. \details Instruction Synchronization Barrier flushes the pipeline in the processor,
  730. so that all instructions following the ISB are fetched from cache or memory,
  731. after the instruction has been completed.
  732. */
  733. __STATIC_FORCEINLINE void __ISB(void)
  734. {
  735. __ASM volatile ("isb 0xF":::"memory");
  736. }
  737. /**
  738. \brief Data Synchronization Barrier
  739. \details Acts as a special kind of Data Memory Barrier.
  740. It completes when all explicit memory accesses before this instruction complete.
  741. */
  742. __STATIC_FORCEINLINE void __DSB(void)
  743. {
  744. __ASM volatile ("dsb 0xF":::"memory");
  745. }
  746. /**
  747. \brief Data Memory Barrier
  748. \details Ensures the apparent order of the explicit memory operations before
  749. and after the instruction, without ensuring their completion.
  750. */
  751. __STATIC_FORCEINLINE void __DMB(void)
  752. {
  753. __ASM volatile ("dmb 0xF":::"memory");
  754. }
  755. /**
  756. \brief Reverse byte order (32 bit)
  757. \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
  758. \param [in] value Value to reverse
  759. \return Reversed value
  760. */
  761. __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
  762. {
  763. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
  764. return __builtin_bswap32(value);
  765. #else
  766. uint32_t result;
  767. __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  768. return result;
  769. #endif
  770. }
  771. /**
  772. \brief Reverse byte order (16 bit)
  773. \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
  774. \param [in] value Value to reverse
  775. \return Reversed value
  776. */
  777. __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
  778. {
  779. uint32_t result;
  780. __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  781. return result;
  782. }
  783. /**
  784. \brief Reverse byte order (16 bit)
  785. \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
  786. \param [in] value Value to reverse
  787. \return Reversed value
  788. */
  789. __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
  790. {
  791. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  792. return (int16_t)__builtin_bswap16(value);
  793. #else
  794. int16_t result;
  795. __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  796. return result;
  797. #endif
  798. }
  799. /**
  800. \brief Rotate Right in unsigned value (32 bit)
  801. \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  802. \param [in] op1 Value to rotate
  803. \param [in] op2 Number of Bits to rotate
  804. \return Rotated value
  805. */
  806. __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
  807. {
  808. op2 %= 32U;
  809. if (op2 == 0U)
  810. {
  811. return op1;
  812. }
  813. return (op1 >> op2) | (op1 << (32U - op2));
  814. }
  815. /**
  816. \brief Breakpoint
  817. \details Causes the processor to enter Debug state.
  818. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  819. \param [in] value is ignored by the processor.
  820. If required, a debugger can use it to store additional information about the breakpoint.
  821. */
  822. #define __BKPT(value) __ASM volatile ("bkpt "#value)
  823. /**
  824. \brief Reverse bit order of value
  825. \details Reverses the bit order of the given value.
  826. \param [in] value Value to reverse
  827. \return Reversed value
  828. */
  829. __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
  830. {
  831. uint32_t result;
  832. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  833. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  834. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  835. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  836. #else
  837. uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
  838. result = value; /* r will be reversed bits of v; first get LSB of v */
  839. for (value >>= 1U; value != 0U; value >>= 1U)
  840. {
  841. result <<= 1U;
  842. result |= value & 1U;
  843. s--;
  844. }
  845. result <<= s; /* shift when v's highest bits are zero */
  846. #endif
  847. return result;
  848. }
  849. /**
  850. \brief Count leading zeros
  851. \details Counts the number of leading zeros of a data value.
  852. \param [in] value Value to count the leading zeros
  853. \return number of leading zeros in value
  854. */
  855. __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
  856. {
  857. /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
  858. __builtin_clz(0) is undefined behaviour, so handle this case specially.
  859. This guarantees ARM-compatible results if happening to compile on a non-ARM
  860. target, and ensures the compiler doesn't decide to activate any
  861. optimisations using the logic "value was passed to __builtin_clz, so it
  862. is non-zero".
  863. ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
  864. single CLZ instruction.
  865. */
  866. if (value == 0U)
  867. {
  868. return 32U;
  869. }
  870. return __builtin_clz(value);
  871. }
  872. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  873. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  874. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  875. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  876. /**
  877. \brief LDR Exclusive (8 bit)
  878. \details Executes a exclusive LDR instruction for 8 bit value.
  879. \param [in] ptr Pointer to data
  880. \return value of type uint8_t at (*ptr)
  881. */
  882. __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
  883. {
  884. uint32_t result;
  885. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  886. __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
  887. #else
  888. /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
  889. accepted by assembler. So has to use following less efficient pattern.
  890. */
  891. __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
  892. #endif
  893. return ((uint8_t) result); /* Add explicit type cast here */
  894. }
  895. /**
  896. \brief LDR Exclusive (16 bit)
  897. \details Executes a exclusive LDR instruction for 16 bit values.
  898. \param [in] ptr Pointer to data
  899. \return value of type uint16_t at (*ptr)
  900. */
  901. __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
  902. {
  903. uint32_t result;
  904. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  905. __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
  906. #else
  907. /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
  908. accepted by assembler. So has to use following less efficient pattern.
  909. */
  910. __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
  911. #endif
  912. return ((uint16_t) result); /* Add explicit type cast here */
  913. }
  914. /**
  915. \brief LDR Exclusive (32 bit)
  916. \details Executes a exclusive LDR instruction for 32 bit values.
  917. \param [in] ptr Pointer to data
  918. \return value of type uint32_t at (*ptr)
  919. */
  920. __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
  921. {
  922. uint32_t result;
  923. __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
  924. return(result);
  925. }
  926. /**
  927. \brief STR Exclusive (8 bit)
  928. \details Executes a exclusive STR instruction for 8 bit values.
  929. \param [in] value Value to store
  930. \param [in] ptr Pointer to location
  931. \return 0 Function succeeded
  932. \return 1 Function failed
  933. */
  934. __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
  935. {
  936. uint32_t result;
  937. __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
  938. return(result);
  939. }
  940. /**
  941. \brief STR Exclusive (16 bit)
  942. \details Executes a exclusive STR instruction for 16 bit values.
  943. \param [in] value Value to store
  944. \param [in] ptr Pointer to location
  945. \return 0 Function succeeded
  946. \return 1 Function failed
  947. */
  948. __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
  949. {
  950. uint32_t result;
  951. __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
  952. return(result);
  953. }
  954. /**
  955. \brief STR Exclusive (32 bit)
  956. \details Executes a exclusive STR instruction for 32 bit values.
  957. \param [in] value Value to store
  958. \param [in] ptr Pointer to location
  959. \return 0 Function succeeded
  960. \return 1 Function failed
  961. */
  962. __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
  963. {
  964. uint32_t result;
  965. __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
  966. return(result);
  967. }
  968. /**
  969. \brief Remove the exclusive lock
  970. \details Removes the exclusive lock which is created by LDREX.
  971. */
  972. __STATIC_FORCEINLINE void __CLREX(void)
  973. {
  974. __ASM volatile ("clrex" ::: "memory");
  975. }
  976. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  977. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  978. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  979. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
  980. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  981. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  982. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  983. /**
  984. \brief Signed Saturate
  985. \details Saturates a signed value.
  986. \param [in] ARG1 Value to be saturated
  987. \param [in] ARG2 Bit position to saturate to (1..32)
  988. \return Saturated value
  989. */
  990. #define __SSAT(ARG1,ARG2) \
  991. __extension__ \
  992. ({ \
  993. int32_t __RES, __ARG1 = (ARG1); \
  994. __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  995. __RES; \
  996. })
  997. /**
  998. \brief Unsigned Saturate
  999. \details Saturates an unsigned value.
  1000. \param [in] ARG1 Value to be saturated
  1001. \param [in] ARG2 Bit position to saturate to (0..31)
  1002. \return Saturated value
  1003. */
  1004. #define __USAT(ARG1,ARG2) \
  1005. __extension__ \
  1006. ({ \
  1007. uint32_t __RES, __ARG1 = (ARG1); \
  1008. __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  1009. __RES; \
  1010. })
  1011. /**
  1012. \brief Rotate Right with Extend (32 bit)
  1013. \details Moves each bit of a bitstring right by one bit.
  1014. The carry input is shifted in at the left end of the bitstring.
  1015. \param [in] value Value to rotate
  1016. \return Rotated value
  1017. */
  1018. __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
  1019. {
  1020. uint32_t result;
  1021. __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  1022. return(result);
  1023. }
  1024. /**
  1025. \brief LDRT Unprivileged (8 bit)
  1026. \details Executes a Unprivileged LDRT instruction for 8 bit value.
  1027. \param [in] ptr Pointer to data
  1028. \return value of type uint8_t at (*ptr)
  1029. */
  1030. __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
  1031. {
  1032. uint32_t result;
  1033. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  1034. __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
  1035. #else
  1036. /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
  1037. accepted by assembler. So has to use following less efficient pattern.
  1038. */
  1039. __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
  1040. #endif
  1041. return ((uint8_t) result); /* Add explicit type cast here */
  1042. }
  1043. /**
  1044. \brief LDRT Unprivileged (16 bit)
  1045. \details Executes a Unprivileged LDRT instruction for 16 bit values.
  1046. \param [in] ptr Pointer to data
  1047. \return value of type uint16_t at (*ptr)
  1048. */
  1049. __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
  1050. {
  1051. uint32_t result;
  1052. #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  1053. __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
  1054. #else
  1055. /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
  1056. accepted by assembler. So has to use following less efficient pattern.
  1057. */
  1058. __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
  1059. #endif
  1060. return ((uint16_t) result); /* Add explicit type cast here */
  1061. }
  1062. /**
  1063. \brief LDRT Unprivileged (32 bit)
  1064. \details Executes a Unprivileged LDRT instruction for 32 bit values.
  1065. \param [in] ptr Pointer to data
  1066. \return value of type uint32_t at (*ptr)
  1067. */
  1068. __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
  1069. {
  1070. uint32_t result;
  1071. __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
  1072. return(result);
  1073. }
  1074. /**
  1075. \brief STRT Unprivileged (8 bit)
  1076. \details Executes a Unprivileged STRT instruction for 8 bit values.
  1077. \param [in] value Value to store
  1078. \param [in] ptr Pointer to location
  1079. */
  1080. __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
  1081. {
  1082. __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  1083. }
  1084. /**
  1085. \brief STRT Unprivileged (16 bit)
  1086. \details Executes a Unprivileged STRT instruction for 16 bit values.
  1087. \param [in] value Value to store
  1088. \param [in] ptr Pointer to location
  1089. */
  1090. __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
  1091. {
  1092. __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  1093. }
  1094. /**
  1095. \brief STRT Unprivileged (32 bit)
  1096. \details Executes a Unprivileged STRT instruction for 32 bit values.
  1097. \param [in] value Value to store
  1098. \param [in] ptr Pointer to location
  1099. */
  1100. __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
  1101. {
  1102. __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
  1103. }
  1104. #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  1105. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  1106. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
  1107. /**
  1108. \brief Signed Saturate
  1109. \details Saturates a signed value.
  1110. \param [in] value Value to be saturated
  1111. \param [in] sat Bit position to saturate to (1..32)
  1112. \return Saturated value
  1113. */
  1114. __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
  1115. {
  1116. if ((sat >= 1U) && (sat <= 32U))
  1117. {
  1118. const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
  1119. const int32_t min = -1 - max ;
  1120. if (val > max)
  1121. {
  1122. return max;
  1123. }
  1124. else if (val < min)
  1125. {
  1126. return min;
  1127. }
  1128. }
  1129. return val;
  1130. }
  1131. /**
  1132. \brief Unsigned Saturate
  1133. \details Saturates an unsigned value.
  1134. \param [in] value Value to be saturated
  1135. \param [in] sat Bit position to saturate to (0..31)
  1136. \return Saturated value
  1137. */
  1138. __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
  1139. {
  1140. if (sat <= 31U)
  1141. {
  1142. const uint32_t max = ((1U << sat) - 1U);
  1143. if (val > (int32_t)max)
  1144. {
  1145. return max;
  1146. }
  1147. else if (val < 0)
  1148. {
  1149. return 0U;
  1150. }
  1151. }
  1152. return (uint32_t)val;
  1153. }
  1154. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  1155. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  1156. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
  1157. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  1158. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  1159. /**
  1160. \brief Load-Acquire (8 bit)
  1161. \details Executes a LDAB instruction for 8 bit value.
  1162. \param [in] ptr Pointer to data
  1163. \return value of type uint8_t at (*ptr)
  1164. */
  1165. __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
  1166. {
  1167. uint32_t result;
  1168. __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
  1169. return ((uint8_t) result);
  1170. }
  1171. /**
  1172. \brief Load-Acquire (16 bit)
  1173. \details Executes a LDAH instruction for 16 bit values.
  1174. \param [in] ptr Pointer to data
  1175. \return value of type uint16_t at (*ptr)
  1176. */
  1177. __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
  1178. {
  1179. uint32_t result;
  1180. __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
  1181. return ((uint16_t) result);
  1182. }
  1183. /**
  1184. \brief Load-Acquire (32 bit)
  1185. \details Executes a LDA instruction for 32 bit values.
  1186. \param [in] ptr Pointer to data
  1187. \return value of type uint32_t at (*ptr)
  1188. */
  1189. __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
  1190. {
  1191. uint32_t result;
  1192. __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
  1193. return(result);
  1194. }
  1195. /**
  1196. \brief Store-Release (8 bit)
  1197. \details Executes a STLB instruction for 8 bit values.
  1198. \param [in] value Value to store
  1199. \param [in] ptr Pointer to location
  1200. */
  1201. __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
  1202. {
  1203. __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  1204. }
  1205. /**
  1206. \brief Store-Release (16 bit)
  1207. \details Executes a STLH instruction for 16 bit values.
  1208. \param [in] value Value to store
  1209. \param [in] ptr Pointer to location
  1210. */
  1211. __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
  1212. {
  1213. __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  1214. }
  1215. /**
  1216. \brief Store-Release (32 bit)
  1217. \details Executes a STL instruction for 32 bit values.
  1218. \param [in] value Value to store
  1219. \param [in] ptr Pointer to location
  1220. */
  1221. __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
  1222. {
  1223. __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  1224. }
  1225. /**
  1226. \brief Load-Acquire Exclusive (8 bit)
  1227. \details Executes a LDAB exclusive instruction for 8 bit value.
  1228. \param [in] ptr Pointer to data
  1229. \return value of type uint8_t at (*ptr)
  1230. */
  1231. __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
  1232. {
  1233. uint32_t result;
  1234. __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
  1235. return ((uint8_t) result);
  1236. }
  1237. /**
  1238. \brief Load-Acquire Exclusive (16 bit)
  1239. \details Executes a LDAH exclusive instruction for 16 bit values.
  1240. \param [in] ptr Pointer to data
  1241. \return value of type uint16_t at (*ptr)
  1242. */
  1243. __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
  1244. {
  1245. uint32_t result;
  1246. __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
  1247. return ((uint16_t) result);
  1248. }
  1249. /**
  1250. \brief Load-Acquire Exclusive (32 bit)
  1251. \details Executes a LDA exclusive instruction for 32 bit values.
  1252. \param [in] ptr Pointer to data
  1253. \return value of type uint32_t at (*ptr)
  1254. */
  1255. __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
  1256. {
  1257. uint32_t result;
  1258. __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
  1259. return(result);
  1260. }
  1261. /**
  1262. \brief Store-Release Exclusive (8 bit)
  1263. \details Executes a STLB exclusive instruction for 8 bit values.
  1264. \param [in] value Value to store
  1265. \param [in] ptr Pointer to location
  1266. \return 0 Function succeeded
  1267. \return 1 Function failed
  1268. */
  1269. __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
  1270. {
  1271. uint32_t result;
  1272. __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
  1273. return(result);
  1274. }
  1275. /**
  1276. \brief Store-Release Exclusive (16 bit)
  1277. \details Executes a STLH exclusive instruction for 16 bit values.
  1278. \param [in] value Value to store
  1279. \param [in] ptr Pointer to location
  1280. \return 0 Function succeeded
  1281. \return 1 Function failed
  1282. */
  1283. __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
  1284. {
  1285. uint32_t result;
  1286. __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
  1287. return(result);
  1288. }
  1289. /**
  1290. \brief Store-Release Exclusive (32 bit)
  1291. \details Executes a STL exclusive instruction for 32 bit values.
  1292. \param [in] value Value to store
  1293. \param [in] ptr Pointer to location
  1294. \return 0 Function succeeded
  1295. \return 1 Function failed
  1296. */
  1297. __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
  1298. {
  1299. uint32_t result;
  1300. __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
  1301. return(result);
  1302. }
  1303. #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  1304. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
  1305. /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
  1306. /* ################### Compiler specific Intrinsics ########################### */
  1307. /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  1308. Access to dedicated SIMD instructions
  1309. @{
  1310. */
  1311. #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
  1312. __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
  1313. {
  1314. uint32_t result;
  1315. __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1316. return(result);
  1317. }
  1318. __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
  1319. {
  1320. uint32_t result;
  1321. __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1322. return(result);
  1323. }
  1324. __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
  1325. {
  1326. uint32_t result;
  1327. __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1328. return(result);
  1329. }
  1330. __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
  1331. {
  1332. uint32_t result;
  1333. __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1334. return(result);
  1335. }
  1336. __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
  1337. {
  1338. uint32_t result;
  1339. __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1340. return(result);
  1341. }
  1342. __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
  1343. {
  1344. uint32_t result;
  1345. __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1346. return(result);
  1347. }
  1348. __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
  1349. {
  1350. uint32_t result;
  1351. __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1352. return(result);
  1353. }
  1354. __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
  1355. {
  1356. uint32_t result;
  1357. __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1358. return(result);
  1359. }
  1360. __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
  1361. {
  1362. uint32_t result;
  1363. __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1364. return(result);
  1365. }
  1366. __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
  1367. {
  1368. uint32_t result;
  1369. __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1370. return(result);
  1371. }
  1372. __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
  1373. {
  1374. uint32_t result;
  1375. __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1376. return(result);
  1377. }
  1378. __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
  1379. {
  1380. uint32_t result;
  1381. __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1382. return(result);
  1383. }
  1384. __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
  1385. {
  1386. uint32_t result;
  1387. __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1388. return(result);
  1389. }
  1390. __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
  1391. {
  1392. uint32_t result;
  1393. __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1394. return(result);
  1395. }
  1396. __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
  1397. {
  1398. uint32_t result;
  1399. __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1400. return(result);
  1401. }
  1402. __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
  1403. {
  1404. uint32_t result;
  1405. __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1406. return(result);
  1407. }
  1408. __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
  1409. {
  1410. uint32_t result;
  1411. __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1412. return(result);
  1413. }
  1414. __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
  1415. {
  1416. uint32_t result;
  1417. __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1418. return(result);
  1419. }
  1420. __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
  1421. {
  1422. uint32_t result;
  1423. __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1424. return(result);
  1425. }
  1426. __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
  1427. {
  1428. uint32_t result;
  1429. __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1430. return(result);
  1431. }
  1432. __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
  1433. {
  1434. uint32_t result;
  1435. __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1436. return(result);
  1437. }
  1438. __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
  1439. {
  1440. uint32_t result;
  1441. __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1442. return(result);
  1443. }
  1444. __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
  1445. {
  1446. uint32_t result;
  1447. __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1448. return(result);
  1449. }
  1450. __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
  1451. {
  1452. uint32_t result;
  1453. __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1454. return(result);
  1455. }
  1456. __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
  1457. {
  1458. uint32_t result;
  1459. __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1460. return(result);
  1461. }
  1462. __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
  1463. {
  1464. uint32_t result;
  1465. __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1466. return(result);
  1467. }
  1468. __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
  1469. {
  1470. uint32_t result;
  1471. __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1472. return(result);
  1473. }
  1474. __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
  1475. {
  1476. uint32_t result;
  1477. __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1478. return(result);
  1479. }
  1480. __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
  1481. {
  1482. uint32_t result;
  1483. __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1484. return(result);
  1485. }
  1486. __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
  1487. {
  1488. uint32_t result;
  1489. __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1490. return(result);
  1491. }
  1492. __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
  1493. {
  1494. uint32_t result;
  1495. __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1496. return(result);
  1497. }
  1498. __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
  1499. {
  1500. uint32_t result;
  1501. __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1502. return(result);
  1503. }
  1504. __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
  1505. {
  1506. uint32_t result;
  1507. __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1508. return(result);
  1509. }
  1510. __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
  1511. {
  1512. uint32_t result;
  1513. __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1514. return(result);
  1515. }
  1516. __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
  1517. {
  1518. uint32_t result;
  1519. __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1520. return(result);
  1521. }
  1522. __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
  1523. {
  1524. uint32_t result;
  1525. __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1526. return(result);
  1527. }
  1528. __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
  1529. {
  1530. uint32_t result;
  1531. __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1532. return(result);
  1533. }
  1534. __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
  1535. {
  1536. uint32_t result;
  1537. __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1538. return(result);
  1539. }
  1540. #define __SSAT16(ARG1,ARG2) \
  1541. ({ \
  1542. int32_t __RES, __ARG1 = (ARG1); \
  1543. __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  1544. __RES; \
  1545. })
  1546. #define __USAT16(ARG1,ARG2) \
  1547. ({ \
  1548. uint32_t __RES, __ARG1 = (ARG1); \
  1549. __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  1550. __RES; \
  1551. })
  1552. __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
  1553. {
  1554. uint32_t result;
  1555. __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
  1556. return(result);
  1557. }
  1558. __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
  1559. {
  1560. uint32_t result;
  1561. __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1562. return(result);
  1563. }
  1564. __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
  1565. {
  1566. uint32_t result;
  1567. __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
  1568. return(result);
  1569. }
  1570. __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
  1571. {
  1572. uint32_t result;
  1573. __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1574. return(result);
  1575. }
  1576. __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
  1577. {
  1578. uint32_t result;
  1579. __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1580. return(result);
  1581. }
  1582. __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
  1583. {
  1584. uint32_t result;
  1585. __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1586. return(result);
  1587. }
  1588. __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
  1589. {
  1590. uint32_t result;
  1591. __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1592. return(result);
  1593. }
  1594. __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
  1595. {
  1596. uint32_t result;
  1597. __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1598. return(result);
  1599. }
  1600. __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
  1601. {
  1602. union llreg_u{
  1603. uint32_t w32[2];
  1604. uint64_t w64;
  1605. } llr;
  1606. llr.w64 = acc;
  1607. #ifndef __ARMEB__ /* Little endian */
  1608. __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
  1609. #else /* Big endian */
  1610. __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
  1611. #endif
  1612. return(llr.w64);
  1613. }
  1614. __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
  1615. {
  1616. union llreg_u{
  1617. uint32_t w32[2];
  1618. uint64_t w64;
  1619. } llr;
  1620. llr.w64 = acc;
  1621. #ifndef __ARMEB__ /* Little endian */
  1622. __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
  1623. #else /* Big endian */
  1624. __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
  1625. #endif
  1626. return(llr.w64);
  1627. }
  1628. __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
  1629. {
  1630. uint32_t result;
  1631. __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1632. return(result);
  1633. }
  1634. __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
  1635. {
  1636. uint32_t result;
  1637. __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1638. return(result);
  1639. }
  1640. __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
  1641. {
  1642. uint32_t result;
  1643. __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1644. return(result);
  1645. }
  1646. __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
  1647. {
  1648. uint32_t result;
  1649. __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1650. return(result);
  1651. }
  1652. __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
  1653. {
  1654. union llreg_u{
  1655. uint32_t w32[2];
  1656. uint64_t w64;
  1657. } llr;
  1658. llr.w64 = acc;
  1659. #ifndef __ARMEB__ /* Little endian */
  1660. __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
  1661. #else /* Big endian */
  1662. __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
  1663. #endif
  1664. return(llr.w64);
  1665. }
  1666. __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
  1667. {
  1668. union llreg_u{
  1669. uint32_t w32[2];
  1670. uint64_t w64;
  1671. } llr;
  1672. llr.w64 = acc;
  1673. #ifndef __ARMEB__ /* Little endian */
  1674. __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
  1675. #else /* Big endian */
  1676. __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
  1677. #endif
  1678. return(llr.w64);
  1679. }
  1680. __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
  1681. {
  1682. uint32_t result;
  1683. __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1684. return(result);
  1685. }
  1686. __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
  1687. {
  1688. int32_t result;
  1689. __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1690. return(result);
  1691. }
  1692. __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
  1693. {
  1694. int32_t result;
  1695. __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1696. return(result);
  1697. }
  1698. #if 0
  1699. #define __PKHBT(ARG1,ARG2,ARG3) \
  1700. ({ \
  1701. uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
  1702. __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
  1703. __RES; \
  1704. })
  1705. #define __PKHTB(ARG1,ARG2,ARG3) \
  1706. ({ \
  1707. uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
  1708. if (ARG3 == 0) \
  1709. __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
  1710. else \
  1711. __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
  1712. __RES; \
  1713. })
  1714. #endif
  1715. #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
  1716. ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
  1717. #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
  1718. ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
  1719. __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
  1720. {
  1721. int32_t result;
  1722. __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
  1723. return(result);
  1724. }
  1725. #endif /* (__ARM_FEATURE_DSP == 1) */
  1726. /*@} end of group CMSIS_SIMD_intrinsics */
  1727. #pragma GCC diagnostic pop
  1728. #endif /* __CMSIS_GCC_H */