scf0403_lcd.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * scf0403.c -- support for DataImage SCF0403 LCD
  4. *
  5. * Copyright (c) 2013 Adapted from Linux driver:
  6. * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved.
  7. * Copyright (c) 2012 CompuLab, Ltd
  8. * Dmitry Lifshitz <lifshitz@compulab.co.il>
  9. * Ilya Ledvich <ilya@compulab.co.il>
  10. * Inspired by Alberto Panizzo <maramaopercheseimorto@gmail.com> &
  11. * Marek Vasut work in l4f00242t03.c
  12. *
  13. * U-Boot port: Nikita Kiryanov <nikita@compulab.co.il>
  14. */
  15. #include <common.h>
  16. #include <asm/gpio.h>
  17. #include <spi.h>
  18. struct scf0403_cmd {
  19. u16 cmd;
  20. u16 *params;
  21. int count;
  22. };
  23. struct scf0403_initseq_entry {
  24. struct scf0403_cmd cmd;
  25. int delay_ms;
  26. };
  27. struct scf0403_priv {
  28. struct spi_slave *spi;
  29. unsigned int reset_gpio;
  30. u32 rddid;
  31. struct scf0403_initseq_entry *init_seq;
  32. int seq_size;
  33. };
  34. struct scf0403_priv priv;
  35. #define SCF0403852GGU04_ID 0x000080
  36. /* SCF0403526GGU20 model commands parameters */
  37. static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06};
  38. static u16 spiinttype_params_sn20[] = {0x60};
  39. static u16 bc_params_sn20[] = {
  40. 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B,
  41. 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01,
  42. 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40,
  43. };
  44. static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67};
  45. static u16 be_params_sn20[] = {
  46. 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22,
  47. };
  48. static u16 vcom_params_sn20[] = {0x74};
  49. static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00};
  50. static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00};
  51. static u16 lvglvolt_params_sn20[] = {0x08};
  52. static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20};
  53. static u16 dispfunc_params_sn20[] = {0xa0};
  54. static u16 dvddvolt_params_sn20[] = {0x74};
  55. static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00};
  56. static u16 panelres_params_sn20[] = {0x82};
  57. static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13};
  58. static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28};
  59. static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20};
  60. static u16 memaccess_params_sn20[] = {0x00};
  61. static u16 pixfmt_params_sn20[] = {0x66};
  62. static u16 pgamma_params_sn20[] = {
  63. 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04,
  64. 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10,
  65. };
  66. static u16 ngamma_params_sn20[] = {
  67. 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03,
  68. 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00,
  69. };
  70. static u16 tearing_params_sn20[] = {0x00};
  71. /* SCF0403852GGU04 model commands parameters */
  72. static u16 memaccess_params_sn04[] = {0x08};
  73. static u16 pixfmt_params_sn04[] = {0x66};
  74. static u16 modectl_params_sn04[] = {0x01};
  75. static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04};
  76. static u16 vcom_params_sn04[] = {0x00, 0x6A};
  77. static u16 pgamma_params_sn04[] = {
  78. 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c,
  79. 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f,
  80. };
  81. static u16 ngamma_params_sn04[] = {
  82. 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05,
  83. 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00,
  84. };
  85. static u16 dispinv_params_sn04[] = {0x02};
  86. /* Common commands */
  87. static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0};
  88. static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0};
  89. /* SCF0403852GGU04 init sequence */
  90. static struct scf0403_initseq_entry scf0403_initseq_sn04[] = {
  91. {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0},
  92. {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0},
  93. {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0},
  94. {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0},
  95. {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0},
  96. {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20},
  97. {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0},
  98. {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100},
  99. };
  100. /* SCF0403526GGU20 init sequence */
  101. static struct scf0403_initseq_entry scf0403_initseq_sn20[] = {
  102. {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0},
  103. {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0},
  104. {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0},
  105. {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0},
  106. {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0},
  107. {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0},
  108. {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0},
  109. {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0},
  110. {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0},
  111. {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0},
  112. {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0},
  113. {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0},
  114. {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0},
  115. {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0},
  116. {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0},
  117. {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0},
  118. {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0},
  119. {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0},
  120. {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0},
  121. {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0},
  122. {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0},
  123. {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0},
  124. };
  125. static void scf0403_gpio_reset(unsigned int gpio)
  126. {
  127. if (!gpio_is_valid(gpio))
  128. return;
  129. gpio_set_value(gpio, 1);
  130. mdelay(100);
  131. gpio_set_value(gpio, 0);
  132. mdelay(40);
  133. gpio_set_value(gpio, 1);
  134. mdelay(100);
  135. }
  136. static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid)
  137. {
  138. int error = 0;
  139. u8 ids_buf = 0x00;
  140. u16 dummy_buf = 0x00;
  141. u16 cmd = 0x04;
  142. error = spi_set_wordlen(spi, 9);
  143. if (error)
  144. return error;
  145. /* Here 9 bits required to transmit a command */
  146. error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE);
  147. if (error)
  148. return error;
  149. /*
  150. * Here 8 + 1 bits required to arrange extra clock cycle
  151. * before the first data bit.
  152. * According to the datasheet - first parameter is the dummy data.
  153. */
  154. error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE);
  155. if (error)
  156. return error;
  157. error = spi_set_wordlen(spi, 8);
  158. if (error)
  159. return error;
  160. /* Read rest of the data */
  161. error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE);
  162. if (error)
  163. return error;
  164. *rddid = ids_buf;
  165. return 0;
  166. }
  167. static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd)
  168. {
  169. int i, error;
  170. u32 command = cmd->cmd;
  171. u32 msg;
  172. error = spi_set_wordlen(spi, 9);
  173. if (error)
  174. return error;
  175. error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE);
  176. if (error)
  177. return error;
  178. for (i = 0; i < cmd->count; i++) {
  179. msg = (cmd->params[i] | 0x100);
  180. error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE);
  181. if (error)
  182. return error;
  183. }
  184. return 0;
  185. }
  186. static void scf0403_lcd_init(struct scf0403_priv *priv)
  187. {
  188. int i;
  189. /* reset LCD */
  190. scf0403_gpio_reset(priv->reset_gpio);
  191. for (i = 0; i < priv->seq_size; i++) {
  192. if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0)
  193. puts("SPI transfer failed\n");
  194. mdelay(priv->init_seq[i].delay_ms);
  195. }
  196. }
  197. static int scf0403_request_reset_gpio(unsigned gpio)
  198. {
  199. int err = gpio_request(gpio, "lcd reset");
  200. if (err)
  201. return err;
  202. err = gpio_direction_output(gpio, 0);
  203. if (err)
  204. gpio_free(gpio);
  205. return err;
  206. }
  207. int scf0403_init(int reset_gpio)
  208. {
  209. int error;
  210. if (gpio_is_valid(reset_gpio)) {
  211. error = scf0403_request_reset_gpio(reset_gpio);
  212. if (error) {
  213. printf("Failed requesting reset GPIO%d: %d\n",
  214. reset_gpio, error);
  215. return error;
  216. }
  217. }
  218. priv.reset_gpio = reset_gpio;
  219. priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0);
  220. error = spi_claim_bus(priv.spi);
  221. if (error)
  222. goto bus_claim_fail;
  223. /* reset LCD */
  224. scf0403_gpio_reset(reset_gpio);
  225. error = scf0403_spi_read_rddid(priv.spi, &priv.rddid);
  226. if (error) {
  227. puts("IDs read failed\n");
  228. goto readid_fail;
  229. }
  230. if (priv.rddid == SCF0403852GGU04_ID) {
  231. priv.init_seq = scf0403_initseq_sn04;
  232. priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04);
  233. } else {
  234. priv.init_seq = scf0403_initseq_sn20;
  235. priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20);
  236. }
  237. scf0403_lcd_init(&priv);
  238. /* Start operation */
  239. scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison);
  240. mdelay(100);
  241. scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout);
  242. spi_release_bus(priv.spi);
  243. return 0;
  244. readid_fail:
  245. spi_release_bus(priv.spi);
  246. bus_claim_fail:
  247. if (gpio_is_valid(priv.reset_gpio))
  248. gpio_free(priv.reset_gpio);
  249. return error;
  250. }