mvebu_lcd.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Video driver for Marvell Armada XP SoC
  4. *
  5. * Initialization of LCD interface and setup of SPLASH screen image
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <video.h>
  10. #include <linux/mbus.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/soc.h>
  14. #define MVEBU_LCD_WIN_CONTROL(w) (0xf000 + ((w) << 4))
  15. #define MVEBU_LCD_WIN_BASE(w) (0xf004 + ((w) << 4))
  16. #define MVEBU_LCD_WIN_REMAP(w) (0xf00c + ((w) << 4))
  17. #define MVEBU_LCD_CFG_DMA_START_ADDR_0 0x00cc
  18. #define MVEBU_LCD_CFG_DMA_START_ADDR_1 0x00dc
  19. #define MVEBU_LCD_CFG_GRA_START_ADDR0 0x00f4
  20. #define MVEBU_LCD_CFG_GRA_START_ADDR1 0x00f8
  21. #define MVEBU_LCD_CFG_GRA_PITCH 0x00fc
  22. #define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
  23. #define MVEBU_LCD_SPU_GRA_HPXL_VLN 0x0104
  24. #define MVEBU_LCD_SPU_GZM_HPXL_VLN 0x0108
  25. #define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN 0x010c
  26. #define MVEBU_LCD_SPU_HWC_HPXL_VLN 0x0110
  27. #define MVEBU_LCD_SPUT_V_H_TOTAL 0x0114
  28. #define MVEBU_LCD_SPU_V_H_ACTIVE 0x0118
  29. #define MVEBU_LCD_SPU_H_PORCH 0x011c
  30. #define MVEBU_LCD_SPU_V_PORCH 0x0120
  31. #define MVEBU_LCD_SPU_BLANKCOLOR 0x0124
  32. #define MVEBU_LCD_SPU_ALPHA_COLOR1 0x0128
  33. #define MVEBU_LCD_SPU_ALPHA_COLOR2 0x012c
  34. #define MVEBU_LCD_SPU_COLORKEY_Y 0x0130
  35. #define MVEBU_LCD_SPU_COLORKEY_U 0x0134
  36. #define MVEBU_LCD_SPU_COLORKEY_V 0x0138
  37. #define MVEBU_LCD_CFG_RDREG4F 0x013c
  38. #define MVEBU_LCD_SPU_SPI_RXDATA 0x0140
  39. #define MVEBU_LCD_SPU_ISA_RXDATA 0x0144
  40. #define MVEBU_LCD_SPU_DBG_ISA 0x0148
  41. #define MVEBU_LCD_SPU_HWC_RDDAT 0x0158
  42. #define MVEBU_LCD_SPU_GAMMA_RDDAT 0x015c
  43. #define MVEBU_LCD_SPU_PALETTE_RDDAT 0x0160
  44. #define MVEBU_LCD_SPU_IOPAD_IN 0x0178
  45. #define MVEBU_LCD_FRAME_COUNT 0x017c
  46. #define MVEBU_LCD_SPU_DMA_CTRL0 0x0190
  47. #define MVEBU_LCD_SPU_DMA_CTRL1 0x0194
  48. #define MVEBU_LCD_SPU_SRAM_CTRL 0x0198
  49. #define MVEBU_LCD_SPU_SRAM_WRDAT 0x019c
  50. #define MVEBU_LCD_SPU_SRAM_PARA0 0x01a0
  51. #define MVEBU_LCD_SPU_SRAM_PARA1 0x01a4
  52. #define MVEBU_LCD_CFG_SCLK_DIV 0x01a8
  53. #define MVEBU_LCD_SPU_CONTRAST 0x01ac
  54. #define MVEBU_LCD_SPU_SATURATION 0x01b0
  55. #define MVEBU_LCD_SPU_CBSH_HUE 0x01b4
  56. #define MVEBU_LCD_SPU_DUMB_CTRL 0x01b8
  57. #define MVEBU_LCD_SPU_IOPAD_CONTROL 0x01bc
  58. #define MVEBU_LCD_SPU_IRQ_ENA_2 0x01d8
  59. #define MVEBU_LCD_SPU_IRQ_ISR_2 0x01dc
  60. #define MVEBU_LCD_SPU_IRQ_ENA 0x01c0
  61. #define MVEBU_LCD_SPU_IRQ_ISR 0x01c4
  62. #define MVEBU_LCD_ADLL_CTRL 0x01c8
  63. #define MVEBU_LCD_CLK_DIS 0x01cc
  64. #define MVEBU_LCD_VGA_HVSYNC_DELAY 0x01d4
  65. #define MVEBU_LCD_CLK_CFG_0 0xf0a0
  66. #define MVEBU_LCD_CLK_CFG_1 0xf0a4
  67. #define MVEBU_LCD_LVDS_CLK_CFG 0xf0ac
  68. #define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0)
  69. enum {
  70. /* Maximum LCD size we support */
  71. LCD_MAX_WIDTH = 640,
  72. LCD_MAX_HEIGHT = 480,
  73. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  74. };
  75. struct mvebu_lcd_info {
  76. u32 fb_base;
  77. int x_res;
  78. int y_res;
  79. int x_fp;
  80. int y_fp;
  81. int x_bp;
  82. int y_bp;
  83. };
  84. struct mvebu_video_priv {
  85. uintptr_t regs;
  86. };
  87. /* Setup Mbus Bridge Windows for LCD */
  88. static void mvebu_lcd_conf_mbus_registers(uintptr_t regs)
  89. {
  90. const struct mbus_dram_target_info *dram;
  91. int i;
  92. dram = mvebu_mbus_dram_info();
  93. /* Disable windows, set size/base/remap to 0 */
  94. for (i = 0; i < 6; i++) {
  95. writel(0, regs + MVEBU_LCD_WIN_CONTROL(i));
  96. writel(0, regs + MVEBU_LCD_WIN_BASE(i));
  97. writel(0, regs + MVEBU_LCD_WIN_REMAP(i));
  98. }
  99. /* Write LCD bridge window registers */
  100. for (i = 0; i < dram->num_cs; i++) {
  101. const struct mbus_dram_window *cs = dram->cs + i;
  102. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  103. (dram->mbus_dram_target_id << 4) | 1,
  104. regs + MVEBU_LCD_WIN_CONTROL(i));
  105. writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i));
  106. }
  107. }
  108. /* Initialize LCD registers */
  109. static void mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info,
  110. uintptr_t regs)
  111. {
  112. /* Local variable for easier handling */
  113. int x = lcd_info->x_res;
  114. int y = lcd_info->y_res;
  115. u32 val;
  116. /* Setup Mbus Bridge Windows */
  117. mvebu_lcd_conf_mbus_registers(regs);
  118. /*
  119. * Set LVDS Pads Control Register
  120. * wr 0 182F0 FFE00000
  121. */
  122. clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16);
  123. /*
  124. * Set the LCD_CFG_GRA_START_ADDR0/1 Registers
  125. * This is supposed to point to the "physical" memory at memory
  126. * end (currently 1GB-64MB but also may be 2GB-64MB).
  127. * See also the Window 0 settings!
  128. */
  129. writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR0);
  130. writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR1);
  131. /*
  132. * Set the LCD_CFG_GRA_PITCH Register
  133. * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting)
  134. * Bits 25-16: Backlight divider from 32kHz Clock
  135. * (here 16=0x10 for 1kHz)
  136. * Bits 15-00: Line Length in Bytes
  137. * 240*2 (for RGB1555)=480=0x1E0
  138. */
  139. writel(0x80100000 + 2 * x, regs + MVEBU_LCD_CFG_GRA_PITCH);
  140. /*
  141. * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register
  142. * Bits 31-16: Vertical start of graphical overlay on screen
  143. * Bits 15-00: Horizontal start of graphical overlay on screen
  144. */
  145. writel(0x00000000, regs + MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN);
  146. /*
  147. * Set the LCD_SPU_GRA_HPXL_VLN Register
  148. * Bits 31-16: Vertical size of graphical overlay 320=0x140
  149. * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
  150. * Values before zooming
  151. */
  152. writel((y << 16) | x, regs + MVEBU_LCD_SPU_GRA_HPXL_VLN);
  153. /*
  154. * Set the LCD_SPU_GZM_HPXL_VLN Register
  155. * Bits 31-16: Vertical size of graphical overlay 320=0x140
  156. * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
  157. * Values after zooming
  158. */
  159. writel((y << 16) | x, regs + MVEBU_LCD_SPU_GZM_HPXL_VLN);
  160. /*
  161. * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
  162. * Bits 31-16: Vertical position of HW Cursor 320=0x140
  163. * Bits 15-00: Horizontal position of HW Cursor 240=0xF0
  164. */
  165. writel((y << 16) | x, regs + MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN);
  166. /*
  167. * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
  168. * Bits 31-16: Vertical size of HW Cursor
  169. * Bits 15-00: Horizontal size of HW Cursor
  170. */
  171. writel(0x00000000, regs + MVEBU_LCD_SPU_HWC_HPXL_VLN);
  172. /*
  173. * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
  174. * Bits 31-16: Screen total vertical lines:
  175. * VSYNC = 1
  176. * Vertical Front Porch = 2
  177. * Vertical Lines = 320
  178. * Vertical Back Porch = 2
  179. * SUM = 325 = 0x0145
  180. * Bits 15-00: Screen total horizontal pixels:
  181. * HSYNC = 1
  182. * Horizontal Front Porch = 44
  183. * Horizontal Lines = 240
  184. * Horizontal Back Porch = 2
  185. * SUM = 287 = 0x011F
  186. * Note: For the display the backporch is between SYNC and
  187. * the start of the pixels.
  188. * This is not certain for the Marvell (!?)
  189. */
  190. val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) |
  191. (x + lcd_info->x_fp + lcd_info->x_bp + 1);
  192. writel(val, regs + MVEBU_LCD_SPUT_V_H_TOTAL);
  193. /*
  194. * Set the LCD_SPU_V_H_ACTIVE Register
  195. * Bits 31-16: Screen active vertical lines 320=0x140
  196. * Bits 15-00: Screen active horizontakl pixels 240=0x00F0
  197. */
  198. writel((y << 16) | x, regs + MVEBU_LCD_SPU_V_H_ACTIVE);
  199. /*
  200. * Set the LCD_SPU_H_PORCH Register
  201. * Bits 31-16: Screen horizontal backporch 44=0x2c
  202. * Bits 15-00: Screen horizontal frontporch 2=0x02
  203. * Note: The terms "front" and "back" for the Marvell seem to be
  204. * exactly opposite to the display.
  205. */
  206. writel((lcd_info->x_fp << 16) | lcd_info->x_bp,
  207. regs + MVEBU_LCD_SPU_H_PORCH);
  208. /*
  209. * Set the LCD_SPU_V_PORCH Register
  210. * Bits 31-16: Screen vertical backporch 2=0x02
  211. * Bits 15-00: Screen vertical frontporch 2=0x02
  212. * Note: The terms "front" and "back" for the Marvell seem to be exactly
  213. * opposite to the display.
  214. */
  215. writel((lcd_info->y_fp << 16) | lcd_info->y_bp,
  216. regs + MVEBU_LCD_SPU_V_PORCH);
  217. /*
  218. * Set the LCD_SPU_BLANKCOLOR Register
  219. * This should be black = 0
  220. * For tests this is magenta=00FF00FF
  221. */
  222. writel(0x00FF00FF, regs + MVEBU_LCD_SPU_BLANKCOLOR);
  223. /*
  224. * Registers in the range of 0x0128 to 0x012C are colors for the cursor
  225. * Registers in the range of 0x0130 to 0x0138 are colors for video
  226. * color keying
  227. */
  228. /*
  229. * Set the LCD_SPU_RDREG4F Register
  230. * Bits 31-12: Reservd
  231. * Bit 11: SRAM Wait
  232. * Bit 10: Smart display fast TX (must be 1)
  233. * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved
  234. * Bit 8: FIFO watermark for DMA: 0=disable
  235. * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80
  236. */
  237. writel(0x00000780, regs + MVEBU_LCD_CFG_RDREG4F);
  238. /*
  239. * Set the LCD_SPU_DMACTRL 0 Register
  240. * Bit 31: Disable overlay blending 1=disable
  241. * Bit 30: Gamma correction enable, 0=disable
  242. * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable
  243. * Bit 28: Color palette enable, 0=disable
  244. * Bit 27: DMA AXI Arbiter, 1=default
  245. * Bit 26: HW Cursor 1-bit mode
  246. * Bit 25: HW Cursor or 1- or 2-bit mode
  247. * Bit 24: HW Cursor enabled, 0=disable
  248. * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555
  249. * Bits 19-16: Video Memory Color Format: 0x1=RGB1555
  250. * Bit 15: Memory Toggle between frame 0 and 1: 0=disable
  251. * Bit 14: Graphics horizontal scaling enable: 0=disable
  252. * Bit 13: Graphics test mode: 0=disable
  253. * Bit 12: Graphics SWAP R and B: 0=disable
  254. * Bit 11: Graphics SWAP U and V: 0=disable
  255. * Bit 10: Graphics SWAP Y and U/V: 0=disable
  256. * Bit 09: Graphic YUV to RGB Conversion: 0=disable
  257. * Bit 08: Graphic Transfer: 1=enable
  258. * Bit 07: Memory Toggle: 0=disable
  259. * Bit 06: Video horizontal scaling enable: 0=disable
  260. * Bit 05: Video test mode: 0=disable
  261. * Bit 04: Video SWAP R and B: 0=disable
  262. * Bit 03: Video SWAP U and V: 0=disable
  263. * Bit 02: Video SWAP Y and U/V: 0=disable
  264. * Bit 01: Video YUV to RGB Conversion: 0=disable
  265. * Bit 00: Video Transfer: 0=disable
  266. */
  267. writel(0x88111100, regs + MVEBU_LCD_SPU_DMA_CTRL0);
  268. /*
  269. * Set the LCD_SPU_DMA_CTRL1 Register
  270. * Bit 31: Manual DMA Trigger = 0
  271. * Bits 30-28: DMA Trigger Source: 0x2 VSYNC
  272. * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge
  273. * Bits 26-24: Color Key Mode: 0=disable
  274. * Bit 23: Fill low bits: 0=fill with zeroes
  275. * Bit 22: Reserved
  276. * Bit 21: Gated Clock: 0=disable
  277. * Bit 20: Power Save enable: 0=disable
  278. * Bits 19-18: Reserved
  279. * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha.
  280. * Bits 15-08: Configure Alpha: 0x00.
  281. * Bits 07-00: Reserved.
  282. */
  283. writel(0x20010000, regs + MVEBU_LCD_SPU_DMA_CTRL1);
  284. /*
  285. * Set the LCD_SPU_SRAM_CTRL Register
  286. * Reset to default = 0000C000
  287. * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2
  288. * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb,
  289. * 3=palette, 15=cursor
  290. */
  291. writel(0x0000C000, regs + MVEBU_LCD_SPU_SRAM_CTRL);
  292. /*
  293. * LCD_SPU_SRAM_WRDAT register: 019C
  294. * LCD_SPU_SRAM_PARA0 register: 01A0
  295. * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings
  296. */
  297. writel(0x00000000, regs + MVEBU_LCD_SPU_SRAM_PARA1);
  298. /* Clock settings in the at 01A8 and in the range F0A0 see below */
  299. /*
  300. * Set LCD_SPU_CONTRAST
  301. * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0
  302. * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0
  303. */
  304. writel(0x00000000, regs + MVEBU_LCD_SPU_CONTRAST);
  305. /*
  306. * Set LCD_SPU_SATURATION
  307. * Bits 31-16: Multiplier signed 4.12 fixed point value
  308. * Bits 15-00: Saturation signed 4.12 fixed point value
  309. */
  310. writel(0x10001000, regs + MVEBU_LCD_SPU_SATURATION);
  311. /*
  312. * Set LCD_SPU_HUE
  313. * Bits 31-16: Sine signed 2.14 fixed point value
  314. * Bits 15-00: Cosine signed 2.14 fixed point value
  315. */
  316. writel(0x00000000, regs + MVEBU_LCD_SPU_CBSH_HUE);
  317. /*
  318. * Set LCD_SPU_DUMB_CTRL
  319. * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888
  320. * Bits 27-12: Reserved
  321. * Bit 11: LCD DMA Pipeline Enable: 1=Enable
  322. * Bits 10-09: Reserved
  323. * Bit 8: LCD GPIO pin (??)
  324. * Bit 7: Reverse RGB
  325. * Bit 6: Invert composite blank signal DE/EN (??)
  326. * Bit 5: Invert composite sync signal
  327. * Bit 4: Invert Pixel Valid Enable DE/EN (??)
  328. * Bit 3: Invert VSYNC
  329. * Bit 2: Invert HSYNC
  330. * Bit 1: Invert Pixel Clock
  331. * Bit 0: Enable LCD Panel: 1=Enable
  332. * Question: Do we have to disable Smart and Dumb LCD
  333. * and separately enable LVDS?
  334. */
  335. writel(0x6000080F, regs + MVEBU_LCD_SPU_DUMB_CTRL);
  336. /*
  337. * Set LCD_SPU_IOPAD_CTRL
  338. * Bits 31-20: Reserved
  339. * Bits 19-18: Vertical Interpolation: 0=Disable
  340. * Bits 17-16: Reserved
  341. * Bit 15: Graphics Vertical Mirror enable: 0=disable
  342. * Bit 14: Reserved
  343. * Bit 13: Video Vertical Mirror enable: 0=disable
  344. * Bit 12: Reserved
  345. * Bit 11: Command Vertical Mirror enable: 0=disable
  346. * Bit 10: Reserved
  347. * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used)
  348. * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary,
  349. * 128 Bytes burst
  350. * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ??
  351. */
  352. writel(0x000000C0, regs + MVEBU_LCD_SPU_IOPAD_CONTROL);
  353. /*
  354. * Set SUP_IRQ_ENA_2: Disable all interrupts
  355. */
  356. writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA_2);
  357. /*
  358. * Set SUP_IRQ_ENA: Disable all interrupts.
  359. */
  360. writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA);
  361. /*
  362. * Set up ADDL Control Register
  363. * Bits 31-29: 0x0 = Fastest Delay Line (default)
  364. * 0x3 = Slowest Delay Line (default)
  365. * Bit 28: Calibration done status.
  366. * Bit 27: Reserved
  367. * Bit 26: Set Pixel Clock to ADDL output
  368. * Bit 25: Reduce CAL Enable
  369. * Bits 24-22: Manual calibration value.
  370. * Bit 21: Manual calibration enable.
  371. * Bit 20: Restart Auto Cal
  372. * Bits 19-16: Calibration Threshold voltage, default= 0x2
  373. * Bite 15-14: Reserved
  374. * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16
  375. * Bit 10: Power Down ADDL module, default = 1!
  376. * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z
  377. * Bit 07: Reset ADDL
  378. * Bit 06: Invert ADLL Clock
  379. * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay
  380. * Note: ADLL is used for a VGA interface with DAC - not used here
  381. */
  382. writel(0x00000000, regs + MVEBU_LCD_ADLL_CTRL);
  383. /*
  384. * Set the LCD_CLK_DIS Register:
  385. * Bits 3 and 4 must be 1
  386. */
  387. writel(0x00000018, regs + MVEBU_LCD_CLK_DIS);
  388. /*
  389. * Set the LCD_VGA_HSYNC/VSYNC Delay Register:
  390. * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals
  391. */
  392. writel(0x00000000, regs + MVEBU_LCD_VGA_HVSYNC_DELAY);
  393. /*
  394. * Clock registers
  395. * See page 475 in the functional spec.
  396. */
  397. /* Step 1 and 2: Disable the PLL */
  398. /*
  399. * Disable PLL, see "LCD Clock Configuration 1 Register" below
  400. */
  401. writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
  402. /*
  403. * Powerdown, see "LCD Clock Configuration 0 Register" below
  404. */
  405. writel(0x94000174, regs + MVEBU_LCD_CLK_CFG_0);
  406. /*
  407. * Set the LCD_CFG_SCLK_DIV Register
  408. * This is set fix to 0x40000001 for the LVDS output:
  409. * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0
  410. * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001
  411. * See page 475 in section 28.5.
  412. */
  413. writel(0x80000001, regs + MVEBU_LCD_CFG_SCLK_DIV);
  414. /*
  415. * Set the LCD Clock Configuration 0 Register:
  416. * Bit 31: Powerdown: 0=Power up
  417. * Bits 30-29: Reserved
  418. * Bits 28-26: PLL_KDIV: This encodes K
  419. * K=16 => 0x5
  420. * Bits 25-17: PLL_MDIV: This is M-1:
  421. * M=1 => 0x0
  422. * Bits 16-13: VCO band: 0x1 for 700-920MHz
  423. * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL!
  424. * N=28=0x1C => 0x1B
  425. * Bits 03-00: R1_CTRL (for N=28 => 0x4)
  426. */
  427. writel(0x940021B4, regs + MVEBU_LCD_CLK_CFG_0);
  428. /*
  429. * Set the LCD Clock Configuration 1 Register:
  430. * Bits 31-19: Reserved
  431. * Bit 18: Select PLL: Core PLL, 1=Dedicated PPL
  432. * Bit 17: Clock Output Enable: 0=disable, 1=enable
  433. * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External
  434. * Bit 15: Half-Div, Device Clock by DIV+0.5*Half-Dev
  435. * Bits 14-13: Reserved
  436. * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider
  437. * M' for LVDS=7!]
  438. */
  439. writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
  440. /*
  441. * Set the LVDS Clock Configuration Register:
  442. * Bit 31: Clock Gating for the input clock to the LVDS
  443. * Bit 30: LVDS Serializer enable: 1=Enabled
  444. * Bits 29-11: Reserved
  445. * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7
  446. * Bits 07-02: Reserved
  447. * Bit 01: 24bbp Option: 0=Option_1,1=Option2
  448. * Bit 00: 1=24bbp Panel: 0=18bpp Panel
  449. * Note: Bits 0 and must be verified with the help of the
  450. * Interface/display
  451. */
  452. writel(0xC0000201, regs + MVEBU_LCD_LVDS_CLK_CFG);
  453. /*
  454. * Power up PLL (Clock Config 0)
  455. */
  456. writel(0x140021B4, regs + MVEBU_LCD_CLK_CFG_0);
  457. /* wait 10 ms */
  458. mdelay(10);
  459. /*
  460. * Enable PLL (Clock Config 1)
  461. */
  462. writel(0x8FF60007, regs + MVEBU_LCD_CLK_CFG_1);
  463. }
  464. static int mvebu_video_probe(struct udevice *dev)
  465. {
  466. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  467. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  468. struct mvebu_video_priv *priv = dev_get_priv(dev);
  469. struct mvebu_lcd_info lcd_info;
  470. struct display_timing timings;
  471. u32 fb_start, fb_end;
  472. int ret;
  473. priv->regs = dev_read_addr(dev);
  474. if (priv->regs == FDT_ADDR_T_NONE) {
  475. dev_err(dev, "failed to get LCD address\n");
  476. return -ENXIO;
  477. }
  478. ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
  479. if (ret) {
  480. dev_err(dev, "failed to get any display timings\n");
  481. return -EINVAL;
  482. }
  483. /* Use DT timing (resolution) in internal info struct */
  484. lcd_info.fb_base = plat->base;
  485. lcd_info.x_res = timings.hactive.typ;
  486. lcd_info.x_fp = timings.hfront_porch.typ;
  487. lcd_info.x_bp = timings.hback_porch.typ;
  488. lcd_info.y_res = timings.vactive.typ;
  489. lcd_info.y_fp = timings.vfront_porch.typ;
  490. lcd_info.y_bp = timings.vback_porch.typ;
  491. /* Initialize the LCD controller */
  492. mvebu_lcd_register_init(&lcd_info, priv->regs);
  493. /* Enable dcache for the frame buffer */
  494. fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  495. fb_end = plat->base + plat->size;
  496. fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  497. mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
  498. DCACHE_WRITEBACK);
  499. video_set_flush_dcache(dev, true);
  500. uc_priv->xsize = lcd_info.x_res;
  501. uc_priv->ysize = lcd_info.y_res;
  502. uc_priv->bpix = VIDEO_BPP16; /* Uses RGB555 format */
  503. return 0;
  504. }
  505. static int mvebu_video_bind(struct udevice *dev)
  506. {
  507. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  508. plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  509. (1 << LCD_MAX_LOG2_BPP) / 8;
  510. return 0;
  511. }
  512. static const struct udevice_id mvebu_video_ids[] = {
  513. { .compatible = "marvell,armada-xp-lcd" },
  514. { }
  515. };
  516. U_BOOT_DRIVER(mvebu_video) = {
  517. .name = "mvebu_video",
  518. .id = UCLASS_VIDEO,
  519. .of_match = mvebu_video_ids,
  520. .bind = mvebu_video_bind,
  521. .probe = mvebu_video_probe,
  522. .priv_auto_alloc_size = sizeof(struct mvebu_video_priv),
  523. };