broadwell_igd.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From coreboot src/soc/intel/broadwell/igd.c
  4. *
  5. * Copyright (C) 2016 Google, Inc
  6. */
  7. #include <common.h>
  8. #include <bios_emul.h>
  9. #include <dm.h>
  10. #include <vbe.h>
  11. #include <video.h>
  12. #include <asm/cpu.h>
  13. #include <asm/intel_regs.h>
  14. #include <asm/io.h>
  15. #include <asm/mtrr.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/iomap.h>
  18. #include <asm/arch/pch.h>
  19. #include "i915_reg.h"
  20. struct broadwell_igd_priv {
  21. u8 *regs;
  22. };
  23. struct broadwell_igd_plat {
  24. u32 dp_hotplug[3];
  25. int port_select;
  26. int power_up_delay;
  27. int power_backlight_on_delay;
  28. int power_down_delay;
  29. int power_backlight_off_delay;
  30. int power_cycle_delay;
  31. int cpu_backlight;
  32. int pch_backlight;
  33. int cdclk;
  34. int pre_graphics_delay;
  35. };
  36. #define GT_RETRY 1000
  37. #define GT_CDCLK_337 0
  38. #define GT_CDCLK_450 1
  39. #define GT_CDCLK_540 2
  40. #define GT_CDCLK_675 3
  41. u32 board_map_oprom_vendev(u32 vendev)
  42. {
  43. return SA_IGD_OPROM_VENDEV;
  44. }
  45. static int poll32(u8 *addr, uint mask, uint value)
  46. {
  47. ulong start;
  48. start = get_timer(0);
  49. debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
  50. while ((readl(addr) & mask) != value) {
  51. if (get_timer(start) > GT_RETRY) {
  52. debug("poll32: timeout: %x\n", readl(addr));
  53. return -ETIMEDOUT;
  54. }
  55. }
  56. return 0;
  57. }
  58. static int haswell_early_init(struct udevice *dev)
  59. {
  60. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  61. u8 *regs = priv->regs;
  62. int ret;
  63. /* Enable Force Wake */
  64. writel(0x00000020, regs + 0xa180);
  65. writel(0x00010001, regs + 0xa188);
  66. ret = poll32(regs + 0x130044, 1, 1);
  67. if (ret)
  68. goto err;
  69. /* Enable Counters */
  70. setbits_le32(regs + 0xa248, 0x00000016);
  71. /* GFXPAUSE settings */
  72. writel(0x00070020, regs + 0xa000);
  73. /* ECO Settings */
  74. clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
  75. /* Enable DOP Clock Gating */
  76. writel(0x000003fd, regs + 0x9424);
  77. /* Enable Unit Level Clock Gating */
  78. writel(0x00000080, regs + 0x9400);
  79. writel(0x40401000, regs + 0x9404);
  80. writel(0x00000000, regs + 0x9408);
  81. writel(0x02000001, regs + 0x940c);
  82. /*
  83. * RC6 Settings
  84. */
  85. /* Wake Rate Limits */
  86. setbits_le32(regs + 0xa090, 0x00000000);
  87. setbits_le32(regs + 0xa098, 0x03e80000);
  88. setbits_le32(regs + 0xa09c, 0x00280000);
  89. setbits_le32(regs + 0xa0a8, 0x0001e848);
  90. setbits_le32(regs + 0xa0ac, 0x00000019);
  91. /* Render/Video/Blitter Idle Max Count */
  92. writel(0x0000000a, regs + 0x02054);
  93. writel(0x0000000a, regs + 0x12054);
  94. writel(0x0000000a, regs + 0x22054);
  95. writel(0x0000000a, regs + 0x1a054);
  96. /* RC Sleep / RCx Thresholds */
  97. setbits_le32(regs + 0xa0b0, 0x00000000);
  98. setbits_le32(regs + 0xa0b4, 0x000003e8);
  99. setbits_le32(regs + 0xa0b8, 0x0000c350);
  100. /* RP Settings */
  101. setbits_le32(regs + 0xa010, 0x000f4240);
  102. setbits_le32(regs + 0xa014, 0x12060000);
  103. setbits_le32(regs + 0xa02c, 0x0000e808);
  104. setbits_le32(regs + 0xa030, 0x0003bd08);
  105. setbits_le32(regs + 0xa068, 0x000101d0);
  106. setbits_le32(regs + 0xa06c, 0x00055730);
  107. setbits_le32(regs + 0xa070, 0x0000000a);
  108. /* RP Control */
  109. writel(0x00000b92, regs + 0xa024);
  110. /* HW RC6 Control */
  111. writel(0x88040000, regs + 0xa090);
  112. /* Video Frequency Request */
  113. writel(0x08000000, regs + 0xa00c);
  114. /* Set RC6 VIDs */
  115. ret = poll32(regs + 0x138124, (1 << 31), 0);
  116. if (ret)
  117. goto err;
  118. writel(0, regs + 0x138128);
  119. writel(0x80000004, regs + 0x138124);
  120. ret = poll32(regs + 0x138124, (1 << 31), 0);
  121. if (ret)
  122. goto err;
  123. /* Enable PM Interrupts */
  124. writel(0x03000076, regs + 0x4402c);
  125. /* Enable RC6 in idle */
  126. writel(0x00040000, regs + 0xa094);
  127. return 0;
  128. err:
  129. debug("%s: ret=%d\n", __func__, ret);
  130. return ret;
  131. };
  132. static int haswell_late_init(struct udevice *dev)
  133. {
  134. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  135. u8 *regs = priv->regs;
  136. int ret;
  137. /* Lock settings */
  138. setbits_le32(regs + 0x0a248, (1 << 31));
  139. setbits_le32(regs + 0x0a004, (1 << 4));
  140. setbits_le32(regs + 0x0a080, (1 << 2));
  141. setbits_le32(regs + 0x0a180, (1 << 31));
  142. /* Disable Force Wake */
  143. writel(0x00010000, regs + 0xa188);
  144. ret = poll32(regs + 0x130044, 1, 0);
  145. if (ret)
  146. goto err;
  147. writel(0x00000001, regs + 0xa188);
  148. /* Enable power well for DP and Audio */
  149. setbits_le32(regs + 0x45400, (1 << 31));
  150. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  151. if (ret)
  152. goto err;
  153. return 0;
  154. err:
  155. debug("%s: ret=%d\n", __func__, ret);
  156. return ret;
  157. };
  158. static int broadwell_early_init(struct udevice *dev)
  159. {
  160. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  161. u8 *regs = priv->regs;
  162. int ret;
  163. /* Enable Force Wake */
  164. writel(0x00010001, regs + 0xa188);
  165. ret = poll32(regs + 0x130044, 1, 1);
  166. if (ret)
  167. goto err;
  168. /* Enable push bus metric control and shift */
  169. writel(0x00000004, regs + 0xa248);
  170. writel(0x000000ff, regs + 0xa250);
  171. writel(0x00000010, regs + 0xa25c);
  172. /* GFXPAUSE settings (set based on stepping) */
  173. /* ECO Settings */
  174. writel(0x45200000, regs + 0xa180);
  175. /* Enable DOP Clock Gating */
  176. writel(0x000000fd, regs + 0x9424);
  177. /* Enable Unit Level Clock Gating */
  178. writel(0x00000000, regs + 0x9400);
  179. writel(0x40401000, regs + 0x9404);
  180. writel(0x00000000, regs + 0x9408);
  181. writel(0x02000001, regs + 0x940c);
  182. writel(0x0000000a, regs + 0x1a054);
  183. /* Video Frequency Request */
  184. writel(0x08000000, regs + 0xa00c);
  185. writel(0x00000009, regs + 0x138158);
  186. writel(0x0000000d, regs + 0x13815c);
  187. /*
  188. * RC6 Settings
  189. */
  190. /* Wake Rate Limits */
  191. clrsetbits_le32(regs + 0x0a090, ~0, 0);
  192. setbits_le32(regs + 0x0a098, 0x03e80000);
  193. setbits_le32(regs + 0x0a09c, 0x00280000);
  194. setbits_le32(regs + 0x0a0a8, 0x0001e848);
  195. setbits_le32(regs + 0x0a0ac, 0x00000019);
  196. /* Render/Video/Blitter Idle Max Count */
  197. writel(0x0000000a, regs + 0x02054);
  198. writel(0x0000000a, regs + 0x12054);
  199. writel(0x0000000a, regs + 0x22054);
  200. /* RC Sleep / RCx Thresholds */
  201. setbits_le32(regs + 0x0a0b0, 0x00000000);
  202. setbits_le32(regs + 0x0a0b8, 0x00000271);
  203. /* RP Settings */
  204. setbits_le32(regs + 0x0a010, 0x000f4240);
  205. setbits_le32(regs + 0x0a014, 0x12060000);
  206. setbits_le32(regs + 0x0a02c, 0x0000e808);
  207. setbits_le32(regs + 0x0a030, 0x0003bd08);
  208. setbits_le32(regs + 0x0a068, 0x000101d0);
  209. setbits_le32(regs + 0x0a06c, 0x00055730);
  210. setbits_le32(regs + 0x0a070, 0x0000000a);
  211. setbits_le32(regs + 0x0a168, 0x00000006);
  212. /* RP Control */
  213. writel(0x00000b92, regs + 0xa024);
  214. /* HW RC6 Control */
  215. writel(0x90040000, regs + 0xa090);
  216. /* Set RC6 VIDs */
  217. ret = poll32(regs + 0x138124, (1 << 31), 0);
  218. if (ret)
  219. goto err;
  220. writel(0, regs + 0x138128);
  221. writel(0x80000004, regs + 0x138124);
  222. ret = poll32(regs + 0x138124, (1 << 31), 0);
  223. if (ret)
  224. goto err;
  225. /* Enable PM Interrupts */
  226. writel(0x03000076, regs + 0x4402c);
  227. /* Enable RC6 in idle */
  228. writel(0x00040000, regs + 0xa094);
  229. return 0;
  230. err:
  231. debug("%s: ret=%d\n", __func__, ret);
  232. return ret;
  233. }
  234. static int broadwell_late_init(struct udevice *dev)
  235. {
  236. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  237. u8 *regs = priv->regs;
  238. int ret;
  239. /* Lock settings */
  240. setbits_le32(regs + 0x0a248, 1 << 31);
  241. setbits_le32(regs + 0x0a000, 1 << 18);
  242. setbits_le32(regs + 0x0a180, 1 << 31);
  243. /* Disable Force Wake */
  244. writel(0x00010000, regs + 0xa188);
  245. ret = poll32(regs + 0x130044, 1, 0);
  246. if (ret)
  247. goto err;
  248. /* Enable power well for DP and Audio */
  249. setbits_le32(regs + 0x45400, 1 << 31);
  250. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  251. if (ret)
  252. goto err;
  253. return 0;
  254. err:
  255. debug("%s: ret=%d\n", __func__, ret);
  256. return ret;
  257. };
  258. static unsigned long gtt_read(struct broadwell_igd_priv *priv,
  259. unsigned long reg)
  260. {
  261. return readl(priv->regs + reg);
  262. }
  263. static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
  264. unsigned long data)
  265. {
  266. writel(data, priv->regs + reg);
  267. }
  268. static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
  269. u32 bic, u32 or)
  270. {
  271. clrsetbits_le32(priv->regs + reg, bic, or);
  272. }
  273. static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
  274. u32 value)
  275. {
  276. unsigned try = GT_RETRY;
  277. u32 data;
  278. while (try--) {
  279. data = gtt_read(priv, reg);
  280. if ((data & mask) == value)
  281. return 0;
  282. udelay(10);
  283. }
  284. debug("GT init timeout\n");
  285. return -ETIMEDOUT;
  286. }
  287. static void igd_setup_panel(struct udevice *dev)
  288. {
  289. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  290. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  291. u32 reg32;
  292. /* Setup Digital Port Hotplug */
  293. reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
  294. reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
  295. reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
  296. gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
  297. /* Setup Panel Power On Delays */
  298. reg32 = (plat->port_select & 0x3) << 30;
  299. reg32 |= (plat->power_up_delay & 0x1fff) << 16;
  300. reg32 |= (plat->power_backlight_on_delay & 0x1fff);
  301. gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
  302. /* Setup Panel Power Off Delays */
  303. reg32 = (plat->power_down_delay & 0x1fff) << 16;
  304. reg32 |= (plat->power_backlight_off_delay & 0x1fff);
  305. gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
  306. /* Setup Panel Power Cycle Delay */
  307. if (plat->power_cycle_delay) {
  308. reg32 = gtt_read(priv, PCH_PP_DIVISOR);
  309. reg32 &= ~0xff;
  310. reg32 |= plat->power_cycle_delay & 0xff;
  311. gtt_write(priv, PCH_PP_DIVISOR, reg32);
  312. }
  313. /* Enable Backlight if needed */
  314. if (plat->cpu_backlight) {
  315. gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
  316. gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
  317. }
  318. if (plat->pch_backlight) {
  319. gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
  320. gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
  321. }
  322. }
  323. static int igd_cdclk_init_haswell(struct udevice *dev)
  324. {
  325. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  326. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  327. int cdclk = plat->cdclk;
  328. u16 devid;
  329. int gpu_is_ulx = 0;
  330. u32 dpdiv, lpcll;
  331. int ret;
  332. dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
  333. /* Check for ULX GT1 or GT2 */
  334. if (devid == 0x0a0e || devid == 0x0a1e)
  335. gpu_is_ulx = 1;
  336. /* 675MHz is not supported on haswell */
  337. if (cdclk == GT_CDCLK_675)
  338. cdclk = GT_CDCLK_337;
  339. /* If CD clock is fixed or ULT then set to 450MHz */
  340. if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
  341. cdclk = GT_CDCLK_450;
  342. /* 540MHz is not supported on ULX */
  343. if (gpu_is_ulx && cdclk == GT_CDCLK_540)
  344. cdclk = GT_CDCLK_337;
  345. /* 337.5MHz is not supported on non-ULT/ULX */
  346. if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
  347. cdclk = GT_CDCLK_450;
  348. /* Set variables based on CD Clock setting */
  349. switch (cdclk) {
  350. case GT_CDCLK_337:
  351. dpdiv = 169;
  352. lpcll = (1 << 26);
  353. break;
  354. case GT_CDCLK_450:
  355. dpdiv = 225;
  356. lpcll = 0;
  357. break;
  358. case GT_CDCLK_540:
  359. dpdiv = 270;
  360. lpcll = (1 << 26);
  361. break;
  362. default:
  363. ret = -EDOM;
  364. goto err;
  365. }
  366. /* Set LPCLL_CTL CD Clock Frequency Select */
  367. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  368. /* ULX: Inform power controller of selected frequency */
  369. if (gpu_is_ulx) {
  370. if (cdclk == GT_CDCLK_450)
  371. gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
  372. else
  373. gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
  374. gtt_write(priv, 0x13812c, 0x00000000);
  375. gtt_write(priv, 0x138124, 0x80000017);
  376. }
  377. /* Set CPU DP AUX 2X bit clock dividers */
  378. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  379. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  380. return 0;
  381. err:
  382. debug("%s: ret=%d\n", __func__, ret);
  383. return ret;
  384. }
  385. static int igd_cdclk_init_broadwell(struct udevice *dev)
  386. {
  387. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  388. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  389. int cdclk = plat->cdclk;
  390. u32 dpdiv, lpcll, pwctl, cdset;
  391. int ret;
  392. /* Inform power controller of upcoming frequency change */
  393. gtt_write(priv, 0x138128, 0);
  394. gtt_write(priv, 0x13812c, 0);
  395. gtt_write(priv, 0x138124, 0x80000018);
  396. /* Poll GT driver mailbox for run/busy clear */
  397. if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
  398. cdclk = GT_CDCLK_450;
  399. if (gtt_read(priv, 0x42014) & 0x1000000) {
  400. /* If CD clock is fixed then set to 450MHz */
  401. cdclk = GT_CDCLK_450;
  402. } else {
  403. /* Program CD clock to highest supported freq */
  404. if (cpu_is_ult())
  405. cdclk = GT_CDCLK_540;
  406. else
  407. cdclk = GT_CDCLK_675;
  408. }
  409. /* CD clock frequency 675MHz not supported on ULT */
  410. if (cpu_is_ult() && cdclk == GT_CDCLK_675)
  411. cdclk = GT_CDCLK_540;
  412. /* Set variables based on CD Clock setting */
  413. switch (cdclk) {
  414. case GT_CDCLK_337:
  415. cdset = 337;
  416. lpcll = (1 << 27);
  417. pwctl = 2;
  418. dpdiv = 169;
  419. break;
  420. case GT_CDCLK_450:
  421. cdset = 449;
  422. lpcll = 0;
  423. pwctl = 0;
  424. dpdiv = 225;
  425. break;
  426. case GT_CDCLK_540:
  427. cdset = 539;
  428. lpcll = (1 << 26);
  429. pwctl = 1;
  430. dpdiv = 270;
  431. break;
  432. case GT_CDCLK_675:
  433. cdset = 674;
  434. lpcll = (1 << 26) | (1 << 27);
  435. pwctl = 3;
  436. dpdiv = 338;
  437. break;
  438. default:
  439. ret = -EDOM;
  440. goto err;
  441. }
  442. debug("%s: frequency = %d\n", __func__, cdclk);
  443. /* Set LPCLL_CTL CD Clock Frequency Select */
  444. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  445. /* Inform power controller of selected frequency */
  446. gtt_write(priv, 0x138128, pwctl);
  447. gtt_write(priv, 0x13812c, 0);
  448. gtt_write(priv, 0x138124, 0x80000017);
  449. /* Program CD Clock Frequency */
  450. gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
  451. /* Set CPU DP AUX 2X bit clock dividers */
  452. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  453. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  454. return 0;
  455. err:
  456. debug("%s: ret=%d\n", __func__, ret);
  457. return ret;
  458. }
  459. u8 systemagent_revision(struct udevice *bus)
  460. {
  461. ulong val;
  462. pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
  463. PCI_SIZE_32);
  464. return val;
  465. }
  466. static int igd_pre_init(struct udevice *dev, bool is_broadwell)
  467. {
  468. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  469. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  470. u32 rp1_gfx_freq;
  471. int ret;
  472. mdelay(plat->pre_graphics_delay);
  473. /* Early init steps */
  474. if (is_broadwell) {
  475. ret = broadwell_early_init(dev);
  476. if (ret)
  477. goto err;
  478. /* Set GFXPAUSE based on stepping */
  479. if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
  480. systemagent_revision(pci_get_controller(dev)) <= 9) {
  481. gtt_write(priv, 0xa000, 0x300ff);
  482. } else {
  483. gtt_write(priv, 0xa000, 0x30020);
  484. }
  485. } else {
  486. ret = haswell_early_init(dev);
  487. if (ret)
  488. goto err;
  489. }
  490. /* Set RP1 graphics frequency */
  491. rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
  492. gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
  493. /* Post VBIOS panel setup */
  494. igd_setup_panel(dev);
  495. return 0;
  496. err:
  497. debug("%s: ret=%d\n", __func__, ret);
  498. return ret;
  499. }
  500. static int igd_post_init(struct udevice *dev, bool is_broadwell)
  501. {
  502. int ret;
  503. /* Late init steps */
  504. if (is_broadwell) {
  505. ret = igd_cdclk_init_broadwell(dev);
  506. if (ret)
  507. return ret;
  508. ret = broadwell_late_init(dev);
  509. if (ret)
  510. return ret;
  511. } else {
  512. igd_cdclk_init_haswell(dev);
  513. ret = haswell_late_init(dev);
  514. if (ret)
  515. return ret;
  516. }
  517. return 0;
  518. }
  519. static int broadwell_igd_int15_handler(void)
  520. {
  521. int res = 0;
  522. debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
  523. switch (M.x86.R_AX) {
  524. case 0x5f35:
  525. /*
  526. * Boot Display Device Hook:
  527. * bit 0 = CRT
  528. * bit 1 = TV (eDP)
  529. * bit 2 = EFP
  530. * bit 3 = LFP
  531. * bit 4 = CRT2
  532. * bit 5 = TV2 (eDP)
  533. * bit 6 = EFP2
  534. * bit 7 = LFP2
  535. */
  536. M.x86.R_AX = 0x005f;
  537. M.x86.R_CX = 0x0000; /* Use video bios default */
  538. res = 1;
  539. break;
  540. default:
  541. debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
  542. break;
  543. }
  544. return res;
  545. }
  546. static int broadwell_igd_probe(struct udevice *dev)
  547. {
  548. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  549. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  550. bool is_broadwell;
  551. int ret;
  552. if (!ll_boot_init()) {
  553. /*
  554. * If we are running from EFI or coreboot, this driver can't
  555. * work.
  556. */
  557. printf("Not available (previous bootloader prevents it)\n");
  558. return -EPERM;
  559. }
  560. is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
  561. bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
  562. debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
  563. ret = igd_pre_init(dev, is_broadwell);
  564. if (!ret) {
  565. ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
  566. if (ret)
  567. debug("failed to run video BIOS: %d\n", ret);
  568. }
  569. if (!ret)
  570. ret = igd_post_init(dev, is_broadwell);
  571. bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
  572. if (ret)
  573. return ret;
  574. /* Use write-combining for the graphics memory, 256MB */
  575. ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20);
  576. if (!ret)
  577. ret = mtrr_commit(true);
  578. if (ret && ret != -ENOSYS) {
  579. printf("Failed to add MTRR: Display will be slow (err %d)\n",
  580. ret);
  581. }
  582. debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
  583. plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
  584. return 0;
  585. }
  586. static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
  587. {
  588. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  589. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  590. int node = dev_of_offset(dev);
  591. const void *blob = gd->fdt_blob;
  592. if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
  593. plat->dp_hotplug,
  594. ARRAY_SIZE(plat->dp_hotplug)))
  595. return -EINVAL;
  596. plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
  597. plat->power_cycle_delay = fdtdec_get_int(blob, node,
  598. "intel,power-cycle-delay", 0);
  599. plat->power_up_delay = fdtdec_get_int(blob, node,
  600. "intel,power-up-delay", 0);
  601. plat->power_down_delay = fdtdec_get_int(blob, node,
  602. "intel,power-down-delay", 0);
  603. plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
  604. "intel,power-backlight-on-delay", 0);
  605. plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
  606. "intel,power-backlight-off-delay", 0);
  607. plat->cpu_backlight = fdtdec_get_int(blob, node,
  608. "intel,cpu-backlight", 0);
  609. plat->pch_backlight = fdtdec_get_int(blob, node,
  610. "intel,pch-backlight", 0);
  611. plat->pre_graphics_delay = fdtdec_get_int(blob, node,
  612. "intel,pre-graphics-delay", 0);
  613. priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
  614. debug("%s: regs at %p\n", __func__, priv->regs);
  615. debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
  616. plat->dp_hotplug[2]);
  617. debug("port_select = %d\n", plat->port_select);
  618. debug("power_up_delay = %d\n", plat->power_up_delay);
  619. debug("power_backlight_on_delay = %d\n",
  620. plat->power_backlight_on_delay);
  621. debug("power_down_delay = %d\n", plat->power_down_delay);
  622. debug("power_backlight_off_delay = %d\n",
  623. plat->power_backlight_off_delay);
  624. debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
  625. debug("cpu_backlight = %x\n", plat->cpu_backlight);
  626. debug("pch_backlight = %x\n", plat->pch_backlight);
  627. debug("cdclk = %d\n", plat->cdclk);
  628. debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
  629. return 0;
  630. }
  631. static const struct video_ops broadwell_igd_ops = {
  632. };
  633. static const struct udevice_id broadwell_igd_ids[] = {
  634. { .compatible = "intel,broadwell-igd" },
  635. { }
  636. };
  637. U_BOOT_DRIVER(broadwell_igd) = {
  638. .name = "broadwell_igd",
  639. .id = UCLASS_VIDEO,
  640. .of_match = broadwell_igd_ids,
  641. .ops = &broadwell_igd_ops,
  642. .ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
  643. .probe = broadwell_igd_probe,
  644. .priv_auto_alloc_size = sizeof(struct broadwell_igd_priv),
  645. .platdata_auto_alloc_size = sizeof(struct broadwell_igd_plat),
  646. };