mxc_spi.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <malloc.h>
  8. #include <spi.h>
  9. #include <linux/errno.h>
  10. #include <asm/io.h>
  11. #include <asm/gpio.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/mach-imx/spi.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #ifdef CONFIG_MX27
  17. /* i.MX27 has a completely wrong register layout and register definitions in the
  18. * datasheet, the correct one is in the Freescale's Linux driver */
  19. #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
  20. "See linux mxc_spi driver from Freescale for details."
  21. #endif
  22. __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
  23. {
  24. return -1;
  25. }
  26. #define OUT MXC_GPIO_DIRECTION_OUT
  27. #define reg_read readl
  28. #define reg_write(a, v) writel(v, a)
  29. #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
  30. #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
  31. #endif
  32. #define MAX_CS_COUNT 4
  33. struct mxc_spi_slave {
  34. struct spi_slave slave;
  35. unsigned long base;
  36. u32 ctrl_reg;
  37. #if defined(MXC_ECSPI)
  38. u32 cfg_reg;
  39. #endif
  40. int gpio;
  41. int ss_pol;
  42. unsigned int max_hz;
  43. unsigned int mode;
  44. struct gpio_desc ss;
  45. struct gpio_desc cs_gpios[MAX_CS_COUNT];
  46. struct udevice *dev;
  47. };
  48. static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
  49. {
  50. return container_of(slave, struct mxc_spi_slave, slave);
  51. }
  52. static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
  53. {
  54. #if defined(CONFIG_DM_SPI)
  55. struct udevice *dev = mxcs->dev;
  56. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  57. u32 cs = slave_plat->cs;
  58. if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
  59. return;
  60. dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
  61. #else
  62. if (mxcs->gpio > 0)
  63. gpio_set_value(mxcs->gpio, mxcs->ss_pol);
  64. #endif
  65. }
  66. static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
  67. {
  68. #if defined(CONFIG_DM_SPI)
  69. struct udevice *dev = mxcs->dev;
  70. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  71. u32 cs = slave_plat->cs;
  72. if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
  73. return;
  74. dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
  75. #else
  76. if (mxcs->gpio > 0)
  77. gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
  78. #endif
  79. }
  80. u32 get_cspi_div(u32 div)
  81. {
  82. int i;
  83. for (i = 0; i < 8; i++) {
  84. if (div <= (4 << i))
  85. return i;
  86. }
  87. return i;
  88. }
  89. #ifdef MXC_CSPI
  90. static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
  91. {
  92. unsigned int ctrl_reg;
  93. u32 clk_src;
  94. u32 div;
  95. unsigned int max_hz = mxcs->max_hz;
  96. unsigned int mode = mxcs->mode;
  97. clk_src = mxc_get_clock(MXC_CSPI_CLK);
  98. div = DIV_ROUND_UP(clk_src, max_hz);
  99. div = get_cspi_div(div);
  100. debug("clk %d Hz, div %d, real clk %d Hz\n",
  101. max_hz, div, clk_src / (4 << div));
  102. ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
  103. MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
  104. MXC_CSPICTRL_DATARATE(div) |
  105. MXC_CSPICTRL_EN |
  106. #ifdef CONFIG_MX35
  107. MXC_CSPICTRL_SSCTL |
  108. #endif
  109. MXC_CSPICTRL_MODE;
  110. if (mode & SPI_CPHA)
  111. ctrl_reg |= MXC_CSPICTRL_PHA;
  112. if (mode & SPI_CPOL)
  113. ctrl_reg |= MXC_CSPICTRL_POL;
  114. if (mode & SPI_CS_HIGH)
  115. ctrl_reg |= MXC_CSPICTRL_SSPOL;
  116. mxcs->ctrl_reg = ctrl_reg;
  117. return 0;
  118. }
  119. #endif
  120. #ifdef MXC_ECSPI
  121. static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
  122. {
  123. u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
  124. s32 reg_ctrl, reg_config;
  125. u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
  126. u32 pre_div = 0, post_div = 0;
  127. struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
  128. unsigned int max_hz = mxcs->max_hz;
  129. unsigned int mode = mxcs->mode;
  130. /*
  131. * Reset SPI and set all CSs to master mode, if toggling
  132. * between slave and master mode we might see a glitch
  133. * on the clock line
  134. */
  135. reg_ctrl = MXC_CSPICTRL_MODE_MASK;
  136. reg_write(&regs->ctrl, reg_ctrl);
  137. reg_ctrl |= MXC_CSPICTRL_EN;
  138. reg_write(&regs->ctrl, reg_ctrl);
  139. if (clk_src > max_hz) {
  140. pre_div = (clk_src - 1) / max_hz;
  141. /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
  142. post_div = fls(pre_div);
  143. if (post_div > 4) {
  144. post_div -= 4;
  145. if (post_div >= 16) {
  146. printf("Error: no divider for the freq: %d\n",
  147. max_hz);
  148. return -1;
  149. }
  150. pre_div >>= post_div;
  151. } else {
  152. post_div = 0;
  153. }
  154. }
  155. debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
  156. reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
  157. MXC_CSPICTRL_SELCHAN(cs);
  158. reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
  159. MXC_CSPICTRL_PREDIV(pre_div);
  160. reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
  161. MXC_CSPICTRL_POSTDIV(post_div);
  162. if (mode & SPI_CS_HIGH)
  163. ss_pol = 1;
  164. if (mode & SPI_CPOL) {
  165. sclkpol = 1;
  166. sclkctl = 1;
  167. }
  168. if (mode & SPI_CPHA)
  169. sclkpha = 1;
  170. reg_config = reg_read(&regs->cfg);
  171. /*
  172. * Configuration register setup
  173. * The MX51 supports different setup for each SS
  174. */
  175. reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
  176. (ss_pol << (cs + MXC_CSPICON_SSPOL));
  177. reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
  178. (sclkpol << (cs + MXC_CSPICON_POL));
  179. reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
  180. (sclkctl << (cs + MXC_CSPICON_CTL));
  181. reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
  182. (sclkpha << (cs + MXC_CSPICON_PHA));
  183. debug("reg_ctrl = 0x%x\n", reg_ctrl);
  184. reg_write(&regs->ctrl, reg_ctrl);
  185. debug("reg_config = 0x%x\n", reg_config);
  186. reg_write(&regs->cfg, reg_config);
  187. /* save config register and control register */
  188. mxcs->ctrl_reg = reg_ctrl;
  189. mxcs->cfg_reg = reg_config;
  190. /* clear interrupt reg */
  191. reg_write(&regs->intr, 0);
  192. reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
  193. return 0;
  194. }
  195. #endif
  196. int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
  197. const u8 *dout, u8 *din, unsigned long flags)
  198. {
  199. int nbytes = DIV_ROUND_UP(bitlen, 8);
  200. u32 data, cnt, i;
  201. struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
  202. u32 ts;
  203. int status;
  204. debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
  205. __func__, bitlen, (ulong)dout, (ulong)din);
  206. mxcs->ctrl_reg = (mxcs->ctrl_reg &
  207. ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
  208. MXC_CSPICTRL_BITCOUNT(bitlen - 1);
  209. reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
  210. #ifdef MXC_ECSPI
  211. reg_write(&regs->cfg, mxcs->cfg_reg);
  212. #endif
  213. /* Clear interrupt register */
  214. reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
  215. /*
  216. * The SPI controller works only with words,
  217. * check if less than a word is sent.
  218. * Access to the FIFO is only 32 bit
  219. */
  220. if (bitlen % 32) {
  221. data = 0;
  222. cnt = (bitlen % 32) / 8;
  223. if (dout) {
  224. for (i = 0; i < cnt; i++) {
  225. data = (data << 8) | (*dout++ & 0xFF);
  226. }
  227. }
  228. debug("Sending SPI 0x%x\n", data);
  229. reg_write(&regs->txdata, data);
  230. nbytes -= cnt;
  231. }
  232. data = 0;
  233. while (nbytes > 0) {
  234. data = 0;
  235. if (dout) {
  236. /* Buffer is not 32-bit aligned */
  237. if ((unsigned long)dout & 0x03) {
  238. data = 0;
  239. for (i = 0; i < 4; i++)
  240. data = (data << 8) | (*dout++ & 0xFF);
  241. } else {
  242. data = *(u32 *)dout;
  243. data = cpu_to_be32(data);
  244. dout += 4;
  245. }
  246. }
  247. debug("Sending SPI 0x%x\n", data);
  248. reg_write(&regs->txdata, data);
  249. nbytes -= 4;
  250. }
  251. /* FIFO is written, now starts the transfer setting the XCH bit */
  252. reg_write(&regs->ctrl, mxcs->ctrl_reg |
  253. MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
  254. ts = get_timer(0);
  255. status = reg_read(&regs->stat);
  256. /* Wait until the TC (Transfer completed) bit is set */
  257. while ((status & MXC_CSPICTRL_TC) == 0) {
  258. if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
  259. printf("spi_xchg_single: Timeout!\n");
  260. return -1;
  261. }
  262. status = reg_read(&regs->stat);
  263. }
  264. /* Transfer completed, clear any pending request */
  265. reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
  266. nbytes = DIV_ROUND_UP(bitlen, 8);
  267. cnt = nbytes % 32;
  268. if (bitlen % 32) {
  269. data = reg_read(&regs->rxdata);
  270. cnt = (bitlen % 32) / 8;
  271. data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
  272. debug("SPI Rx unaligned: 0x%x\n", data);
  273. if (din) {
  274. memcpy(din, &data, cnt);
  275. din += cnt;
  276. }
  277. nbytes -= cnt;
  278. }
  279. while (nbytes > 0) {
  280. u32 tmp;
  281. tmp = reg_read(&regs->rxdata);
  282. data = cpu_to_be32(tmp);
  283. debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
  284. cnt = min_t(u32, nbytes, sizeof(data));
  285. if (din) {
  286. memcpy(din, &data, cnt);
  287. din += cnt;
  288. }
  289. nbytes -= cnt;
  290. }
  291. return 0;
  292. }
  293. static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
  294. unsigned int bitlen, const void *dout,
  295. void *din, unsigned long flags)
  296. {
  297. int n_bytes = DIV_ROUND_UP(bitlen, 8);
  298. int n_bits;
  299. int ret;
  300. u32 blk_size;
  301. u8 *p_outbuf = (u8 *)dout;
  302. u8 *p_inbuf = (u8 *)din;
  303. if (!mxcs)
  304. return -EINVAL;
  305. if (flags & SPI_XFER_BEGIN)
  306. mxc_spi_cs_activate(mxcs);
  307. while (n_bytes > 0) {
  308. if (n_bytes < MAX_SPI_BYTES)
  309. blk_size = n_bytes;
  310. else
  311. blk_size = MAX_SPI_BYTES;
  312. n_bits = blk_size * 8;
  313. ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
  314. if (ret)
  315. return ret;
  316. if (dout)
  317. p_outbuf += blk_size;
  318. if (din)
  319. p_inbuf += blk_size;
  320. n_bytes -= blk_size;
  321. }
  322. if (flags & SPI_XFER_END) {
  323. mxc_spi_cs_deactivate(mxcs);
  324. }
  325. return 0;
  326. }
  327. static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
  328. {
  329. struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
  330. int ret;
  331. reg_write(&regs->rxdata, 1);
  332. udelay(1);
  333. ret = spi_cfg_mxc(mxcs, cs);
  334. if (ret) {
  335. printf("mxc_spi: cannot setup SPI controller\n");
  336. return ret;
  337. }
  338. reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
  339. reg_write(&regs->intr, 0);
  340. return 0;
  341. }
  342. #ifndef CONFIG_DM_SPI
  343. int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
  344. void *din, unsigned long flags)
  345. {
  346. struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  347. return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
  348. }
  349. /*
  350. * Some SPI devices require active chip-select over multiple
  351. * transactions, we achieve this using a GPIO. Still, the SPI
  352. * controller has to be configured to use one of its own chipselects.
  353. * To use this feature you have to implement board_spi_cs_gpio() to assign
  354. * a gpio value for each cs (-1 if cs doesn't need to use gpio).
  355. * You must use some unused on this SPI controller cs between 0 and 3.
  356. */
  357. static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
  358. unsigned int bus, unsigned int cs)
  359. {
  360. int ret;
  361. mxcs->gpio = board_spi_cs_gpio(bus, cs);
  362. if (mxcs->gpio == -1)
  363. return 0;
  364. gpio_request(mxcs->gpio, "spi-cs");
  365. ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
  366. if (ret) {
  367. printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
  368. return -EINVAL;
  369. }
  370. return 0;
  371. }
  372. static unsigned long spi_bases[] = {
  373. MXC_SPI_BASE_ADDRESSES
  374. };
  375. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  376. unsigned int max_hz, unsigned int mode)
  377. {
  378. struct mxc_spi_slave *mxcs;
  379. int ret;
  380. if (bus >= ARRAY_SIZE(spi_bases))
  381. return NULL;
  382. if (max_hz == 0) {
  383. printf("Error: desired clock is 0\n");
  384. return NULL;
  385. }
  386. mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
  387. if (!mxcs) {
  388. puts("mxc_spi: SPI Slave not allocated !\n");
  389. return NULL;
  390. }
  391. mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
  392. ret = setup_cs_gpio(mxcs, bus, cs);
  393. if (ret < 0) {
  394. free(mxcs);
  395. return NULL;
  396. }
  397. mxcs->base = spi_bases[bus];
  398. mxcs->max_hz = max_hz;
  399. mxcs->mode = mode;
  400. return &mxcs->slave;
  401. }
  402. void spi_free_slave(struct spi_slave *slave)
  403. {
  404. struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  405. free(mxcs);
  406. }
  407. int spi_claim_bus(struct spi_slave *slave)
  408. {
  409. struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  410. return mxc_spi_claim_bus_internal(mxcs, slave->cs);
  411. }
  412. void spi_release_bus(struct spi_slave *slave)
  413. {
  414. /* TODO: Shut the controller down */
  415. }
  416. #else
  417. static int mxc_spi_probe(struct udevice *bus)
  418. {
  419. struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
  420. int node = dev_of_offset(bus);
  421. const void *blob = gd->fdt_blob;
  422. int ret;
  423. int i;
  424. ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
  425. ARRAY_SIZE(mxcs->cs_gpios), 0);
  426. if (ret < 0) {
  427. pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
  428. return ret;
  429. }
  430. for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
  431. if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
  432. continue;
  433. ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
  434. GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
  435. if (ret) {
  436. dev_err(bus, "Setting cs %d error\n", i);
  437. return ret;
  438. }
  439. }
  440. mxcs->base = devfdt_get_addr(bus);
  441. if (mxcs->base == FDT_ADDR_T_NONE)
  442. return -ENODEV;
  443. mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  444. 20000000);
  445. return 0;
  446. }
  447. static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
  448. const void *dout, void *din, unsigned long flags)
  449. {
  450. struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
  451. return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
  452. }
  453. static int mxc_spi_claim_bus(struct udevice *dev)
  454. {
  455. struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
  456. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  457. mxcs->dev = dev;
  458. return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
  459. }
  460. static int mxc_spi_release_bus(struct udevice *dev)
  461. {
  462. return 0;
  463. }
  464. static int mxc_spi_set_speed(struct udevice *bus, uint speed)
  465. {
  466. /* Nothing to do */
  467. return 0;
  468. }
  469. static int mxc_spi_set_mode(struct udevice *bus, uint mode)
  470. {
  471. struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
  472. mxcs->mode = mode;
  473. mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
  474. return 0;
  475. }
  476. static const struct dm_spi_ops mxc_spi_ops = {
  477. .claim_bus = mxc_spi_claim_bus,
  478. .release_bus = mxc_spi_release_bus,
  479. .xfer = mxc_spi_xfer,
  480. .set_speed = mxc_spi_set_speed,
  481. .set_mode = mxc_spi_set_mode,
  482. };
  483. static const struct udevice_id mxc_spi_ids[] = {
  484. { .compatible = "fsl,imx51-ecspi" },
  485. { }
  486. };
  487. U_BOOT_DRIVER(mxc_spi) = {
  488. .name = "mxc_spi",
  489. .id = UCLASS_SPI,
  490. .of_match = mxc_spi_ids,
  491. .ops = &mxc_spi_ops,
  492. .platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
  493. .probe = mxc_spi_probe,
  494. };
  495. #endif