atmel-quadspi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Atmel QSPI Controller
  4. *
  5. * Copyright (C) 2015 Atmel Corporation
  6. * Copyright (C) 2018 Cryptera A/S
  7. *
  8. * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
  9. * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
  10. */
  11. #include <asm/io.h>
  12. #include <clk.h>
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <fdtdec.h>
  17. #include <linux/io.h>
  18. #include <linux/iopoll.h>
  19. #include <linux/ioport.h>
  20. #include <mach/clk.h>
  21. #include <spi.h>
  22. #include <spi-mem.h>
  23. /* QSPI register offsets */
  24. #define QSPI_CR 0x0000 /* Control Register */
  25. #define QSPI_MR 0x0004 /* Mode Register */
  26. #define QSPI_RD 0x0008 /* Receive Data Register */
  27. #define QSPI_TD 0x000c /* Transmit Data Register */
  28. #define QSPI_SR 0x0010 /* Status Register */
  29. #define QSPI_IER 0x0014 /* Interrupt Enable Register */
  30. #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
  31. #define QSPI_IMR 0x001c /* Interrupt Mask Register */
  32. #define QSPI_SCR 0x0020 /* Serial Clock Register */
  33. #define QSPI_IAR 0x0030 /* Instruction Address Register */
  34. #define QSPI_ICR 0x0034 /* Instruction Code Register */
  35. #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
  36. #define QSPI_IFR 0x0038 /* Instruction Frame Register */
  37. #define QSPI_RICR 0x003C /* Read Instruction Code Register */
  38. #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
  39. #define QSPI_SKR 0x0044 /* Scrambling Key Register */
  40. #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
  41. #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
  42. #define QSPI_VERSION 0x00FC /* Version Register */
  43. /* Bitfields in QSPI_CR (Control Register) */
  44. #define QSPI_CR_QSPIEN BIT(0)
  45. #define QSPI_CR_QSPIDIS BIT(1)
  46. #define QSPI_CR_SWRST BIT(7)
  47. #define QSPI_CR_LASTXFER BIT(24)
  48. /* Bitfields in QSPI_MR (Mode Register) */
  49. #define QSPI_MR_SMM BIT(0)
  50. #define QSPI_MR_LLB BIT(1)
  51. #define QSPI_MR_WDRBT BIT(2)
  52. #define QSPI_MR_SMRM BIT(3)
  53. #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
  54. #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
  55. #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
  56. #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
  57. #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
  58. #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
  59. #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
  60. #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
  61. #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
  62. #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
  63. /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
  64. #define QSPI_SR_RDRF BIT(0)
  65. #define QSPI_SR_TDRE BIT(1)
  66. #define QSPI_SR_TXEMPTY BIT(2)
  67. #define QSPI_SR_OVRES BIT(3)
  68. #define QSPI_SR_CSR BIT(8)
  69. #define QSPI_SR_CSS BIT(9)
  70. #define QSPI_SR_INSTRE BIT(10)
  71. #define QSPI_SR_QSPIENS BIT(24)
  72. #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
  73. /* Bitfields in QSPI_SCR (Serial Clock Register) */
  74. #define QSPI_SCR_CPOL BIT(0)
  75. #define QSPI_SCR_CPHA BIT(1)
  76. #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
  77. #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
  78. #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
  79. #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
  80. /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
  81. #define QSPI_ICR_INST_MASK GENMASK(7, 0)
  82. #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
  83. #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
  84. #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
  85. /* Bitfields in QSPI_IFR (Instruction Frame Register) */
  86. #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
  87. #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
  88. #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
  89. #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
  90. #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
  91. #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
  92. #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
  93. #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
  94. #define QSPI_IFR_INSTEN BIT(4)
  95. #define QSPI_IFR_ADDREN BIT(5)
  96. #define QSPI_IFR_OPTEN BIT(6)
  97. #define QSPI_IFR_DATAEN BIT(7)
  98. #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
  99. #define QSPI_IFR_OPTL_1BIT (0 << 8)
  100. #define QSPI_IFR_OPTL_2BIT (1 << 8)
  101. #define QSPI_IFR_OPTL_4BIT (2 << 8)
  102. #define QSPI_IFR_OPTL_8BIT (3 << 8)
  103. #define QSPI_IFR_ADDRL BIT(10)
  104. #define QSPI_IFR_TFRTYP_MEM BIT(12)
  105. #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
  106. #define QSPI_IFR_CRM BIT(14)
  107. #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
  108. #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
  109. #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
  110. /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
  111. #define QSPI_SMR_SCREN BIT(0)
  112. #define QSPI_SMR_RVDIS BIT(1)
  113. /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
  114. #define QSPI_WPMR_WPEN BIT(0)
  115. #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
  116. #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
  117. /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
  118. #define QSPI_WPSR_WPVS BIT(0)
  119. #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
  120. #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
  121. struct atmel_qspi_caps {
  122. bool has_qspick;
  123. bool has_ricr;
  124. };
  125. struct atmel_qspi {
  126. void __iomem *regs;
  127. void __iomem *mem;
  128. const struct atmel_qspi_caps *caps;
  129. ulong bus_clk_rate;
  130. u32 mr;
  131. };
  132. struct atmel_qspi_mode {
  133. u8 cmd_buswidth;
  134. u8 addr_buswidth;
  135. u8 data_buswidth;
  136. u32 config;
  137. };
  138. static const struct atmel_qspi_mode atmel_qspi_modes[] = {
  139. { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
  140. { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
  141. { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
  142. { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
  143. { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
  144. { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
  145. { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
  146. };
  147. static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
  148. const struct atmel_qspi_mode *mode)
  149. {
  150. if (op->cmd.buswidth != mode->cmd_buswidth)
  151. return false;
  152. if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
  153. return false;
  154. if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
  155. return false;
  156. return true;
  157. }
  158. static int atmel_qspi_find_mode(const struct spi_mem_op *op)
  159. {
  160. u32 i;
  161. for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
  162. if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
  163. return i;
  164. return -ENOTSUPP;
  165. }
  166. static bool atmel_qspi_supports_op(struct spi_slave *slave,
  167. const struct spi_mem_op *op)
  168. {
  169. if (atmel_qspi_find_mode(op) < 0)
  170. return false;
  171. /* special case not supported by hardware */
  172. if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
  173. op->dummy.nbytes == 0)
  174. return false;
  175. return true;
  176. }
  177. static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
  178. const struct spi_mem_op *op, u32 *offset)
  179. {
  180. u32 iar, icr, ifr;
  181. u32 dummy_cycles = 0;
  182. int mode;
  183. iar = 0;
  184. icr = QSPI_ICR_INST(op->cmd.opcode);
  185. ifr = QSPI_IFR_INSTEN;
  186. mode = atmel_qspi_find_mode(op);
  187. if (mode < 0)
  188. return mode;
  189. ifr |= atmel_qspi_modes[mode].config;
  190. if (op->dummy.buswidth && op->dummy.nbytes)
  191. dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
  192. /*
  193. * The controller allows 24 and 32-bit addressing while NAND-flash
  194. * requires 16-bit long. Handling 8-bit long addresses is done using
  195. * the option field. For the 16-bit addresses, the workaround depends
  196. * of the number of requested dummy bits. If there are 8 or more dummy
  197. * cycles, the address is shifted and sent with the first dummy byte.
  198. * Otherwise opcode is disabled and the first byte of the address
  199. * contains the command opcode (works only if the opcode and address
  200. * use the same buswidth). The limitation is when the 16-bit address is
  201. * used without enough dummy cycles and the opcode is using a different
  202. * buswidth than the address.
  203. */
  204. if (op->addr.buswidth) {
  205. switch (op->addr.nbytes) {
  206. case 0:
  207. break;
  208. case 1:
  209. ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
  210. icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
  211. break;
  212. case 2:
  213. if (dummy_cycles < 8 / op->addr.buswidth) {
  214. ifr &= ~QSPI_IFR_INSTEN;
  215. ifr |= QSPI_IFR_ADDREN;
  216. iar = (op->cmd.opcode << 16) |
  217. (op->addr.val & 0xffff);
  218. } else {
  219. ifr |= QSPI_IFR_ADDREN;
  220. iar = (op->addr.val << 8) & 0xffffff;
  221. dummy_cycles -= 8 / op->addr.buswidth;
  222. }
  223. break;
  224. case 3:
  225. ifr |= QSPI_IFR_ADDREN;
  226. iar = op->addr.val & 0xffffff;
  227. break;
  228. case 4:
  229. ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
  230. iar = op->addr.val & 0x7ffffff;
  231. break;
  232. default:
  233. return -ENOTSUPP;
  234. }
  235. }
  236. /* offset of the data access in the QSPI memory space */
  237. *offset = iar;
  238. /* Set number of dummy cycles */
  239. if (dummy_cycles)
  240. ifr |= QSPI_IFR_NBDUM(dummy_cycles);
  241. /* Set data enable */
  242. if (op->data.nbytes)
  243. ifr |= QSPI_IFR_DATAEN;
  244. /*
  245. * If the QSPI controller is set in regular SPI mode, set it in
  246. * Serial Memory Mode (SMM).
  247. */
  248. if (aq->mr != QSPI_MR_SMM) {
  249. writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
  250. aq->mr = QSPI_MR_SMM;
  251. }
  252. /* Clear pending interrupts */
  253. (void)readl(aq->regs + QSPI_SR);
  254. if (aq->caps->has_ricr) {
  255. if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  256. ifr |= QSPI_IFR_APBTFRTYP_READ;
  257. /* Set QSPI Instruction Frame registers */
  258. writel(iar, aq->regs + QSPI_IAR);
  259. if (op->data.dir == SPI_MEM_DATA_IN)
  260. writel(icr, aq->regs + QSPI_RICR);
  261. else
  262. writel(icr, aq->regs + QSPI_WICR);
  263. writel(ifr, aq->regs + QSPI_IFR);
  264. } else {
  265. if (op->data.dir == SPI_MEM_DATA_OUT)
  266. ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
  267. /* Set QSPI Instruction Frame registers */
  268. writel(iar, aq->regs + QSPI_IAR);
  269. writel(icr, aq->regs + QSPI_ICR);
  270. writel(ifr, aq->regs + QSPI_IFR);
  271. }
  272. return 0;
  273. }
  274. static int atmel_qspi_exec_op(struct spi_slave *slave,
  275. const struct spi_mem_op *op)
  276. {
  277. struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
  278. u32 sr, imr, offset;
  279. int err;
  280. err = atmel_qspi_set_cfg(aq, op, &offset);
  281. if (err)
  282. return err;
  283. /* Skip to the final steps if there is no data */
  284. if (op->data.nbytes) {
  285. /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
  286. (void)readl(aq->regs + QSPI_IFR);
  287. /* Send/Receive data */
  288. if (op->data.dir == SPI_MEM_DATA_IN)
  289. memcpy_fromio(op->data.buf.in, aq->mem + offset,
  290. op->data.nbytes);
  291. else
  292. memcpy_toio(aq->mem + offset, op->data.buf.out,
  293. op->data.nbytes);
  294. /* Release the chip-select */
  295. writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
  296. }
  297. /* Poll INSTruction End and Chip Select Rise flags. */
  298. imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
  299. return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
  300. 1000000);
  301. }
  302. static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
  303. {
  304. struct atmel_qspi *aq = dev_get_priv(bus);
  305. u32 scr, scbr, mask, new_value;
  306. /* Compute the QSPI baudrate */
  307. scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
  308. if (scbr > 0)
  309. scbr--;
  310. new_value = QSPI_SCR_SCBR(scbr);
  311. mask = QSPI_SCR_SCBR_MASK;
  312. scr = readl(aq->regs + QSPI_SCR);
  313. if ((scr & mask) == new_value)
  314. return 0;
  315. scr = (scr & ~mask) | new_value;
  316. writel(scr, aq->regs + QSPI_SCR);
  317. return 0;
  318. }
  319. static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
  320. {
  321. struct atmel_qspi *aq = dev_get_priv(bus);
  322. u32 scr, mask, new_value = 0;
  323. if (mode & SPI_CPOL)
  324. new_value = QSPI_SCR_CPOL;
  325. if (mode & SPI_CPHA)
  326. new_value = QSPI_SCR_CPHA;
  327. mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
  328. scr = readl(aq->regs + QSPI_SCR);
  329. if ((scr & mask) == new_value)
  330. return 0;
  331. scr = (scr & ~mask) | new_value;
  332. writel(scr, aq->regs + QSPI_SCR);
  333. return 0;
  334. }
  335. static int atmel_qspi_enable_clk(struct udevice *dev)
  336. {
  337. struct atmel_qspi *aq = dev_get_priv(dev);
  338. struct clk pclk, qspick;
  339. int ret;
  340. ret = clk_get_by_name(dev, "pclk", &pclk);
  341. if (ret)
  342. ret = clk_get_by_index(dev, 0, &pclk);
  343. if (ret) {
  344. dev_err(dev, "Missing QSPI peripheral clock\n");
  345. return ret;
  346. }
  347. ret = clk_enable(&pclk);
  348. if (ret) {
  349. dev_err(dev, "Failed to enable QSPI peripheral clock\n");
  350. goto free_pclk;
  351. }
  352. if (aq->caps->has_qspick) {
  353. /* Get the QSPI system clock */
  354. ret = clk_get_by_name(dev, "qspick", &qspick);
  355. if (ret) {
  356. dev_err(dev, "Missing QSPI peripheral clock\n");
  357. goto free_pclk;
  358. }
  359. ret = clk_enable(&qspick);
  360. if (ret)
  361. dev_err(dev, "Failed to enable QSPI system clock\n");
  362. clk_free(&qspick);
  363. }
  364. aq->bus_clk_rate = clk_get_rate(&pclk);
  365. if (!aq->bus_clk_rate)
  366. ret = -EINVAL;
  367. free_pclk:
  368. clk_free(&pclk);
  369. return ret;
  370. }
  371. static void atmel_qspi_init(struct atmel_qspi *aq)
  372. {
  373. /* Reset the QSPI controller */
  374. writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
  375. /* Set the QSPI controller by default in Serial Memory Mode */
  376. writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
  377. aq->mr = QSPI_MR_SMM;
  378. /* Enable the QSPI controller */
  379. writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
  380. }
  381. static int atmel_qspi_probe(struct udevice *dev)
  382. {
  383. struct atmel_qspi *aq = dev_get_priv(dev);
  384. struct resource res;
  385. int ret;
  386. aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
  387. if (!aq->caps) {
  388. dev_err(dev, "Could not retrieve QSPI caps\n");
  389. return -EINVAL;
  390. };
  391. /* Map the registers */
  392. ret = dev_read_resource_byname(dev, "qspi_base", &res);
  393. if (ret) {
  394. dev_err(dev, "missing registers\n");
  395. return ret;
  396. }
  397. aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
  398. if (IS_ERR(aq->regs))
  399. return PTR_ERR(aq->regs);
  400. /* Map the AHB memory */
  401. ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
  402. if (ret) {
  403. dev_err(dev, "missing AHB memory\n");
  404. return ret;
  405. }
  406. aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
  407. if (IS_ERR(aq->mem))
  408. return PTR_ERR(aq->mem);
  409. ret = atmel_qspi_enable_clk(dev);
  410. if (ret)
  411. return ret;
  412. atmel_qspi_init(aq);
  413. return 0;
  414. }
  415. static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
  416. .supports_op = atmel_qspi_supports_op,
  417. .exec_op = atmel_qspi_exec_op,
  418. };
  419. static const struct dm_spi_ops atmel_qspi_ops = {
  420. .set_speed = atmel_qspi_set_speed,
  421. .set_mode = atmel_qspi_set_mode,
  422. .mem_ops = &atmel_qspi_mem_ops,
  423. };
  424. static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
  425. static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
  426. .has_qspick = true,
  427. .has_ricr = true,
  428. };
  429. static const struct udevice_id atmel_qspi_ids[] = {
  430. {
  431. .compatible = "atmel,sama5d2-qspi",
  432. .data = (ulong)&atmel_sama5d2_qspi_caps,
  433. },
  434. {
  435. .compatible = "microchip,sam9x60-qspi",
  436. .data = (ulong)&atmel_sam9x60_qspi_caps,
  437. },
  438. { /* sentinel */ }
  439. };
  440. U_BOOT_DRIVER(atmel_qspi) = {
  441. .name = "atmel_qspi",
  442. .id = UCLASS_SPI,
  443. .of_match = atmel_qspi_ids,
  444. .ops = &atmel_qspi_ops,
  445. .priv_auto_alloc_size = sizeof(struct atmel_qspi),
  446. .probe = atmel_qspi_probe,
  447. };