tmio-common.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <cpu_func.h>
  9. #include <fdtdec.h>
  10. #include <mmc.h>
  11. #include <dm.h>
  12. #include <dm/pinctrl.h>
  13. #include <linux/compat.h>
  14. #include <linux/dma-direction.h>
  15. #include <linux/io.h>
  16. #include <linux/sizes.h>
  17. #include <power/regulator.h>
  18. #include <asm/unaligned.h>
  19. #include "tmio-common.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
  22. {
  23. return readq(priv->regbase + (reg << 1));
  24. }
  25. static void tmio_sd_writeq(struct tmio_sd_priv *priv,
  26. u64 val, unsigned int reg)
  27. {
  28. writeq(val, priv->regbase + (reg << 1));
  29. }
  30. static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
  31. {
  32. return readw(priv->regbase + (reg >> 1));
  33. }
  34. static void tmio_sd_writew(struct tmio_sd_priv *priv,
  35. u16 val, unsigned int reg)
  36. {
  37. writew(val, priv->regbase + (reg >> 1));
  38. }
  39. u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
  40. {
  41. u32 val;
  42. if (priv->caps & TMIO_SD_CAP_64BIT)
  43. return readl(priv->regbase + (reg << 1));
  44. else if (priv->caps & TMIO_SD_CAP_16BIT) {
  45. val = readw(priv->regbase + (reg >> 1)) & 0xffff;
  46. if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
  47. (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
  48. val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
  49. }
  50. return val;
  51. } else
  52. return readl(priv->regbase + reg);
  53. }
  54. void tmio_sd_writel(struct tmio_sd_priv *priv,
  55. u32 val, unsigned int reg)
  56. {
  57. if (priv->caps & TMIO_SD_CAP_64BIT)
  58. writel(val, priv->regbase + (reg << 1));
  59. else if (priv->caps & TMIO_SD_CAP_16BIT) {
  60. writew(val & 0xffff, priv->regbase + (reg >> 1));
  61. if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
  62. reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
  63. reg == TMIO_SD_ARG)
  64. writew(val >> 16, priv->regbase + (reg >> 1) + 2);
  65. } else
  66. writel(val, priv->regbase + reg);
  67. }
  68. static dma_addr_t __dma_map_single(void *ptr, size_t size,
  69. enum dma_data_direction dir)
  70. {
  71. unsigned long addr = (unsigned long)ptr;
  72. if (dir == DMA_FROM_DEVICE)
  73. invalidate_dcache_range(addr, addr + size);
  74. else
  75. flush_dcache_range(addr, addr + size);
  76. return addr;
  77. }
  78. static void __dma_unmap_single(dma_addr_t addr, size_t size,
  79. enum dma_data_direction dir)
  80. {
  81. if (dir != DMA_TO_DEVICE)
  82. invalidate_dcache_range(addr, addr + size);
  83. }
  84. static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
  85. {
  86. struct tmio_sd_priv *priv = dev_get_priv(dev);
  87. u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
  88. if (info2 & TMIO_SD_INFO2_ERR_RTO) {
  89. /*
  90. * TIMEOUT must be returned for unsupported command. Do not
  91. * display error log since this might be a part of sequence to
  92. * distinguish between SD and MMC.
  93. */
  94. return -ETIMEDOUT;
  95. }
  96. if (info2 & TMIO_SD_INFO2_ERR_TO) {
  97. dev_err(dev, "timeout error\n");
  98. return -ETIMEDOUT;
  99. }
  100. if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
  101. TMIO_SD_INFO2_ERR_IDX)) {
  102. if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
  103. (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
  104. dev_err(dev, "communication out of sync\n");
  105. return -EILSEQ;
  106. }
  107. if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
  108. TMIO_SD_INFO2_ERR_ILW)) {
  109. dev_err(dev, "illegal access\n");
  110. return -EIO;
  111. }
  112. return 0;
  113. }
  114. static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
  115. unsigned int reg, u32 flag)
  116. {
  117. struct tmio_sd_priv *priv = dev_get_priv(dev);
  118. long wait = 1000000;
  119. int ret;
  120. while (!(tmio_sd_readl(priv, reg) & flag)) {
  121. if (wait-- < 0) {
  122. dev_err(dev, "timeout\n");
  123. return -ETIMEDOUT;
  124. }
  125. ret = tmio_sd_check_error(dev, cmd);
  126. if (ret)
  127. return ret;
  128. udelay(1);
  129. }
  130. return 0;
  131. }
  132. #define tmio_pio_read_fifo(__width, __suffix) \
  133. static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
  134. char *pbuf, uint blksz) \
  135. { \
  136. u##__width *buf = (u##__width *)pbuf; \
  137. int i; \
  138. \
  139. if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
  140. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  141. *buf++ = tmio_sd_read##__suffix(priv, \
  142. TMIO_SD_BUF); \
  143. } \
  144. } else { \
  145. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  146. u##__width data; \
  147. data = tmio_sd_read##__suffix(priv, \
  148. TMIO_SD_BUF); \
  149. put_unaligned(data, buf++); \
  150. } \
  151. } \
  152. }
  153. tmio_pio_read_fifo(64, q)
  154. tmio_pio_read_fifo(32, l)
  155. tmio_pio_read_fifo(16, w)
  156. static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
  157. char *pbuf, uint blocksize)
  158. {
  159. struct tmio_sd_priv *priv = dev_get_priv(dev);
  160. int ret;
  161. /* wait until the buffer is filled with data */
  162. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  163. TMIO_SD_INFO2_BRE);
  164. if (ret)
  165. return ret;
  166. /*
  167. * Clear the status flag _before_ read the buffer out because
  168. * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
  169. */
  170. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  171. if (priv->caps & TMIO_SD_CAP_64BIT)
  172. tmio_pio_read_fifo_64(priv, pbuf, blocksize);
  173. else if (priv->caps & TMIO_SD_CAP_16BIT)
  174. tmio_pio_read_fifo_16(priv, pbuf, blocksize);
  175. else
  176. tmio_pio_read_fifo_32(priv, pbuf, blocksize);
  177. return 0;
  178. }
  179. #define tmio_pio_write_fifo(__width, __suffix) \
  180. static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
  181. const char *pbuf, uint blksz)\
  182. { \
  183. const u##__width *buf = (const u##__width *)pbuf; \
  184. int i; \
  185. \
  186. if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
  187. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  188. tmio_sd_write##__suffix(priv, *buf++, \
  189. TMIO_SD_BUF); \
  190. } \
  191. } else { \
  192. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  193. u##__width data = get_unaligned(buf++); \
  194. tmio_sd_write##__suffix(priv, data, \
  195. TMIO_SD_BUF); \
  196. } \
  197. } \
  198. }
  199. tmio_pio_write_fifo(64, q)
  200. tmio_pio_write_fifo(32, l)
  201. tmio_pio_write_fifo(16, w)
  202. static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
  203. const char *pbuf, uint blocksize)
  204. {
  205. struct tmio_sd_priv *priv = dev_get_priv(dev);
  206. int ret;
  207. /* wait until the buffer becomes empty */
  208. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  209. TMIO_SD_INFO2_BWE);
  210. if (ret)
  211. return ret;
  212. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  213. if (priv->caps & TMIO_SD_CAP_64BIT)
  214. tmio_pio_write_fifo_64(priv, pbuf, blocksize);
  215. else if (priv->caps & TMIO_SD_CAP_16BIT)
  216. tmio_pio_write_fifo_16(priv, pbuf, blocksize);
  217. else
  218. tmio_pio_write_fifo_32(priv, pbuf, blocksize);
  219. return 0;
  220. }
  221. static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
  222. struct mmc_data *data)
  223. {
  224. const char *src = data->src;
  225. char *dest = data->dest;
  226. int i, ret;
  227. for (i = 0; i < data->blocks; i++) {
  228. if (data->flags & MMC_DATA_READ)
  229. ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
  230. data->blocksize);
  231. else
  232. ret = tmio_sd_pio_write_one_block(dev, cmd, src,
  233. data->blocksize);
  234. if (ret)
  235. return ret;
  236. if (data->flags & MMC_DATA_READ)
  237. dest += data->blocksize;
  238. else
  239. src += data->blocksize;
  240. }
  241. return 0;
  242. }
  243. static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
  244. dma_addr_t dma_addr)
  245. {
  246. u32 tmp;
  247. tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
  248. tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
  249. /* enable DMA */
  250. tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
  251. tmp |= TMIO_SD_EXTMODE_DMA_EN;
  252. tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
  253. tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
  254. /* suppress the warning "right shift count >= width of type" */
  255. dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
  256. tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
  257. tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
  258. }
  259. static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
  260. unsigned int blocks)
  261. {
  262. struct tmio_sd_priv *priv = dev_get_priv(dev);
  263. long wait = 1000000 + 10 * blocks;
  264. while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
  265. if (wait-- < 0) {
  266. dev_err(dev, "timeout during DMA\n");
  267. return -ETIMEDOUT;
  268. }
  269. udelay(10);
  270. }
  271. if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
  272. dev_err(dev, "error during DMA\n");
  273. return -EIO;
  274. }
  275. return 0;
  276. }
  277. static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
  278. {
  279. struct tmio_sd_priv *priv = dev_get_priv(dev);
  280. size_t len = data->blocks * data->blocksize;
  281. void *buf;
  282. enum dma_data_direction dir;
  283. dma_addr_t dma_addr;
  284. u32 poll_flag, tmp;
  285. int ret;
  286. tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
  287. if (data->flags & MMC_DATA_READ) {
  288. buf = data->dest;
  289. dir = DMA_FROM_DEVICE;
  290. /*
  291. * The DMA READ completion flag position differs on Socionext
  292. * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
  293. * bit 17 is a hardware bug and forbidden. It is either bit 17
  294. * or bit 20 on Renesas SoCs, depending on SoC.
  295. */
  296. poll_flag = priv->read_poll_flag;
  297. tmp |= TMIO_SD_DMA_MODE_DIR_RD;
  298. } else {
  299. buf = (void *)data->src;
  300. dir = DMA_TO_DEVICE;
  301. poll_flag = TMIO_SD_DMA_INFO1_END_WR;
  302. tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
  303. }
  304. tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
  305. dma_addr = __dma_map_single(buf, len, dir);
  306. tmio_sd_dma_start(priv, dma_addr);
  307. ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
  308. if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
  309. udelay(1);
  310. __dma_unmap_single(dma_addr, len, dir);
  311. return ret;
  312. }
  313. /* check if the address is DMA'able */
  314. static bool tmio_sd_addr_is_dmaable(const char *src)
  315. {
  316. uintptr_t addr = (uintptr_t)src;
  317. if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
  318. return false;
  319. #if defined(CONFIG_RCAR_GEN3)
  320. /* Gen3 DMA has 32bit limit */
  321. if (addr >> 32)
  322. return false;
  323. #endif
  324. #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
  325. defined(CONFIG_SPL_BUILD)
  326. /*
  327. * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
  328. * of L2, which is unreachable from the DMA engine.
  329. */
  330. if (addr < CONFIG_SPL_STACK)
  331. return false;
  332. #endif
  333. return true;
  334. }
  335. int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  336. struct mmc_data *data)
  337. {
  338. struct tmio_sd_priv *priv = dev_get_priv(dev);
  339. int ret;
  340. u32 tmp;
  341. if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
  342. dev_err(dev, "command busy\n");
  343. return -EBUSY;
  344. }
  345. /* clear all status flags */
  346. tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
  347. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  348. /* disable DMA once */
  349. tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
  350. tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
  351. tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
  352. tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
  353. tmp = cmd->cmdidx;
  354. if (data) {
  355. tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
  356. tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
  357. /* Do not send CMD12 automatically */
  358. tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
  359. if (data->blocks > 1)
  360. tmp |= TMIO_SD_CMD_MULTI;
  361. if (data->flags & MMC_DATA_READ)
  362. tmp |= TMIO_SD_CMD_RD;
  363. }
  364. /*
  365. * Do not use the response type auto-detection on this hardware.
  366. * CMD8, for example, has different response types on SD and eMMC,
  367. * while this controller always assumes the response type for SD.
  368. * Set the response type manually.
  369. */
  370. switch (cmd->resp_type) {
  371. case MMC_RSP_NONE:
  372. tmp |= TMIO_SD_CMD_RSP_NONE;
  373. break;
  374. case MMC_RSP_R1:
  375. tmp |= TMIO_SD_CMD_RSP_R1;
  376. break;
  377. case MMC_RSP_R1b:
  378. tmp |= TMIO_SD_CMD_RSP_R1B;
  379. break;
  380. case MMC_RSP_R2:
  381. tmp |= TMIO_SD_CMD_RSP_R2;
  382. break;
  383. case MMC_RSP_R3:
  384. tmp |= TMIO_SD_CMD_RSP_R3;
  385. break;
  386. default:
  387. dev_err(dev, "unknown response type\n");
  388. return -EINVAL;
  389. }
  390. dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
  391. cmd->cmdidx, tmp, cmd->cmdarg);
  392. tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
  393. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
  394. TMIO_SD_INFO1_RSP);
  395. if (ret)
  396. return ret;
  397. if (cmd->resp_type & MMC_RSP_136) {
  398. u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
  399. u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
  400. u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
  401. u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
  402. cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
  403. ((rsp_103_72 & 0xff000000) >> 24);
  404. cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
  405. ((rsp_71_40 & 0xff000000) >> 24);
  406. cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
  407. ((rsp_39_8 & 0xff000000) >> 24);
  408. cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
  409. } else {
  410. /* bit 39-8 */
  411. cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
  412. }
  413. if (data) {
  414. /* use DMA if the HW supports it and the buffer is aligned */
  415. if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
  416. tmio_sd_addr_is_dmaable(data->src))
  417. ret = tmio_sd_dma_xfer(dev, data);
  418. else
  419. ret = tmio_sd_pio_xfer(dev, cmd, data);
  420. if (ret)
  421. return ret;
  422. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
  423. TMIO_SD_INFO1_CMP);
  424. if (ret)
  425. return ret;
  426. }
  427. return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  428. TMIO_SD_INFO2_SCLKDIVEN);
  429. }
  430. static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
  431. struct mmc *mmc)
  432. {
  433. u32 val, tmp;
  434. switch (mmc->bus_width) {
  435. case 0:
  436. case 1:
  437. val = TMIO_SD_OPTION_WIDTH_1;
  438. break;
  439. case 4:
  440. val = TMIO_SD_OPTION_WIDTH_4;
  441. break;
  442. case 8:
  443. val = TMIO_SD_OPTION_WIDTH_8;
  444. break;
  445. default:
  446. return -EINVAL;
  447. }
  448. tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
  449. tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
  450. tmp |= val;
  451. tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
  452. return 0;
  453. }
  454. static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
  455. struct mmc *mmc)
  456. {
  457. u32 tmp;
  458. tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
  459. if (mmc->ddr_mode)
  460. tmp |= TMIO_SD_IF_MODE_DDR;
  461. else
  462. tmp &= ~TMIO_SD_IF_MODE_DDR;
  463. tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
  464. }
  465. static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
  466. {
  467. return priv->clk_get_rate(priv);
  468. }
  469. static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
  470. {
  471. unsigned int divisor;
  472. u32 tmp, val = 0;
  473. ulong mclk;
  474. if (mmc->clock) {
  475. mclk = tmio_sd_clk_get_rate(priv);
  476. divisor = DIV_ROUND_UP(mclk, mmc->clock);
  477. /* Do not set divider to 0xff in DDR mode */
  478. if (mmc->ddr_mode && (divisor == 1))
  479. divisor = 2;
  480. if (divisor <= 1)
  481. val = (priv->caps & TMIO_SD_CAP_RCAR) ?
  482. TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
  483. else if (divisor <= 2)
  484. val = TMIO_SD_CLKCTL_DIV2;
  485. else if (divisor <= 4)
  486. val = TMIO_SD_CLKCTL_DIV4;
  487. else if (divisor <= 8)
  488. val = TMIO_SD_CLKCTL_DIV8;
  489. else if (divisor <= 16)
  490. val = TMIO_SD_CLKCTL_DIV16;
  491. else if (divisor <= 32)
  492. val = TMIO_SD_CLKCTL_DIV32;
  493. else if (divisor <= 64)
  494. val = TMIO_SD_CLKCTL_DIV64;
  495. else if (divisor <= 128)
  496. val = TMIO_SD_CLKCTL_DIV128;
  497. else if (divisor <= 256)
  498. val = TMIO_SD_CLKCTL_DIV256;
  499. else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
  500. val = TMIO_SD_CLKCTL_DIV512;
  501. else
  502. val = TMIO_SD_CLKCTL_DIV1024;
  503. }
  504. tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  505. if (mmc->clock &&
  506. !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
  507. ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
  508. /*
  509. * Stop the clock before changing its rate
  510. * to avoid a glitch signal
  511. */
  512. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  513. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  514. /* Change the clock rate. */
  515. tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
  516. tmp |= val;
  517. }
  518. /* Enable or Disable the clock */
  519. if (mmc->clk_disable) {
  520. tmp |= TMIO_SD_CLKCTL_OFFEN;
  521. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  522. } else {
  523. tmp &= ~TMIO_SD_CLKCTL_OFFEN;
  524. tmp |= TMIO_SD_CLKCTL_SCLKEN;
  525. }
  526. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  527. udelay(1000);
  528. }
  529. static void tmio_sd_set_pins(struct udevice *dev)
  530. {
  531. __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
  532. #ifdef CONFIG_DM_REGULATOR
  533. struct tmio_sd_priv *priv = dev_get_priv(dev);
  534. if (priv->vqmmc_dev) {
  535. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  536. regulator_set_value(priv->vqmmc_dev, 1800000);
  537. else
  538. regulator_set_value(priv->vqmmc_dev, 3300000);
  539. regulator_set_enable(priv->vqmmc_dev, true);
  540. }
  541. #endif
  542. #ifdef CONFIG_PINCTRL
  543. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  544. pinctrl_select_state(dev, "state_uhs");
  545. else
  546. pinctrl_select_state(dev, "default");
  547. #endif
  548. }
  549. int tmio_sd_set_ios(struct udevice *dev)
  550. {
  551. struct tmio_sd_priv *priv = dev_get_priv(dev);
  552. struct mmc *mmc = mmc_get_mmc_dev(dev);
  553. int ret;
  554. dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
  555. mmc->clock, mmc->ddr_mode, mmc->bus_width);
  556. tmio_sd_set_clk_rate(priv, mmc);
  557. ret = tmio_sd_set_bus_width(priv, mmc);
  558. if (ret)
  559. return ret;
  560. tmio_sd_set_ddr_mode(priv, mmc);
  561. tmio_sd_set_pins(dev);
  562. return 0;
  563. }
  564. int tmio_sd_get_cd(struct udevice *dev)
  565. {
  566. struct tmio_sd_priv *priv = dev_get_priv(dev);
  567. if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
  568. return 1;
  569. return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
  570. TMIO_SD_INFO1_CD);
  571. }
  572. static void tmio_sd_host_init(struct tmio_sd_priv *priv)
  573. {
  574. u32 tmp;
  575. /* soft reset of the host */
  576. tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
  577. tmp &= ~TMIO_SD_SOFT_RST_RSTX;
  578. tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
  579. tmp |= TMIO_SD_SOFT_RST_RSTX;
  580. tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
  581. /* FIXME: implement eMMC hw_reset */
  582. tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
  583. /*
  584. * Connected to 32bit AXI.
  585. * This register dropped backward compatibility at version 0x10.
  586. * Write an appropriate value depending on the IP version.
  587. */
  588. if (priv->version >= 0x10) {
  589. if (priv->caps & TMIO_SD_CAP_64BIT)
  590. tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
  591. else
  592. tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
  593. } else {
  594. tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
  595. }
  596. if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
  597. tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
  598. tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
  599. tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
  600. }
  601. }
  602. int tmio_sd_bind(struct udevice *dev)
  603. {
  604. struct tmio_sd_plat *plat = dev_get_platdata(dev);
  605. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  606. }
  607. int tmio_sd_probe(struct udevice *dev, u32 quirks)
  608. {
  609. struct tmio_sd_plat *plat = dev_get_platdata(dev);
  610. struct tmio_sd_priv *priv = dev_get_priv(dev);
  611. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  612. fdt_addr_t base;
  613. ulong mclk;
  614. int ret;
  615. base = devfdt_get_addr(dev);
  616. if (base == FDT_ADDR_T_NONE)
  617. return -EINVAL;
  618. priv->regbase = devm_ioremap(dev, base, SZ_2K);
  619. if (!priv->regbase)
  620. return -ENOMEM;
  621. #ifdef CONFIG_DM_REGULATOR
  622. device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
  623. if (priv->vqmmc_dev)
  624. regulator_set_value(priv->vqmmc_dev, 3300000);
  625. #endif
  626. ret = mmc_of_parse(dev, &plat->cfg);
  627. if (ret < 0) {
  628. dev_err(dev, "failed to parse host caps\n");
  629. return ret;
  630. }
  631. plat->cfg.name = dev->name;
  632. plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  633. if (quirks)
  634. priv->caps = quirks;
  635. priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
  636. TMIO_SD_VERSION_IP;
  637. dev_dbg(dev, "version %x\n", priv->version);
  638. if (priv->version >= 0x10) {
  639. priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
  640. priv->caps |= TMIO_SD_CAP_DIV1024;
  641. }
  642. if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
  643. NULL))
  644. priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
  645. tmio_sd_host_init(priv);
  646. mclk = tmio_sd_clk_get_rate(priv);
  647. plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
  648. plat->cfg.f_min = mclk /
  649. (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
  650. plat->cfg.f_max = mclk;
  651. if (quirks & TMIO_SD_CAP_16BIT)
  652. plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
  653. else
  654. plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
  655. upriv->mmc = &plat->mmc;
  656. return 0;
  657. }