tegra_mmc.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 SAMSUNG Electronics
  4. * Minkyu Kang <mk7.kang@samsung.com>
  5. * Jaehoon Chung <jh80.chung@samsung.com>
  6. * Portions Copyright 2011-2016 NVIDIA Corporation
  7. */
  8. #include <bouncebuf.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <mmc.h>
  13. #include <asm/gpio.h>
  14. #include <asm/io.h>
  15. #include <asm/arch-tegra/tegra_mmc.h>
  16. struct tegra_mmc_plat {
  17. struct mmc_config cfg;
  18. struct mmc mmc;
  19. };
  20. struct tegra_mmc_priv {
  21. struct tegra_mmc *reg;
  22. struct reset_ctl reset_ctl;
  23. struct clk clk;
  24. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  25. struct gpio_desc pwr_gpio; /* Power GPIO */
  26. struct gpio_desc wp_gpio; /* Write Protect GPIO */
  27. unsigned int version; /* SDHCI spec. version */
  28. unsigned int clock; /* Current clock (MHz) */
  29. };
  30. static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
  31. unsigned short power)
  32. {
  33. u8 pwr = 0;
  34. debug("%s: power = %x\n", __func__, power);
  35. if (power != (unsigned short)-1) {
  36. switch (1 << power) {
  37. case MMC_VDD_165_195:
  38. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  39. break;
  40. case MMC_VDD_29_30:
  41. case MMC_VDD_30_31:
  42. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  43. break;
  44. case MMC_VDD_32_33:
  45. case MMC_VDD_33_34:
  46. pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  47. break;
  48. }
  49. }
  50. debug("%s: pwr = %X\n", __func__, pwr);
  51. /* Set the bus voltage first (if any) */
  52. writeb(pwr, &priv->reg->pwrcon);
  53. if (pwr == 0)
  54. return;
  55. /* Now enable bus power */
  56. pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  57. writeb(pwr, &priv->reg->pwrcon);
  58. }
  59. static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
  60. struct mmc_data *data,
  61. struct bounce_buffer *bbstate)
  62. {
  63. unsigned char ctrl;
  64. debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  65. bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  66. data->blocksize);
  67. writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
  68. /*
  69. * DMASEL[4:3]
  70. * 00 = Selects SDMA
  71. * 01 = Reserved
  72. * 10 = Selects 32-bit Address ADMA2
  73. * 11 = Selects 64-bit Address ADMA2
  74. */
  75. ctrl = readb(&priv->reg->hostctl);
  76. ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  77. ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  78. writeb(ctrl, &priv->reg->hostctl);
  79. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  80. writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
  81. writew(data->blocks, &priv->reg->blkcnt);
  82. }
  83. static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
  84. struct mmc_data *data)
  85. {
  86. unsigned short mode;
  87. debug(" mmc_set_transfer_mode called\n");
  88. /*
  89. * TRNMOD
  90. * MUL1SIN0[5] : Multi/Single Block Select
  91. * RD1WT0[4] : Data Transfer Direction Select
  92. * 1 = read
  93. * 0 = write
  94. * ENACMD12[2] : Auto CMD12 Enable
  95. * ENBLKCNT[1] : Block Count Enable
  96. * ENDMA[0] : DMA Enable
  97. */
  98. mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
  99. TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
  100. if (data->blocks > 1)
  101. mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
  102. if (data->flags & MMC_DATA_READ)
  103. mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
  104. writew(mode, &priv->reg->trnmod);
  105. }
  106. static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
  107. struct mmc_cmd *cmd,
  108. struct mmc_data *data,
  109. unsigned int timeout)
  110. {
  111. /*
  112. * PRNSTS
  113. * CMDINHDAT[1] : Command Inhibit (DAT)
  114. * CMDINHCMD[0] : Command Inhibit (CMD)
  115. */
  116. unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
  117. /*
  118. * We shouldn't wait for data inhibit for stop commands, even
  119. * though they might use busy signaling
  120. */
  121. if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
  122. mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
  123. while (readl(&priv->reg->prnsts) & mask) {
  124. if (timeout == 0) {
  125. printf("%s: timeout error\n", __func__);
  126. return -1;
  127. }
  128. timeout--;
  129. udelay(1000);
  130. }
  131. return 0;
  132. }
  133. static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
  134. struct mmc_data *data,
  135. struct bounce_buffer *bbstate)
  136. {
  137. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  138. int flags, i;
  139. int result;
  140. unsigned int mask = 0;
  141. unsigned int retry = 0x100000;
  142. debug(" mmc_send_cmd called\n");
  143. result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
  144. if (result < 0)
  145. return result;
  146. if (data)
  147. tegra_mmc_prepare_data(priv, data, bbstate);
  148. debug("cmd->arg: %08x\n", cmd->cmdarg);
  149. writel(cmd->cmdarg, &priv->reg->argument);
  150. if (data)
  151. tegra_mmc_set_transfer_mode(priv, data);
  152. if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
  153. return -1;
  154. /*
  155. * CMDREG
  156. * CMDIDX[13:8] : Command index
  157. * DATAPRNT[5] : Data Present Select
  158. * ENCMDIDX[4] : Command Index Check Enable
  159. * ENCMDCRC[3] : Command CRC Check Enable
  160. * RSPTYP[1:0]
  161. * 00 = No Response
  162. * 01 = Length 136
  163. * 10 = Length 48
  164. * 11 = Length 48 Check busy after response
  165. */
  166. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  167. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
  168. else if (cmd->resp_type & MMC_RSP_136)
  169. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
  170. else if (cmd->resp_type & MMC_RSP_BUSY)
  171. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
  172. else
  173. flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
  174. if (cmd->resp_type & MMC_RSP_CRC)
  175. flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
  176. if (cmd->resp_type & MMC_RSP_OPCODE)
  177. flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
  178. if (data)
  179. flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
  180. debug("cmd: %d\n", cmd->cmdidx);
  181. writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
  182. for (i = 0; i < retry; i++) {
  183. mask = readl(&priv->reg->norintsts);
  184. /* Command Complete */
  185. if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
  186. if (!data)
  187. writel(mask, &priv->reg->norintsts);
  188. break;
  189. }
  190. }
  191. if (i == retry) {
  192. printf("%s: waiting for status update\n", __func__);
  193. writel(mask, &priv->reg->norintsts);
  194. return -ETIMEDOUT;
  195. }
  196. if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
  197. /* Timeout Error */
  198. debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
  199. writel(mask, &priv->reg->norintsts);
  200. return -ETIMEDOUT;
  201. } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
  202. /* Error Interrupt */
  203. debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
  204. writel(mask, &priv->reg->norintsts);
  205. return -1;
  206. }
  207. if (cmd->resp_type & MMC_RSP_PRESENT) {
  208. if (cmd->resp_type & MMC_RSP_136) {
  209. /* CRC is stripped so we need to do some shifting. */
  210. for (i = 0; i < 4; i++) {
  211. unsigned long offset = (unsigned long)
  212. (&priv->reg->rspreg3 - i);
  213. cmd->response[i] = readl(offset) << 8;
  214. if (i != 3) {
  215. cmd->response[i] |=
  216. readb(offset - 1);
  217. }
  218. debug("cmd->resp[%d]: %08x\n",
  219. i, cmd->response[i]);
  220. }
  221. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  222. for (i = 0; i < retry; i++) {
  223. /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
  224. if (readl(&priv->reg->prnsts)
  225. & (1 << 20)) /* DAT[0] */
  226. break;
  227. }
  228. if (i == retry) {
  229. printf("%s: card is still busy\n", __func__);
  230. writel(mask, &priv->reg->norintsts);
  231. return -ETIMEDOUT;
  232. }
  233. cmd->response[0] = readl(&priv->reg->rspreg0);
  234. debug("cmd->resp[0]: %08x\n", cmd->response[0]);
  235. } else {
  236. cmd->response[0] = readl(&priv->reg->rspreg0);
  237. debug("cmd->resp[0]: %08x\n", cmd->response[0]);
  238. }
  239. }
  240. if (data) {
  241. unsigned long start = get_timer(0);
  242. while (1) {
  243. mask = readl(&priv->reg->norintsts);
  244. if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
  245. /* Error Interrupt */
  246. writel(mask, &priv->reg->norintsts);
  247. printf("%s: error during transfer: 0x%08x\n",
  248. __func__, mask);
  249. return -1;
  250. } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
  251. /*
  252. * DMA Interrupt, restart the transfer where
  253. * it was interrupted.
  254. */
  255. unsigned int address = readl(&priv->reg->sysad);
  256. debug("DMA end\n");
  257. writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
  258. &priv->reg->norintsts);
  259. writel(address, &priv->reg->sysad);
  260. } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
  261. /* Transfer Complete */
  262. debug("r/w is done\n");
  263. break;
  264. } else if (get_timer(start) > 8000UL) {
  265. writel(mask, &priv->reg->norintsts);
  266. printf("%s: MMC Timeout\n"
  267. " Interrupt status 0x%08x\n"
  268. " Interrupt status enable 0x%08x\n"
  269. " Interrupt signal enable 0x%08x\n"
  270. " Present status 0x%08x\n",
  271. __func__, mask,
  272. readl(&priv->reg->norintstsen),
  273. readl(&priv->reg->norintsigen),
  274. readl(&priv->reg->prnsts));
  275. return -1;
  276. }
  277. }
  278. writel(mask, &priv->reg->norintsts);
  279. }
  280. udelay(1000);
  281. return 0;
  282. }
  283. static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  284. struct mmc_data *data)
  285. {
  286. void *buf;
  287. unsigned int bbflags;
  288. size_t len;
  289. struct bounce_buffer bbstate;
  290. int ret;
  291. if (data) {
  292. if (data->flags & MMC_DATA_READ) {
  293. buf = data->dest;
  294. bbflags = GEN_BB_WRITE;
  295. } else {
  296. buf = (void *)data->src;
  297. bbflags = GEN_BB_READ;
  298. }
  299. len = data->blocks * data->blocksize;
  300. bounce_buffer_start(&bbstate, buf, len, bbflags);
  301. }
  302. ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
  303. if (data)
  304. bounce_buffer_stop(&bbstate);
  305. return ret;
  306. }
  307. static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
  308. {
  309. ulong rate;
  310. int div;
  311. unsigned short clk;
  312. unsigned long timeout;
  313. debug(" mmc_change_clock called\n");
  314. /*
  315. * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
  316. */
  317. if (clock == 0)
  318. goto out;
  319. rate = clk_set_rate(&priv->clk, clock);
  320. div = (rate + clock - 1) / clock;
  321. debug("div = %d\n", div);
  322. writew(0, &priv->reg->clkcon);
  323. /*
  324. * CLKCON
  325. * SELFREQ[15:8] : base clock divided by value
  326. * ENSDCLK[2] : SD Clock Enable
  327. * STBLINTCLK[1] : Internal Clock Stable
  328. * ENINTCLK[0] : Internal Clock Enable
  329. */
  330. div >>= 1;
  331. clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
  332. TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
  333. writew(clk, &priv->reg->clkcon);
  334. /* Wait max 10 ms */
  335. timeout = 10;
  336. while (!(readw(&priv->reg->clkcon) &
  337. TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
  338. if (timeout == 0) {
  339. printf("%s: timeout error\n", __func__);
  340. return;
  341. }
  342. timeout--;
  343. udelay(1000);
  344. }
  345. clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
  346. writew(clk, &priv->reg->clkcon);
  347. debug("mmc_change_clock: clkcon = %08X\n", clk);
  348. out:
  349. priv->clock = clock;
  350. }
  351. static int tegra_mmc_set_ios(struct udevice *dev)
  352. {
  353. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  354. struct mmc *mmc = mmc_get_mmc_dev(dev);
  355. unsigned char ctrl;
  356. debug(" mmc_set_ios called\n");
  357. debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
  358. /* Change clock first */
  359. tegra_mmc_change_clock(priv, mmc->clock);
  360. ctrl = readb(&priv->reg->hostctl);
  361. /*
  362. * WIDE8[5]
  363. * 0 = Depend on WIDE4
  364. * 1 = 8-bit mode
  365. * WIDE4[1]
  366. * 1 = 4-bit mode
  367. * 0 = 1-bit mode
  368. */
  369. if (mmc->bus_width == 8)
  370. ctrl |= (1 << 5);
  371. else if (mmc->bus_width == 4)
  372. ctrl |= (1 << 1);
  373. else
  374. ctrl &= ~(1 << 1 | 1 << 5);
  375. writeb(ctrl, &priv->reg->hostctl);
  376. debug("mmc_set_ios: hostctl = %08X\n", ctrl);
  377. return 0;
  378. }
  379. static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
  380. {
  381. #if defined(CONFIG_TEGRA30)
  382. u32 val;
  383. debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
  384. /* Set the pad drive strength for SDMMC1 or 3 only */
  385. if (priv->reg != (void *)0x78000000 &&
  386. priv->reg != (void *)0x78000400) {
  387. debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
  388. __func__);
  389. return;
  390. }
  391. val = readl(&priv->reg->sdmemcmppadctl);
  392. val &= 0xFFFFFFF0;
  393. val |= MEMCOMP_PADCTRL_VREF;
  394. writel(val, &priv->reg->sdmemcmppadctl);
  395. val = readl(&priv->reg->autocalcfg);
  396. val &= 0xFFFF0000;
  397. val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
  398. writel(val, &priv->reg->autocalcfg);
  399. #endif
  400. }
  401. static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
  402. {
  403. unsigned int timeout;
  404. debug(" mmc_reset called\n");
  405. /*
  406. * RSTALL[0] : Software reset for all
  407. * 1 = reset
  408. * 0 = work
  409. */
  410. writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
  411. priv->clock = 0;
  412. /* Wait max 100 ms */
  413. timeout = 100;
  414. /* hw clears the bit when it's done */
  415. while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
  416. if (timeout == 0) {
  417. printf("%s: timeout error\n", __func__);
  418. return;
  419. }
  420. timeout--;
  421. udelay(1000);
  422. }
  423. /* Set SD bus voltage & enable bus power */
  424. tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
  425. debug("%s: power control = %02X, host control = %02X\n", __func__,
  426. readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
  427. /* Make sure SDIO pads are set up */
  428. tegra_mmc_pad_init(priv);
  429. }
  430. static int tegra_mmc_init(struct udevice *dev)
  431. {
  432. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  433. struct mmc *mmc = mmc_get_mmc_dev(dev);
  434. unsigned int mask;
  435. debug(" tegra_mmc_init called\n");
  436. tegra_mmc_reset(priv, mmc);
  437. #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
  438. /*
  439. * Disable the external clock loopback and use the internal one on
  440. * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
  441. * bits being set to 0xfffd according to the TRM.
  442. *
  443. * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
  444. * approach once proper kernel integration made it mainline.
  445. */
  446. if (priv->reg == (void *)0x700b0400) {
  447. mask = readl(&priv->reg->venmiscctl);
  448. mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
  449. writel(mask, &priv->reg->venmiscctl);
  450. }
  451. #endif
  452. priv->version = readw(&priv->reg->hcver);
  453. debug("host version = %x\n", priv->version);
  454. /* mask all */
  455. writel(0xffffffff, &priv->reg->norintstsen);
  456. writel(0xffffffff, &priv->reg->norintsigen);
  457. writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
  458. /*
  459. * NORMAL Interrupt Status Enable Register init
  460. * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
  461. * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
  462. * [3] ENSTADMAINT : DMA boundary interrupt
  463. * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
  464. * [0] ENSTACMDCMPLT : Command Complete Status Enable
  465. */
  466. mask = readl(&priv->reg->norintstsen);
  467. mask &= ~(0xffff);
  468. mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
  469. TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
  470. TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
  471. TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
  472. TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
  473. writel(mask, &priv->reg->norintstsen);
  474. /*
  475. * NORMAL Interrupt Signal Enable Register init
  476. * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
  477. */
  478. mask = readl(&priv->reg->norintsigen);
  479. mask &= ~(0xffff);
  480. mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
  481. writel(mask, &priv->reg->norintsigen);
  482. return 0;
  483. }
  484. static int tegra_mmc_getcd(struct udevice *dev)
  485. {
  486. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  487. debug("tegra_mmc_getcd called\n");
  488. if (dm_gpio_is_valid(&priv->cd_gpio))
  489. return dm_gpio_get_value(&priv->cd_gpio);
  490. return 1;
  491. }
  492. static const struct dm_mmc_ops tegra_mmc_ops = {
  493. .send_cmd = tegra_mmc_send_cmd,
  494. .set_ios = tegra_mmc_set_ios,
  495. .get_cd = tegra_mmc_getcd,
  496. };
  497. static int tegra_mmc_probe(struct udevice *dev)
  498. {
  499. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  500. struct tegra_mmc_plat *plat = dev_get_platdata(dev);
  501. struct tegra_mmc_priv *priv = dev_get_priv(dev);
  502. struct mmc_config *cfg = &plat->cfg;
  503. int bus_width, ret;
  504. cfg->name = dev->name;
  505. bus_width = dev_read_u32_default(dev, "bus-width", 1);
  506. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  507. cfg->host_caps = 0;
  508. if (bus_width == 8)
  509. cfg->host_caps |= MMC_MODE_8BIT;
  510. if (bus_width >= 4)
  511. cfg->host_caps |= MMC_MODE_4BIT;
  512. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  513. /*
  514. * min freq is for card identification, and is the highest
  515. * low-speed SDIO card frequency (actually 400KHz)
  516. * max freq is highest HS eMMC clock as per the SD/MMC spec
  517. * (actually 52MHz)
  518. */
  519. cfg->f_min = 375000;
  520. cfg->f_max = 48000000;
  521. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  522. priv->reg = (void *)dev_read_addr(dev);
  523. ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
  524. if (ret) {
  525. debug("reset_get_by_name() failed: %d\n", ret);
  526. return ret;
  527. }
  528. ret = clk_get_by_index(dev, 0, &priv->clk);
  529. if (ret) {
  530. debug("clk_get_by_index() failed: %d\n", ret);
  531. return ret;
  532. }
  533. ret = reset_assert(&priv->reset_ctl);
  534. if (ret)
  535. return ret;
  536. ret = clk_enable(&priv->clk);
  537. if (ret)
  538. return ret;
  539. ret = clk_set_rate(&priv->clk, 20000000);
  540. if (IS_ERR_VALUE(ret))
  541. return ret;
  542. ret = reset_deassert(&priv->reset_ctl);
  543. if (ret)
  544. return ret;
  545. /* These GPIOs are optional */
  546. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
  547. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
  548. gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
  549. GPIOD_IS_OUT);
  550. if (dm_gpio_is_valid(&priv->pwr_gpio))
  551. dm_gpio_set_value(&priv->pwr_gpio, 1);
  552. upriv->mmc = &plat->mmc;
  553. return tegra_mmc_init(dev);
  554. }
  555. static int tegra_mmc_bind(struct udevice *dev)
  556. {
  557. struct tegra_mmc_plat *plat = dev_get_platdata(dev);
  558. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  559. }
  560. static const struct udevice_id tegra_mmc_ids[] = {
  561. { .compatible = "nvidia,tegra20-sdhci" },
  562. { .compatible = "nvidia,tegra30-sdhci" },
  563. { .compatible = "nvidia,tegra114-sdhci" },
  564. { .compatible = "nvidia,tegra124-sdhci" },
  565. { .compatible = "nvidia,tegra210-sdhci" },
  566. { .compatible = "nvidia,tegra186-sdhci" },
  567. { }
  568. };
  569. U_BOOT_DRIVER(tegra_mmc_drv) = {
  570. .name = "tegra_mmc",
  571. .id = UCLASS_MMC,
  572. .of_match = tegra_mmc_ids,
  573. .bind = tegra_mmc_bind,
  574. .probe = tegra_mmc_probe,
  575. .ops = &tegra_mmc_ops,
  576. .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
  577. .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
  578. };