mmc_spi.c 10 KB

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  1. /*
  2. * generic mmc spi driver
  3. *
  4. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
  5. * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
  6. *
  7. * Licensed under the GPL-2 or later.
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <malloc.h>
  12. #include <part.h>
  13. #include <mmc.h>
  14. #include <stdlib.h>
  15. #include <u-boot/crc.h>
  16. #include <linux/crc7.h>
  17. #include <asm/byteorder.h>
  18. #include <dm.h>
  19. #include <spi.h>
  20. /* MMC/SD in SPI mode reports R1 status always */
  21. #define R1_SPI_IDLE BIT(0)
  22. #define R1_SPI_ERASE_RESET BIT(1)
  23. #define R1_SPI_ILLEGAL_COMMAND BIT(2)
  24. #define R1_SPI_COM_CRC BIT(3)
  25. #define R1_SPI_ERASE_SEQ BIT(4)
  26. #define R1_SPI_ADDRESS BIT(5)
  27. #define R1_SPI_PARAMETER BIT(6)
  28. /* R1 bit 7 is always zero, reuse this bit for error */
  29. #define R1_SPI_ERROR BIT(7)
  30. /* Response tokens used to ack each block written: */
  31. #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
  32. #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
  33. #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
  34. #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
  35. /* Read and write blocks start with these tokens and end with crc;
  36. * on error, read tokens act like a subset of R2_SPI_* values.
  37. */
  38. /* single block write multiblock read */
  39. #define SPI_TOKEN_SINGLE 0xfe
  40. /* multiblock write */
  41. #define SPI_TOKEN_MULTI_WRITE 0xfc
  42. /* terminate multiblock write */
  43. #define SPI_TOKEN_STOP_TRAN 0xfd
  44. /* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
  45. #define MMC_SPI_CMD(x) (0x40 | (x))
  46. /* bus capability */
  47. #define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
  48. #define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
  49. #define MMC_SPI_MAX_CLOCK 25000000 /* SD/MMC legacy speed */
  50. /* timeout value */
  51. #define CMD_TIMEOUT 8
  52. #define READ_TIMEOUT 3000000 /* 1 sec */
  53. #define WRITE_TIMEOUT 3000000 /* 1 sec */
  54. struct mmc_spi_plat {
  55. struct mmc_config cfg;
  56. struct mmc mmc;
  57. };
  58. struct mmc_spi_priv {
  59. struct spi_slave *spi;
  60. };
  61. static int mmc_spi_sendcmd(struct udevice *dev,
  62. ushort cmdidx, u32 cmdarg, u32 resp_type,
  63. u8 *resp, u32 resp_size,
  64. bool resp_match, u8 resp_match_value)
  65. {
  66. int i, rpos = 0, ret = 0;
  67. u8 cmdo[7], r;
  68. debug("%s: cmd%d cmdarg=0x%x resp_type=0x%x "
  69. "resp_size=%d resp_match=%d resp_match_value=0x%x\n",
  70. __func__, cmdidx, cmdarg, resp_type,
  71. resp_size, resp_match, resp_match_value);
  72. cmdo[0] = 0xff;
  73. cmdo[1] = MMC_SPI_CMD(cmdidx);
  74. cmdo[2] = cmdarg >> 24;
  75. cmdo[3] = cmdarg >> 16;
  76. cmdo[4] = cmdarg >> 8;
  77. cmdo[5] = cmdarg;
  78. cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
  79. ret = dm_spi_xfer(dev, sizeof(cmdo) * 8, cmdo, NULL, SPI_XFER_BEGIN);
  80. if (ret)
  81. return ret;
  82. ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
  83. if (ret)
  84. return ret;
  85. if (!resp || !resp_size)
  86. return 0;
  87. debug("%s: cmd%d", __func__, cmdidx);
  88. if (resp_match) {
  89. r = ~resp_match_value;
  90. i = CMD_TIMEOUT;
  91. while (i--) {
  92. ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
  93. if (ret)
  94. return ret;
  95. debug(" resp%d=0x%x", rpos, r);
  96. rpos++;
  97. if (r == resp_match_value)
  98. break;
  99. }
  100. if (!i && (r != resp_match_value))
  101. return -ETIMEDOUT;
  102. }
  103. for (i = 0; i < resp_size; i++) {
  104. if (i == 0 && resp_match) {
  105. resp[i] = resp_match_value;
  106. continue;
  107. }
  108. ret = dm_spi_xfer(dev, 1 * 8, NULL, &r, 0);
  109. if (ret)
  110. return ret;
  111. debug(" resp%d=0x%x", rpos, r);
  112. rpos++;
  113. resp[i] = r;
  114. }
  115. debug("\n");
  116. return 0;
  117. }
  118. static int mmc_spi_readdata(struct udevice *dev,
  119. void *xbuf, u32 bcnt, u32 bsize)
  120. {
  121. u16 crc;
  122. u8 *buf = xbuf, r1;
  123. int i, ret = 0;
  124. while (bcnt--) {
  125. for (i = 0; i < READ_TIMEOUT; i++) {
  126. ret = dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
  127. if (ret)
  128. return ret;
  129. if (r1 == SPI_TOKEN_SINGLE)
  130. break;
  131. }
  132. debug("%s: data tok%d 0x%x\n", __func__, i, r1);
  133. if (r1 == SPI_TOKEN_SINGLE) {
  134. ret = dm_spi_xfer(dev, bsize * 8, NULL, buf, 0);
  135. if (ret)
  136. return ret;
  137. ret = dm_spi_xfer(dev, 2 * 8, NULL, &crc, 0);
  138. if (ret)
  139. return ret;
  140. #ifdef CONFIG_MMC_SPI_CRC_ON
  141. if (be16_to_cpu(crc16_ccitt(0, buf, bsize)) != crc) {
  142. debug("%s: data crc error\n", __func__);
  143. r1 = R1_SPI_COM_CRC;
  144. break;
  145. }
  146. #endif
  147. r1 = 0;
  148. } else {
  149. r1 = R1_SPI_ERROR;
  150. break;
  151. }
  152. buf += bsize;
  153. }
  154. if (r1 & R1_SPI_COM_CRC)
  155. ret = -ECOMM;
  156. else if (r1) /* other errors */
  157. ret = -ETIMEDOUT;
  158. return ret;
  159. }
  160. static int mmc_spi_writedata(struct udevice *dev, const void *xbuf,
  161. u32 bcnt, u32 bsize, int multi)
  162. {
  163. const u8 *buf = xbuf;
  164. u8 r1, tok[2];
  165. u16 crc;
  166. int i, ret = 0;
  167. tok[0] = 0xff;
  168. tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE;
  169. while (bcnt--) {
  170. #ifdef CONFIG_MMC_SPI_CRC_ON
  171. crc = cpu_to_be16(crc16_ccitt(0, (u8 *)buf, bsize));
  172. #endif
  173. dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
  174. dm_spi_xfer(dev, bsize * 8, buf, NULL, 0);
  175. dm_spi_xfer(dev, 2 * 8, &crc, NULL, 0);
  176. for (i = 0; i < CMD_TIMEOUT; i++) {
  177. dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
  178. if ((r1 & 0x10) == 0) /* response token */
  179. break;
  180. }
  181. debug("%s: data tok%d 0x%x\n", __func__, i, r1);
  182. if (SPI_MMC_RESPONSE_CODE(r1) == SPI_RESPONSE_ACCEPTED) {
  183. debug("%s: data accepted\n", __func__);
  184. for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
  185. dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
  186. if (i && r1 == 0xff) {
  187. r1 = 0;
  188. break;
  189. }
  190. }
  191. if (i == WRITE_TIMEOUT) {
  192. debug("%s: data write timeout 0x%x\n",
  193. __func__, r1);
  194. r1 = R1_SPI_ERROR;
  195. break;
  196. }
  197. } else {
  198. debug("%s: data error 0x%x\n", __func__, r1);
  199. r1 = R1_SPI_COM_CRC;
  200. break;
  201. }
  202. buf += bsize;
  203. }
  204. if (multi && bcnt == -1) { /* stop multi write */
  205. tok[1] = SPI_TOKEN_STOP_TRAN;
  206. dm_spi_xfer(dev, 2 * 8, tok, NULL, 0);
  207. for (i = 0; i < WRITE_TIMEOUT; i++) { /* wait busy */
  208. dm_spi_xfer(dev, 1 * 8, NULL, &r1, 0);
  209. if (i && r1 == 0xff) {
  210. r1 = 0;
  211. break;
  212. }
  213. }
  214. if (i == WRITE_TIMEOUT) {
  215. debug("%s: data write timeout 0x%x\n", __func__, r1);
  216. r1 = R1_SPI_ERROR;
  217. }
  218. }
  219. if (r1 & R1_SPI_COM_CRC)
  220. ret = -ECOMM;
  221. else if (r1) /* other errors */
  222. ret = -ETIMEDOUT;
  223. return ret;
  224. }
  225. static int dm_mmc_spi_set_ios(struct udevice *dev)
  226. {
  227. return 0;
  228. }
  229. static int dm_mmc_spi_request(struct udevice *dev, struct mmc_cmd *cmd,
  230. struct mmc_data *data)
  231. {
  232. int i, multi, ret = 0;
  233. u8 *resp = NULL;
  234. u32 resp_size = 0;
  235. bool resp_match = false;
  236. u8 resp8 = 0, resp40[5] = { 0 }, resp_match_value = 0;
  237. dm_spi_claim_bus(dev);
  238. for (i = 0; i < 4; i++)
  239. cmd->response[i] = 0;
  240. switch (cmd->cmdidx) {
  241. case SD_CMD_APP_SEND_OP_COND:
  242. case MMC_CMD_SEND_OP_COND:
  243. resp = &resp8;
  244. resp_size = sizeof(resp8);
  245. cmd->cmdarg = 0x40000000;
  246. break;
  247. case SD_CMD_SEND_IF_COND:
  248. resp = (u8 *)&resp40[0];
  249. resp_size = sizeof(resp40);
  250. resp_match = true;
  251. resp_match_value = R1_SPI_IDLE;
  252. break;
  253. case MMC_CMD_SPI_READ_OCR:
  254. resp = (u8 *)&resp40[0];
  255. resp_size = sizeof(resp40);
  256. break;
  257. case MMC_CMD_SEND_STATUS:
  258. case MMC_CMD_SET_BLOCKLEN:
  259. case MMC_CMD_SPI_CRC_ON_OFF:
  260. case MMC_CMD_STOP_TRANSMISSION:
  261. resp = &resp8;
  262. resp_size = sizeof(resp8);
  263. resp_match = true;
  264. resp_match_value = 0x0;
  265. break;
  266. case MMC_CMD_SEND_CSD:
  267. case MMC_CMD_SEND_CID:
  268. case MMC_CMD_READ_SINGLE_BLOCK:
  269. case MMC_CMD_READ_MULTIPLE_BLOCK:
  270. case MMC_CMD_WRITE_SINGLE_BLOCK:
  271. case MMC_CMD_WRITE_MULTIPLE_BLOCK:
  272. break;
  273. default:
  274. resp = &resp8;
  275. resp_size = sizeof(resp8);
  276. resp_match = true;
  277. resp_match_value = R1_SPI_IDLE;
  278. break;
  279. };
  280. ret = mmc_spi_sendcmd(dev, cmd->cmdidx, cmd->cmdarg, cmd->resp_type,
  281. resp, resp_size, resp_match, resp_match_value);
  282. if (ret)
  283. goto done;
  284. switch (cmd->cmdidx) {
  285. case SD_CMD_APP_SEND_OP_COND:
  286. case MMC_CMD_SEND_OP_COND:
  287. cmd->response[0] = (resp8 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
  288. break;
  289. case SD_CMD_SEND_IF_COND:
  290. case MMC_CMD_SPI_READ_OCR:
  291. cmd->response[0] = resp40[4];
  292. cmd->response[0] |= (uint)resp40[3] << 8;
  293. cmd->response[0] |= (uint)resp40[2] << 16;
  294. cmd->response[0] |= (uint)resp40[1] << 24;
  295. break;
  296. case MMC_CMD_SEND_STATUS:
  297. cmd->response[0] = (resp8 & 0xff) ?
  298. MMC_STATUS_ERROR : MMC_STATUS_RDY_FOR_DATA;
  299. break;
  300. case MMC_CMD_SEND_CID:
  301. case MMC_CMD_SEND_CSD:
  302. ret = mmc_spi_readdata(dev, cmd->response, 1, 16);
  303. if (ret)
  304. return ret;
  305. for (i = 0; i < 4; i++)
  306. cmd->response[i] =
  307. cpu_to_be32(cmd->response[i]);
  308. break;
  309. default:
  310. cmd->response[0] = resp8;
  311. break;
  312. }
  313. debug("%s: cmd%d resp0=0x%x resp1=0x%x resp2=0x%x resp3=0x%x\n",
  314. __func__, cmd->cmdidx, cmd->response[0], cmd->response[1],
  315. cmd->response[2], cmd->response[3]);
  316. if (data) {
  317. debug("%s: data flags=0x%x blocks=%d block_size=%d\n",
  318. __func__, data->flags, data->blocks, data->blocksize);
  319. multi = (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK);
  320. if (data->flags == MMC_DATA_READ)
  321. ret = mmc_spi_readdata(dev, data->dest,
  322. data->blocks, data->blocksize);
  323. else if (data->flags == MMC_DATA_WRITE)
  324. ret = mmc_spi_writedata(dev, data->src,
  325. data->blocks, data->blocksize,
  326. multi);
  327. }
  328. done:
  329. dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
  330. dm_spi_release_bus(dev);
  331. return ret;
  332. }
  333. static int mmc_spi_probe(struct udevice *dev)
  334. {
  335. struct mmc_spi_priv *priv = dev_get_priv(dev);
  336. struct mmc_spi_plat *plat = dev_get_platdata(dev);
  337. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  338. char *name;
  339. priv->spi = dev_get_parent_priv(dev);
  340. if (!priv->spi->max_hz)
  341. priv->spi->max_hz = MMC_SPI_MAX_CLOCK;
  342. priv->spi->speed = 0;
  343. priv->spi->mode = SPI_MODE_0;
  344. priv->spi->wordlen = 8;
  345. name = malloc(strlen(dev->parent->name) + strlen(dev->name) + 4);
  346. if (!name)
  347. return -ENOMEM;
  348. sprintf(name, "%s:%s", dev->parent->name, dev->name);
  349. plat->cfg.name = name;
  350. plat->cfg.host_caps = MMC_MODE_SPI;
  351. plat->cfg.voltages = MMC_SPI_VOLTAGE;
  352. plat->cfg.f_min = MMC_SPI_MIN_CLOCK;
  353. plat->cfg.f_max = priv->spi->max_hz;
  354. plat->cfg.part_type = PART_TYPE_DOS;
  355. plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  356. plat->mmc.cfg = &plat->cfg;
  357. plat->mmc.priv = priv;
  358. plat->mmc.dev = dev;
  359. upriv->mmc = &plat->mmc;
  360. return 0;
  361. }
  362. static int mmc_spi_bind(struct udevice *dev)
  363. {
  364. struct mmc_spi_plat *plat = dev_get_platdata(dev);
  365. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  366. }
  367. static const struct dm_mmc_ops mmc_spi_ops = {
  368. .send_cmd = dm_mmc_spi_request,
  369. .set_ios = dm_mmc_spi_set_ios,
  370. };
  371. static const struct udevice_id dm_mmc_spi_match[] = {
  372. { .compatible = "mmc-spi-slot" },
  373. { /* sentinel */ }
  374. };
  375. U_BOOT_DRIVER(mmc_spi) = {
  376. .name = "mmc_spi",
  377. .id = UCLASS_MMC,
  378. .of_match = dm_mmc_spi_match,
  379. .ops = &mmc_spi_ops,
  380. .probe = mmc_spi_probe,
  381. .bind = mmc_spi_bind,
  382. .platdata_auto_alloc_size = sizeof(struct mmc_spi_plat),
  383. .priv_auto_alloc_size = sizeof(struct mmc_spi_priv),
  384. };