gen_atmel_mci.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010
  4. * Rob Emanuele <rob@emanuele.us>
  5. * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
  6. *
  7. * Original Driver:
  8. * Copyright (C) 2004-2006 Atmel Corporation
  9. */
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <mmc.h>
  14. #include <part.h>
  15. #include <malloc.h>
  16. #include <asm/io.h>
  17. #include <linux/errno.h>
  18. #include <asm/byteorder.h>
  19. #include <asm/arch/clk.h>
  20. #include <asm/arch/hardware.h>
  21. #include "atmel_mci.h"
  22. #ifndef CONFIG_SYS_MMC_CLK_OD
  23. # define CONFIG_SYS_MMC_CLK_OD 150000
  24. #endif
  25. #define MMC_DEFAULT_BLKLEN 512
  26. #if defined(CONFIG_ATMEL_MCI_PORTB)
  27. # define MCI_BUS 1
  28. #else
  29. # define MCI_BUS 0
  30. #endif
  31. #ifdef CONFIG_DM_MMC
  32. struct atmel_mci_plat {
  33. struct mmc mmc;
  34. struct mmc_config cfg;
  35. struct atmel_mci *mci;
  36. };
  37. #endif
  38. struct atmel_mci_priv {
  39. #ifndef CONFIG_DM_MMC
  40. struct mmc_config cfg;
  41. struct atmel_mci *mci;
  42. #endif
  43. unsigned int initialized:1;
  44. unsigned int curr_clk;
  45. #ifdef CONFIG_DM_MMC
  46. ulong bus_clk_rate;
  47. #endif
  48. };
  49. /* Read Atmel MCI IP version */
  50. static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
  51. {
  52. return readl(&mci->version) & 0x00000fff;
  53. }
  54. /*
  55. * Print command and status:
  56. *
  57. * - always when DEBUG is defined
  58. * - on command errors
  59. */
  60. static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
  61. {
  62. debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
  63. cmdr, cmdr & 0x3F, arg, status, msg);
  64. }
  65. static inline void mci_set_blklen(atmel_mci_t *mci, int blklen)
  66. {
  67. unsigned int version = atmel_mci_get_version(mci);
  68. blklen &= 0xfffc;
  69. /* MCI IP version >= 0x200 has blkr */
  70. if (version >= 0x200)
  71. writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->blkr)),
  72. &mci->blkr);
  73. else
  74. writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->mr)), &mci->mr);
  75. }
  76. /* Setup for MCI Clock and Block Size */
  77. #ifdef CONFIG_DM_MMC
  78. static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen)
  79. {
  80. struct atmel_mci_plat *plat = dev_get_platdata(dev);
  81. struct atmel_mci_priv *priv = dev_get_priv(dev);
  82. struct mmc *mmc = &plat->mmc;
  83. u32 bus_hz = priv->bus_clk_rate;
  84. atmel_mci_t *mci = plat->mci;
  85. #else
  86. static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
  87. {
  88. struct atmel_mci_priv *priv = mmc->priv;
  89. u32 bus_hz = get_mci_clk_rate();
  90. atmel_mci_t *mci = priv->mci;
  91. #endif
  92. u32 clkdiv = 255;
  93. unsigned int version = atmel_mci_get_version(mci);
  94. u32 clkodd = 0;
  95. u32 mr;
  96. debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
  97. bus_hz, hz, blklen);
  98. if (hz > 0) {
  99. if (version >= 0x500) {
  100. clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
  101. if (clkdiv > 511)
  102. clkdiv = 511;
  103. clkodd = clkdiv & 1;
  104. clkdiv >>= 1;
  105. debug("mci: setting clock %u Hz, block size %u\n",
  106. bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
  107. } else {
  108. /* find clkdiv yielding a rate <= than requested */
  109. for (clkdiv = 0; clkdiv < 255; clkdiv++) {
  110. if ((bus_hz / (clkdiv + 1) / 2) <= hz)
  111. break;
  112. }
  113. debug("mci: setting clock %u Hz, block size %u\n",
  114. (bus_hz / (clkdiv + 1)) / 2, blklen);
  115. }
  116. }
  117. if (version >= 0x500)
  118. priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2);
  119. else
  120. priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2;
  121. mr = MMCI_BF(CLKDIV, clkdiv);
  122. /* MCI IP version >= 0x200 has R/WPROOF */
  123. if (version >= 0x200)
  124. mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);
  125. /*
  126. * MCI IP version >= 0x500 use bit 16 as clkodd.
  127. * MCI IP version < 0x500 use upper 16 bits for blklen.
  128. */
  129. if (version >= 0x500)
  130. mr |= MMCI_BF(CLKODD, clkodd);
  131. writel(mr, &mci->mr);
  132. mci_set_blklen(mci, blklen);
  133. if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
  134. writel(MMCI_BIT(HSMODE), &mci->cfg);
  135. priv->initialized = 1;
  136. }
  137. /* Return the CMDR with flags for a given command and data packet */
  138. static u32 mci_encode_cmd(
  139. struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
  140. {
  141. u32 cmdr = 0;
  142. /* Default Flags for Errors */
  143. *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
  144. MMCI_BIT(RINDE) | MMCI_BIT(RTOE));
  145. /* Default Flags for the Command */
  146. cmdr |= MMCI_BIT(MAXLAT);
  147. if (data) {
  148. cmdr |= MMCI_BF(TRCMD, 1);
  149. if (data->blocks > 1)
  150. cmdr |= MMCI_BF(TRTYP, 1);
  151. if (data->flags & MMC_DATA_READ)
  152. cmdr |= MMCI_BIT(TRDIR);
  153. }
  154. if (cmd->resp_type & MMC_RSP_CRC)
  155. *error_flags |= MMCI_BIT(RCRCE);
  156. if (cmd->resp_type & MMC_RSP_136)
  157. cmdr |= MMCI_BF(RSPTYP, 2);
  158. else if (cmd->resp_type & MMC_RSP_BUSY)
  159. cmdr |= MMCI_BF(RSPTYP, 3);
  160. else if (cmd->resp_type & MMC_RSP_PRESENT)
  161. cmdr |= MMCI_BF(RSPTYP, 1);
  162. return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
  163. }
  164. /* Entered into function pointer in mci_send_cmd */
  165. static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
  166. {
  167. u32 status;
  168. do {
  169. status = readl(&mci->sr);
  170. if (status & (error_flags | MMCI_BIT(OVRE)))
  171. goto io_fail;
  172. } while (!(status & MMCI_BIT(RXRDY)));
  173. if (status & MMCI_BIT(RXRDY)) {
  174. *data = readl(&mci->rdr);
  175. status = 0;
  176. }
  177. io_fail:
  178. return status;
  179. }
  180. /* Entered into function pointer in mci_send_cmd */
  181. static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
  182. {
  183. u32 status;
  184. do {
  185. status = readl(&mci->sr);
  186. if (status & (error_flags | MMCI_BIT(UNRE)))
  187. goto io_fail;
  188. } while (!(status & MMCI_BIT(TXRDY)));
  189. if (status & MMCI_BIT(TXRDY)) {
  190. writel(*data, &mci->tdr);
  191. status = 0;
  192. }
  193. io_fail:
  194. return status;
  195. }
  196. /*
  197. * Entered into mmc structure during driver init
  198. *
  199. * Sends a command out on the bus and deals with the block data.
  200. * Takes the mmc pointer, a command pointer, and an optional data pointer.
  201. */
  202. #ifdef CONFIG_DM_MMC
  203. static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  204. struct mmc_data *data)
  205. {
  206. struct atmel_mci_plat *plat = dev_get_platdata(dev);
  207. struct atmel_mci_priv *priv = dev_get_priv(dev);
  208. atmel_mci_t *mci = plat->mci;
  209. #else
  210. static int
  211. mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  212. {
  213. struct atmel_mci_priv *priv = mmc->priv;
  214. atmel_mci_t *mci = priv->mci;
  215. #endif
  216. u32 cmdr;
  217. u32 error_flags = 0;
  218. u32 status;
  219. if (!priv->initialized) {
  220. puts ("MCI not initialized!\n");
  221. return -ECOMM;
  222. }
  223. /* Figure out the transfer arguments */
  224. cmdr = mci_encode_cmd(cmd, data, &error_flags);
  225. mci_set_blklen(mci, data->blocksize);
  226. /* For multi blocks read/write, set the block register */
  227. if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
  228. || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
  229. writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
  230. &mci->blkr);
  231. /* Send the command */
  232. writel(cmd->cmdarg, &mci->argr);
  233. writel(cmdr, &mci->cmdr);
  234. #ifdef DEBUG
  235. dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
  236. #endif
  237. /* Wait for the command to complete */
  238. while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
  239. if ((status & error_flags) & MMCI_BIT(RTOE)) {
  240. dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
  241. return -ETIMEDOUT;
  242. } else if (status & error_flags) {
  243. dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
  244. return -ECOMM;
  245. }
  246. /* Copy the response to the response buffer */
  247. if (cmd->resp_type & MMC_RSP_136) {
  248. cmd->response[0] = readl(&mci->rspr);
  249. cmd->response[1] = readl(&mci->rspr1);
  250. cmd->response[2] = readl(&mci->rspr2);
  251. cmd->response[3] = readl(&mci->rspr3);
  252. } else
  253. cmd->response[0] = readl(&mci->rspr);
  254. /* transfer all of the blocks */
  255. if (data) {
  256. u32 word_count, block_count;
  257. u32* ioptr;
  258. u32 i;
  259. u32 (*mci_data_op)
  260. (atmel_mci_t *mci, u32* data, u32 error_flags);
  261. if (data->flags & MMC_DATA_READ) {
  262. mci_data_op = mci_data_read;
  263. ioptr = (u32*)data->dest;
  264. } else {
  265. mci_data_op = mci_data_write;
  266. ioptr = (u32*)data->src;
  267. }
  268. status = 0;
  269. for (block_count = 0;
  270. block_count < data->blocks && !status;
  271. block_count++) {
  272. word_count = 0;
  273. do {
  274. status = mci_data_op(mci, ioptr, error_flags);
  275. word_count++;
  276. ioptr++;
  277. } while (!status && word_count < (data->blocksize/4));
  278. #ifdef DEBUG
  279. if (data->flags & MMC_DATA_READ)
  280. {
  281. u32 cnt = word_count * 4;
  282. printf("Read Data:\n");
  283. print_buffer(0, data->dest + cnt * block_count,
  284. 1, cnt, 0);
  285. }
  286. #endif
  287. if (status) {
  288. dump_cmd(cmdr, cmd->cmdarg, status,
  289. "Data Transfer Failed");
  290. return -ECOMM;
  291. }
  292. }
  293. /* Wait for Transfer End */
  294. i = 0;
  295. do {
  296. status = readl(&mci->sr);
  297. if (status & error_flags) {
  298. dump_cmd(cmdr, cmd->cmdarg, status,
  299. "DTIP Wait Failed");
  300. return -ECOMM;
  301. }
  302. i++;
  303. } while ((status & MMCI_BIT(DTIP)) && i < 10000);
  304. if (status & MMCI_BIT(DTIP)) {
  305. dump_cmd(cmdr, cmd->cmdarg, status,
  306. "XFER DTIP never unset, ignoring");
  307. }
  308. }
  309. /*
  310. * After the switch command, wait for 8 clocks before the next
  311. * command
  312. */
  313. if (cmd->cmdidx == MMC_CMD_SWITCH)
  314. udelay(8*1000000 / priv->curr_clk); /* 8 clk in us */
  315. return 0;
  316. }
  317. #ifdef CONFIG_DM_MMC
  318. static int atmel_mci_set_ios(struct udevice *dev)
  319. {
  320. struct atmel_mci_plat *plat = dev_get_platdata(dev);
  321. struct mmc *mmc = mmc_get_mmc_dev(dev);
  322. atmel_mci_t *mci = plat->mci;
  323. #else
  324. /* Entered into mmc structure during driver init */
  325. static int mci_set_ios(struct mmc *mmc)
  326. {
  327. struct atmel_mci_priv *priv = mmc->priv;
  328. atmel_mci_t *mci = priv->mci;
  329. #endif
  330. int bus_width = mmc->bus_width;
  331. unsigned int version = atmel_mci_get_version(mci);
  332. int busw;
  333. /* Set the clock speed */
  334. #ifdef CONFIG_DM_MMC
  335. mci_set_mode(dev, mmc->clock, MMC_DEFAULT_BLKLEN);
  336. #else
  337. mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
  338. #endif
  339. /*
  340. * set the bus width and select slot for this interface
  341. * there is no capability for multiple slots on the same interface yet
  342. */
  343. if ((version & 0xf00) >= 0x300) {
  344. switch (bus_width) {
  345. case 8:
  346. busw = 3;
  347. break;
  348. case 4:
  349. busw = 2;
  350. break;
  351. default:
  352. busw = 0;
  353. break;
  354. }
  355. writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
  356. } else {
  357. busw = (bus_width == 4) ? 1 : 0;
  358. writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
  359. }
  360. return 0;
  361. }
  362. #ifdef CONFIG_DM_MMC
  363. static int atmel_mci_hw_init(struct udevice *dev)
  364. {
  365. struct atmel_mci_plat *plat = dev_get_platdata(dev);
  366. atmel_mci_t *mci = plat->mci;
  367. #else
  368. /* Entered into mmc structure during driver init */
  369. static int mci_init(struct mmc *mmc)
  370. {
  371. struct atmel_mci_priv *priv = mmc->priv;
  372. atmel_mci_t *mci = priv->mci;
  373. #endif
  374. /* Initialize controller */
  375. writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
  376. writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
  377. writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
  378. writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
  379. /* This delay can be optimized, but stick with max value */
  380. writel(0x7f, &mci->dtor);
  381. /* Disable Interrupts */
  382. writel(~0UL, &mci->idr);
  383. /* Set default clocks and blocklen */
  384. #ifdef CONFIG_DM_MMC
  385. mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
  386. #else
  387. mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
  388. #endif
  389. return 0;
  390. }
  391. #ifndef CONFIG_DM_MMC
  392. static const struct mmc_ops atmel_mci_ops = {
  393. .send_cmd = mci_send_cmd,
  394. .set_ios = mci_set_ios,
  395. .init = mci_init,
  396. };
  397. /*
  398. * This is the only exported function
  399. *
  400. * Call it with the MCI register base address
  401. */
  402. int atmel_mci_init(void *regs)
  403. {
  404. struct mmc *mmc;
  405. struct mmc_config *cfg;
  406. struct atmel_mci_priv *priv;
  407. unsigned int version;
  408. priv = calloc(1, sizeof(*priv));
  409. if (!priv)
  410. return -ENOMEM;
  411. cfg = &priv->cfg;
  412. cfg->name = "mci";
  413. cfg->ops = &atmel_mci_ops;
  414. priv->mci = (struct atmel_mci *)regs;
  415. priv->initialized = 0;
  416. /* need to be able to pass these in on a board by board basis */
  417. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  418. version = atmel_mci_get_version(priv->mci);
  419. if ((version & 0xf00) >= 0x300) {
  420. cfg->host_caps = MMC_MODE_8BIT;
  421. cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  422. }
  423. cfg->host_caps |= MMC_MODE_4BIT;
  424. /*
  425. * min and max frequencies determined by
  426. * max and min of clock divider
  427. */
  428. cfg->f_min = get_mci_clk_rate() / (2*256);
  429. cfg->f_max = get_mci_clk_rate() / (2*1);
  430. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  431. mmc = mmc_create(cfg, priv);
  432. if (mmc == NULL) {
  433. free(priv);
  434. return -ENODEV;
  435. }
  436. /* NOTE: possibly leaking the priv structure */
  437. return 0;
  438. }
  439. #endif
  440. #ifdef CONFIG_DM_MMC
  441. static const struct dm_mmc_ops atmel_mci_mmc_ops = {
  442. .send_cmd = atmel_mci_send_cmd,
  443. .set_ios = atmel_mci_set_ios,
  444. };
  445. static void atmel_mci_setup_cfg(struct udevice *dev)
  446. {
  447. struct atmel_mci_plat *plat = dev_get_platdata(dev);
  448. struct atmel_mci_priv *priv = dev_get_priv(dev);
  449. struct mmc_config *cfg;
  450. u32 version;
  451. cfg = &plat->cfg;
  452. cfg->name = "Atmel mci";
  453. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  454. /*
  455. * If the version is above 3.0, the capabilities of the 8-bit
  456. * bus width and high speed are supported.
  457. */
  458. version = atmel_mci_get_version(plat->mci);
  459. if ((version & 0xf00) >= 0x300) {
  460. cfg->host_caps = MMC_MODE_8BIT |
  461. MMC_MODE_HS | MMC_MODE_HS_52MHz;
  462. }
  463. cfg->host_caps |= MMC_MODE_4BIT;
  464. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  465. cfg->f_min = priv->bus_clk_rate / (2 * 256);
  466. cfg->f_max = priv->bus_clk_rate / 2;
  467. }
  468. static int atmel_mci_enable_clk(struct udevice *dev)
  469. {
  470. struct atmel_mci_priv *priv = dev_get_priv(dev);
  471. struct clk clk;
  472. ulong clk_rate;
  473. int ret = 0;
  474. ret = clk_get_by_index(dev, 0, &clk);
  475. if (ret) {
  476. ret = -EINVAL;
  477. goto failed;
  478. }
  479. ret = clk_enable(&clk);
  480. if (ret)
  481. goto failed;
  482. clk_rate = clk_get_rate(&clk);
  483. if (!clk_rate) {
  484. ret = -EINVAL;
  485. goto failed;
  486. }
  487. priv->bus_clk_rate = clk_rate;
  488. failed:
  489. clk_free(&clk);
  490. return ret;
  491. }
  492. static int atmel_mci_probe(struct udevice *dev)
  493. {
  494. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  495. struct atmel_mci_plat *plat = dev_get_platdata(dev);
  496. struct mmc *mmc;
  497. int ret;
  498. ret = atmel_mci_enable_clk(dev);
  499. if (ret)
  500. return ret;
  501. plat->mci = (struct atmel_mci *)devfdt_get_addr_ptr(dev);
  502. atmel_mci_setup_cfg(dev);
  503. mmc = &plat->mmc;
  504. mmc->cfg = &plat->cfg;
  505. mmc->dev = dev;
  506. upriv->mmc = mmc;
  507. atmel_mci_hw_init(dev);
  508. return 0;
  509. }
  510. static int atmel_mci_bind(struct udevice *dev)
  511. {
  512. struct atmel_mci_plat *plat = dev_get_platdata(dev);
  513. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  514. }
  515. static const struct udevice_id atmel_mci_ids[] = {
  516. { .compatible = "atmel,hsmci" },
  517. { }
  518. };
  519. U_BOOT_DRIVER(atmel_mci) = {
  520. .name = "atmel-mci",
  521. .id = UCLASS_MMC,
  522. .of_match = atmel_mci_ids,
  523. .bind = atmel_mci_bind,
  524. .probe = atmel_mci_probe,
  525. .platdata_auto_alloc_size = sizeof(struct atmel_mci_plat),
  526. .priv_auto_alloc_size = sizeof(struct atmel_mci_priv),
  527. .ops = &atmel_mci_mmc_ops,
  528. };
  529. #endif