mxs_ocotp.c 6.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 OCOTP Driver
  4. *
  5. * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  6. *
  7. * Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block
  8. * used in i.MX6 . While these blocks are very similar at the first
  9. * glance, by digging deeper, one will notice differences (like the
  10. * tight dependence on MXS power block, some completely new registers
  11. * etc.) which would make common driver an ifdef nightmare :-(
  12. */
  13. #include <common.h>
  14. #include <fuse.h>
  15. #include <linux/errno.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/imx-regs.h>
  19. #include <asm/arch/sys_proto.h>
  20. #define MXS_OCOTP_TIMEOUT 100000
  21. static struct mxs_ocotp_regs *ocotp_regs =
  22. (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
  23. static struct mxs_power_regs *power_regs =
  24. (struct mxs_power_regs *)MXS_POWER_BASE;
  25. static struct mxs_clkctrl_regs *clkctrl_regs =
  26. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  27. static int mxs_ocotp_wait_busy_clear(void)
  28. {
  29. uint32_t reg;
  30. int timeout = MXS_OCOTP_TIMEOUT;
  31. while (--timeout) {
  32. reg = readl(&ocotp_regs->hw_ocotp_ctrl);
  33. if (!(reg & OCOTP_CTRL_BUSY))
  34. break;
  35. udelay(10);
  36. }
  37. if (!timeout)
  38. return -EINVAL;
  39. /* Wait a little as per FSL datasheet's 'write postamble' section. */
  40. udelay(10);
  41. return 0;
  42. }
  43. static void mxs_ocotp_clear_error(void)
  44. {
  45. writel(OCOTP_CTRL_ERROR, &ocotp_regs->hw_ocotp_ctrl_clr);
  46. }
  47. static int mxs_ocotp_read_bank_open(bool open)
  48. {
  49. int ret = 0;
  50. if (open) {
  51. writel(OCOTP_CTRL_RD_BANK_OPEN,
  52. &ocotp_regs->hw_ocotp_ctrl_set);
  53. /*
  54. * Wait before polling the BUSY bit, since the BUSY bit might
  55. * be asserted only after a few HCLK cycles and if we were to
  56. * poll immediatelly, we could miss the busy bit.
  57. */
  58. udelay(10);
  59. ret = mxs_ocotp_wait_busy_clear();
  60. } else {
  61. writel(OCOTP_CTRL_RD_BANK_OPEN,
  62. &ocotp_regs->hw_ocotp_ctrl_clr);
  63. }
  64. return ret;
  65. }
  66. static void mxs_ocotp_scale_vddio(bool enter, uint32_t *val)
  67. {
  68. uint32_t scale_val;
  69. if (enter) {
  70. /*
  71. * Enter the fuse programming VDDIO voltage setup. We start
  72. * scaling the voltage from it's current value down to 2.8V
  73. * which is the one and only correct voltage for programming
  74. * the OCOTP fuses (according to datasheet).
  75. */
  76. scale_val = readl(&power_regs->hw_power_vddioctrl);
  77. scale_val &= POWER_VDDIOCTRL_TRG_MASK;
  78. /* Return the original voltage. */
  79. *val = scale_val;
  80. /*
  81. * Start scaling VDDIO down to 0x2, which is 2.8V . Actually,
  82. * the value 0x0 should be 2.8V, but that's not the case on
  83. * most designs due to load etc., so we play safe. Undervolt
  84. * can actually cause incorrect programming of the fuses and
  85. * or reboots of the board.
  86. */
  87. while (scale_val > 2) {
  88. clrsetbits_le32(&power_regs->hw_power_vddioctrl,
  89. POWER_VDDIOCTRL_TRG_MASK, --scale_val);
  90. udelay(500);
  91. }
  92. } else {
  93. /* Start scaling VDDIO up to original value . */
  94. for (scale_val = 2; scale_val <= *val; scale_val++) {
  95. clrsetbits_le32(&power_regs->hw_power_vddioctrl,
  96. POWER_VDDIOCTRL_TRG_MASK, scale_val);
  97. udelay(500);
  98. }
  99. }
  100. mdelay(10);
  101. }
  102. static int mxs_ocotp_wait_hclk_ready(void)
  103. {
  104. uint32_t reg, timeout = MXS_OCOTP_TIMEOUT;
  105. while (--timeout) {
  106. reg = readl(&clkctrl_regs->hw_clkctrl_hbus);
  107. if (!(reg & CLKCTRL_HBUS_ASM_BUSY))
  108. break;
  109. }
  110. if (!timeout)
  111. return -EINVAL;
  112. return 0;
  113. }
  114. static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
  115. {
  116. uint32_t scale_val;
  117. int ret;
  118. ret = mxs_ocotp_wait_hclk_ready();
  119. if (ret)
  120. return ret;
  121. /* Set CPU bypass */
  122. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  123. &clkctrl_regs->hw_clkctrl_clkseq_set);
  124. if (enter) {
  125. /* Return the original HCLK clock speed. */
  126. *val = readl(&clkctrl_regs->hw_clkctrl_hbus);
  127. *val &= CLKCTRL_HBUS_DIV_MASK;
  128. *val >>= CLKCTRL_HBUS_DIV_OFFSET;
  129. /* Scale the HCLK to 454/19 = 23.9 MHz . */
  130. scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
  131. scale_val &= CLKCTRL_HBUS_DIV_MASK;
  132. } else {
  133. /* Scale the HCLK back to original frequency. */
  134. scale_val = (~(*val)) << CLKCTRL_HBUS_DIV_OFFSET;
  135. scale_val &= CLKCTRL_HBUS_DIV_MASK;
  136. }
  137. writel(CLKCTRL_HBUS_DIV_MASK,
  138. &clkctrl_regs->hw_clkctrl_hbus_set);
  139. writel(scale_val,
  140. &clkctrl_regs->hw_clkctrl_hbus_clr);
  141. mdelay(10);
  142. ret = mxs_ocotp_wait_hclk_ready();
  143. if (ret)
  144. return ret;
  145. /* Disable CPU bypass */
  146. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  147. &clkctrl_regs->hw_clkctrl_clkseq_clr);
  148. mdelay(10);
  149. return 0;
  150. }
  151. static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
  152. {
  153. uint32_t hclk_val, vddio_val;
  154. int ret;
  155. mxs_ocotp_clear_error();
  156. /* Make sure the banks are closed for reading. */
  157. ret = mxs_ocotp_read_bank_open(0);
  158. if (ret) {
  159. puts("Failed closing banks for reading!\n");
  160. return ret;
  161. }
  162. ret = mxs_ocotp_scale_hclk(1, &hclk_val);
  163. if (ret) {
  164. puts("Failed scaling down the HCLK!\n");
  165. return ret;
  166. }
  167. mxs_ocotp_scale_vddio(1, &vddio_val);
  168. ret = mxs_ocotp_wait_busy_clear();
  169. if (ret) {
  170. puts("Failed waiting for ready state!\n");
  171. goto fail;
  172. }
  173. /* Program the fuse address */
  174. writel(addr | OCOTP_CTRL_WR_UNLOCK_KEY, &ocotp_regs->hw_ocotp_ctrl);
  175. /* Program the data. */
  176. writel(mask, &ocotp_regs->hw_ocotp_data);
  177. udelay(10);
  178. ret = mxs_ocotp_wait_busy_clear();
  179. if (ret) {
  180. puts("Failed waiting for ready state!\n");
  181. goto fail;
  182. }
  183. /* Check for errors */
  184. if (readl(&ocotp_regs->hw_ocotp_ctrl) & OCOTP_CTRL_ERROR) {
  185. puts("Failed writing fuses!\n");
  186. ret = -EPERM;
  187. goto fail;
  188. }
  189. fail:
  190. mxs_ocotp_scale_vddio(0, &vddio_val);
  191. if (mxs_ocotp_scale_hclk(0, &hclk_val))
  192. puts("Failed scaling up the HCLK!\n");
  193. return ret;
  194. }
  195. static int mxs_ocotp_read_fuse(uint32_t reg, uint32_t *val)
  196. {
  197. int ret;
  198. /* Register offset from CUST0 */
  199. reg = ((uint32_t)&ocotp_regs->hw_ocotp_cust0) + (reg << 4);
  200. ret = mxs_ocotp_wait_busy_clear();
  201. if (ret) {
  202. puts("Failed waiting for ready state!\n");
  203. return ret;
  204. }
  205. mxs_ocotp_clear_error();
  206. ret = mxs_ocotp_read_bank_open(1);
  207. if (ret) {
  208. puts("Failed opening banks for reading!\n");
  209. return ret;
  210. }
  211. *val = readl(reg);
  212. ret = mxs_ocotp_read_bank_open(0);
  213. if (ret) {
  214. puts("Failed closing banks for reading!\n");
  215. return ret;
  216. }
  217. return ret;
  218. }
  219. static int mxs_ocotp_valid(u32 bank, u32 word)
  220. {
  221. if (bank > 4)
  222. return -EINVAL;
  223. if (word > 7)
  224. return -EINVAL;
  225. return 0;
  226. }
  227. /*
  228. * The 'fuse' command API
  229. */
  230. int fuse_read(u32 bank, u32 word, u32 *val)
  231. {
  232. int ret;
  233. ret = mxs_ocotp_valid(bank, word);
  234. if (ret)
  235. return ret;
  236. return mxs_ocotp_read_fuse((bank << 3) | word, val);
  237. }
  238. int fuse_prog(u32 bank, u32 word, u32 val)
  239. {
  240. int ret;
  241. ret = mxs_ocotp_valid(bank, word);
  242. if (ret)
  243. return ret;
  244. return mxs_ocotp_write_fuse((bank << 3) | word, val);
  245. }
  246. int fuse_sense(u32 bank, u32 word, u32 *val)
  247. {
  248. /* We do not support sensing :-( */
  249. return -EINVAL;
  250. }
  251. int fuse_override(u32 bank, u32 word, u32 val)
  252. {
  253. /* We do not support overriding :-( */
  254. return -EINVAL;
  255. }