fsl_sata.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. * Author: Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <console.h>
  10. #include <cpu_func.h>
  11. #include <asm/io.h>
  12. #include <asm/processor.h>
  13. #include <asm/fsl_serdes.h>
  14. #include <malloc.h>
  15. #include <libata.h>
  16. #include <fis.h>
  17. #include <sata.h>
  18. #include "fsl_sata.h"
  19. #if CONFIG_IS_ENABLED(BLK)
  20. #include <dm.h>
  21. #include <ahci.h>
  22. #include <blk.h>
  23. #else
  24. #ifndef CONFIG_SYS_SATA1_FLAGS
  25. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  26. #endif
  27. #ifndef CONFIG_SYS_SATA2_FLAGS
  28. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  29. #endif
  30. static struct fsl_sata_info fsl_sata_info[] = {
  31. #ifdef CONFIG_SATA1
  32. {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
  33. #else
  34. {0, 0},
  35. #endif
  36. #ifdef CONFIG_SATA2
  37. {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
  38. #else
  39. {0, 0},
  40. #endif
  41. };
  42. #endif
  43. static inline void sdelay(unsigned long sec)
  44. {
  45. unsigned long i;
  46. for (i = 0; i < sec; i++)
  47. mdelay(1000);
  48. }
  49. static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
  50. {
  51. printf("Status FIS dump:\n\r");
  52. printf("fis_type: %02x\n\r", s->fis_type);
  53. printf("pm_port_i: %02x\n\r", s->pm_port_i);
  54. printf("status: %02x\n\r", s->status);
  55. printf("error: %02x\n\r", s->error);
  56. printf("lba_low: %02x\n\r", s->lba_low);
  57. printf("lba_mid: %02x\n\r", s->lba_mid);
  58. printf("lba_high: %02x\n\r", s->lba_high);
  59. printf("device: %02x\n\r", s->device);
  60. printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
  61. printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
  62. printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
  63. printf("res1: %02x\n\r", s->res1);
  64. printf("sector_count: %02x\n\r", s->sector_count);
  65. printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
  66. }
  67. static int ata_wait_register(unsigned __iomem *addr, u32 mask,
  68. u32 val, u32 timeout_msec)
  69. {
  70. int i;
  71. u32 temp;
  72. for (i = 0; (((temp = in_le32(addr)) & mask) != val)
  73. && i < timeout_msec; i++)
  74. mdelay(1);
  75. return (i < timeout_msec) ? 0 : -1;
  76. }
  77. #if !CONFIG_IS_ENABLED(BLK)
  78. int init_sata(int dev)
  79. #else
  80. static int init_sata(struct fsl_ata_priv *priv, int dev)
  81. #endif
  82. {
  83. u32 length, align;
  84. cmd_hdr_tbl_t *cmd_hdr;
  85. u32 cda;
  86. u32 val32;
  87. fsl_sata_reg_t __iomem *reg;
  88. u32 sig;
  89. int i;
  90. fsl_sata_t *sata;
  91. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  92. printf("the sata index %d is out of ranges\n\r", dev);
  93. return -1;
  94. }
  95. #ifdef CONFIG_MPC85xx
  96. if ((dev == 0) && (!is_serdes_configured(SATA1))) {
  97. printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
  98. return -1;
  99. }
  100. if ((dev == 1) && (!is_serdes_configured(SATA2))) {
  101. printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
  102. return -1;
  103. }
  104. #endif
  105. /* Allocate SATA device driver struct */
  106. sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
  107. if (!sata) {
  108. printf("alloc the sata device struct failed\n\r");
  109. return -1;
  110. }
  111. /* Zero all of the device driver struct */
  112. memset((void *)sata, 0, sizeof(fsl_sata_t));
  113. snprintf(sata->name, 12, "SATA%d:\n", dev);
  114. /* Set the controller register base address to device struct */
  115. #if !CONFIG_IS_ENABLED(BLK)
  116. sata_dev_desc[dev].priv = (void *)sata;
  117. reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
  118. sata->dma_flag = fsl_sata_info[dev].flags;
  119. #else
  120. reg = (fsl_sata_reg_t *)(priv->base + priv->offset * dev);
  121. sata->dma_flag = priv->flag;
  122. priv->fsl_sata = sata;
  123. #endif
  124. sata->reg_base = reg;
  125. /* Allocate the command header table, 4 bytes aligned */
  126. length = sizeof(struct cmd_hdr_tbl);
  127. align = SATA_HC_CMD_HDR_TBL_ALIGN;
  128. sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
  129. if (!sata->cmd_hdr_tbl_offset) {
  130. printf("alloc the command header failed\n\r");
  131. return -1;
  132. }
  133. cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
  134. & ~(align - 1));
  135. sata->cmd_hdr = cmd_hdr;
  136. /* Zero all of the command header table */
  137. memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
  138. /* Allocate command descriptor for all command */
  139. length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
  140. align = SATA_HC_CMD_DESC_ALIGN;
  141. sata->cmd_desc_offset = (void *)malloc(length + align);
  142. if (!sata->cmd_desc_offset) {
  143. printf("alloc the command descriptor failed\n\r");
  144. return -1;
  145. }
  146. sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
  147. & ~(align - 1));
  148. /* Zero all of command descriptor */
  149. memset((void *)sata->cmd_desc_offset, 0, length + align);
  150. /* Link the command descriptor to command header */
  151. for (i = 0; i < SATA_HC_MAX_CMD; i++) {
  152. cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
  153. & ~(CMD_HDR_CDA_ALIGN - 1);
  154. cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
  155. }
  156. /* To have safe state, force the controller offline */
  157. val32 = in_le32(&reg->hcontrol);
  158. val32 &= ~HCONTROL_ONOFF;
  159. val32 |= HCONTROL_FORCE_OFFLINE;
  160. out_le32(&reg->hcontrol, val32);
  161. /* Wait the controller offline */
  162. ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
  163. /* Set the command header base address to CHBA register to tell DMA */
  164. out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
  165. /* Snoop for the command header */
  166. val32 = in_le32(&reg->hcontrol);
  167. val32 |= HCONTROL_HDR_SNOOP;
  168. out_le32(&reg->hcontrol, val32);
  169. /* Disable all of interrupts */
  170. val32 = in_le32(&reg->hcontrol);
  171. val32 &= ~HCONTROL_INT_EN_ALL;
  172. out_le32(&reg->hcontrol, val32);
  173. /* Clear all of interrupts */
  174. val32 = in_le32(&reg->hstatus);
  175. out_le32(&reg->hstatus, val32);
  176. /* Set the ICC, no interrupt coalescing */
  177. out_le32(&reg->icc, 0x01000000);
  178. /* No PM attatched, the SATA device direct connect */
  179. out_le32(&reg->cqpmp, 0);
  180. /* Clear SError register */
  181. val32 = in_le32(&reg->serror);
  182. out_le32(&reg->serror, val32);
  183. /* Clear CER register */
  184. val32 = in_le32(&reg->cer);
  185. out_le32(&reg->cer, val32);
  186. /* Clear DER register */
  187. val32 = in_le32(&reg->der);
  188. out_le32(&reg->der, val32);
  189. /* No device detection or initialization action requested */
  190. out_le32(&reg->scontrol, 0x00000300);
  191. /* Configure the transport layer, default value */
  192. out_le32(&reg->transcfg, 0x08000016);
  193. /* Configure the link layer, default value */
  194. out_le32(&reg->linkcfg, 0x0000ff34);
  195. /* Bring the controller online */
  196. val32 = in_le32(&reg->hcontrol);
  197. val32 |= HCONTROL_ONOFF;
  198. out_le32(&reg->hcontrol, val32);
  199. mdelay(100);
  200. /* print sata device name */
  201. if (!dev)
  202. printf("%s ", sata->name);
  203. else
  204. printf(" %s ", sata->name);
  205. /* Wait PHY RDY signal changed for 500ms */
  206. ata_wait_register(&reg->hstatus, HSTATUS_PHY_RDY,
  207. HSTATUS_PHY_RDY, 500);
  208. /* Check PHYRDY */
  209. val32 = in_le32(&reg->hstatus);
  210. if (val32 & HSTATUS_PHY_RDY) {
  211. sata->link = 1;
  212. } else {
  213. sata->link = 0;
  214. printf("(No RDY)\n\r");
  215. return -1;
  216. }
  217. /* Wait for signature updated, which is 1st D2H */
  218. ata_wait_register(&reg->hstatus, HSTATUS_SIGNATURE,
  219. HSTATUS_SIGNATURE, 10000);
  220. if (val32 & HSTATUS_SIGNATURE) {
  221. sig = in_le32(&reg->sig);
  222. debug("Signature updated, the sig =%08x\n\r", sig);
  223. sata->ata_device_type = ata_dev_classify(sig);
  224. }
  225. /* Check the speed */
  226. val32 = in_le32(&reg->sstatus);
  227. if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
  228. printf("(1.5 Gbps)\n\r");
  229. else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
  230. printf("(3 Gbps)\n\r");
  231. return 0;
  232. }
  233. int reset_sata(int dev)
  234. {
  235. return 0;
  236. }
  237. static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
  238. {
  239. printf("\n\rSATA: %08x\n\r", (u32)reg);
  240. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  241. printf("CAR: %08x\n\r", in_le32(&reg->car));
  242. printf("CCR: %08x\n\r", in_le32(&reg->ccr));
  243. printf("CER: %08x\n\r", in_le32(&reg->cer));
  244. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  245. printf("DER: %08x\n\r", in_le32(&reg->der));
  246. printf("CHBA: %08x\n\r", in_le32(&reg->chba));
  247. printf("HStatus: %08x\n\r", in_le32(&reg->hstatus));
  248. printf("HControl: %08x\n\r", in_le32(&reg->hcontrol));
  249. printf("CQPMP: %08x\n\r", in_le32(&reg->cqpmp));
  250. printf("SIG: %08x\n\r", in_le32(&reg->sig));
  251. printf("ICC: %08x\n\r", in_le32(&reg->icc));
  252. printf("SStatus: %08x\n\r", in_le32(&reg->sstatus));
  253. printf("SError: %08x\n\r", in_le32(&reg->serror));
  254. printf("SControl: %08x\n\r", in_le32(&reg->scontrol));
  255. printf("SNotification: %08x\n\r", in_le32(&reg->snotification));
  256. printf("TransCfg: %08x\n\r", in_le32(&reg->transcfg));
  257. printf("TransStatus: %08x\n\r", in_le32(&reg->transstatus));
  258. printf("LinkCfg: %08x\n\r", in_le32(&reg->linkcfg));
  259. printf("LinkCfg1: %08x\n\r", in_le32(&reg->linkcfg1));
  260. printf("LinkCfg2: %08x\n\r", in_le32(&reg->linkcfg2));
  261. printf("LinkStatus: %08x\n\r", in_le32(&reg->linkstatus));
  262. printf("LinkStatus1: %08x\n\r", in_le32(&reg->linkstatus1));
  263. printf("PhyCtrlCfg: %08x\n\r", in_le32(&reg->phyctrlcfg));
  264. printf("SYSPR: %08x\n\r", in_be32(&reg->syspr));
  265. }
  266. static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  267. int is_ncq, int tag, u8 *buffer, u32 len)
  268. {
  269. cmd_hdr_entry_t *cmd_hdr;
  270. cmd_desc_t *cmd_desc;
  271. sata_fis_h2d_t *h2d;
  272. prd_entry_t *prde;
  273. u32 ext_c_ddc;
  274. u32 prde_count;
  275. u32 val32;
  276. u32 ttl;
  277. fsl_sata_reg_t __iomem *reg = sata->reg_base;
  278. int i;
  279. /* Check xfer length */
  280. if (len > SATA_HC_MAX_XFER_LEN) {
  281. printf("max transfer length is 64MB\n\r");
  282. return 0;
  283. }
  284. /* Setup the command descriptor */
  285. cmd_desc = sata->cmd_desc + tag;
  286. /* Get the pointer cfis of command descriptor */
  287. h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
  288. /* Zero the cfis of command descriptor */
  289. memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
  290. /* Copy the cfis from user to command descriptor */
  291. h2d->fis_type = cfis->fis_type;
  292. h2d->pm_port_c = cfis->pm_port_c;
  293. h2d->command = cfis->command;
  294. h2d->features = cfis->features;
  295. h2d->features_exp = cfis->features_exp;
  296. h2d->lba_low = cfis->lba_low;
  297. h2d->lba_mid = cfis->lba_mid;
  298. h2d->lba_high = cfis->lba_high;
  299. h2d->lba_low_exp = cfis->lba_low_exp;
  300. h2d->lba_mid_exp = cfis->lba_mid_exp;
  301. h2d->lba_high_exp = cfis->lba_high_exp;
  302. if (!is_ncq) {
  303. h2d->sector_count = cfis->sector_count;
  304. h2d->sector_count_exp = cfis->sector_count_exp;
  305. } else { /* NCQ */
  306. h2d->sector_count = (u8)(tag << 3);
  307. }
  308. h2d->device = cfis->device;
  309. h2d->control = cfis->control;
  310. /* Setup the PRD table */
  311. prde = (prd_entry_t *)cmd_desc->prdt;
  312. memset((void *)prde, 0, sizeof(struct prdt));
  313. prde_count = 0;
  314. ttl = len;
  315. for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
  316. if (!len)
  317. break;
  318. prde->dba = cpu_to_le32((u32)buffer & ~0x3);
  319. debug("dba = %08x\n\r", (u32)buffer);
  320. if (len < PRD_ENTRY_MAX_XFER_SZ) {
  321. ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
  322. debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
  323. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  324. prde_count++;
  325. prde++;
  326. break;
  327. } else {
  328. ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
  329. debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
  330. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  331. buffer += PRD_ENTRY_MAX_XFER_SZ;
  332. len -= PRD_ENTRY_MAX_XFER_SZ;
  333. prde_count++;
  334. prde++;
  335. }
  336. }
  337. /* Setup the command slot of cmd hdr */
  338. cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
  339. cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
  340. val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
  341. val32 |= sizeof(sata_fis_h2d_t);
  342. cmd_hdr->prde_fis_len = cpu_to_le32(val32);
  343. cmd_hdr->ttl = cpu_to_le32(ttl);
  344. if (!is_ncq) {
  345. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
  346. } else {
  347. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
  348. }
  349. tag &= CMD_HDR_ATTR_TAG;
  350. val32 |= tag;
  351. debug("attribute = %08x\n\r", val32);
  352. cmd_hdr->attribute = cpu_to_le32(val32);
  353. /* Make sure cmd desc and cmd slot valid before command issue */
  354. sync();
  355. /* PMP*/
  356. val32 = (u32)(h2d->pm_port_c & 0x0f);
  357. out_le32(&reg->cqpmp, val32);
  358. /* Wait no active */
  359. if (ata_wait_register(&reg->car, (1 << tag), 0, 10000))
  360. printf("Wait no active time out\n\r");
  361. /* Issue command */
  362. if (!(in_le32(&reg->cqr) & (1 << tag))) {
  363. val32 = 1 << tag;
  364. out_le32(&reg->cqr, val32);
  365. }
  366. /* Wait command completed for 10s */
  367. if (ata_wait_register(&reg->ccr, (1 << tag), (1 << tag), 10000)) {
  368. if (!is_ncq)
  369. printf("Non-NCQ command time out\n\r");
  370. else
  371. printf("NCQ command time out\n\r");
  372. }
  373. val32 = in_le32(&reg->cer);
  374. if (val32) {
  375. u32 der;
  376. fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
  377. printf("CE at device\n\r");
  378. fsl_sata_dump_regs(reg);
  379. der = in_le32(&reg->der);
  380. out_le32(&reg->cer, val32);
  381. out_le32(&reg->der, der);
  382. }
  383. /* Clear complete flags */
  384. val32 = in_le32(&reg->ccr);
  385. out_le32(&reg->ccr, val32);
  386. return len;
  387. }
  388. static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  389. int tag, u8 *buffer, u32 len)
  390. {
  391. return 0;
  392. }
  393. static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  394. enum cmd_type command_type, int tag, u8 *buffer, u32 len)
  395. {
  396. int rc;
  397. if (tag > SATA_HC_MAX_CMD || tag < 0) {
  398. printf("tag is out of range, tag=%d\n\r", tag);
  399. return -1;
  400. }
  401. switch (command_type) {
  402. case CMD_ATA:
  403. rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
  404. return rc;
  405. case CMD_RESET:
  406. rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
  407. return rc;
  408. case CMD_NCQ:
  409. rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
  410. return rc;
  411. case CMD_ATAPI:
  412. case CMD_VENDOR_BIST:
  413. case CMD_BIST:
  414. printf("not support now\n\r");
  415. return -1;
  416. default:
  417. break;
  418. }
  419. return -1;
  420. }
  421. static void fsl_sata_xfer_mode(fsl_sata_t *sata, u16 *id)
  422. {
  423. sata->pio = id[ATA_ID_PIO_MODES];
  424. sata->mwdma = id[ATA_ID_MWDMA_MODES];
  425. sata->udma = id[ATA_ID_UDMA_MODES];
  426. debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
  427. }
  428. static void fsl_sata_set_features(fsl_sata_t *sata)
  429. {
  430. struct sata_fis_h2d h2d, *cfis = &h2d;
  431. u8 udma_cap;
  432. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  433. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  434. cfis->pm_port_c = 0x80; /* is command */
  435. cfis->command = ATA_CMD_SET_FEATURES;
  436. cfis->features = SETFEATURES_XFER;
  437. /* First check the device capablity */
  438. udma_cap = (u8)(sata->udma & 0xff);
  439. debug("udma_cap %02x\n\r", udma_cap);
  440. if (udma_cap == ATA_UDMA6)
  441. cfis->sector_count = XFER_UDMA_6;
  442. if (udma_cap == ATA_UDMA5)
  443. cfis->sector_count = XFER_UDMA_5;
  444. if (udma_cap == ATA_UDMA4)
  445. cfis->sector_count = XFER_UDMA_4;
  446. if (udma_cap == ATA_UDMA3)
  447. cfis->sector_count = XFER_UDMA_3;
  448. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  449. }
  450. static u32 fsl_sata_rw_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt, u8 *buffer,
  451. int is_write)
  452. {
  453. struct sata_fis_h2d h2d, *cfis = &h2d;
  454. u32 block;
  455. block = start;
  456. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  457. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  458. cfis->pm_port_c = 0x80; /* is command */
  459. cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  460. cfis->device = ATA_LBA;
  461. cfis->device |= (block >> 24) & 0xf;
  462. cfis->lba_high = (block >> 16) & 0xff;
  463. cfis->lba_mid = (block >> 8) & 0xff;
  464. cfis->lba_low = block & 0xff;
  465. cfis->sector_count = (u8)(blkcnt & 0xff);
  466. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
  467. return blkcnt;
  468. }
  469. static void fsl_sata_flush_cache(fsl_sata_t *sata)
  470. {
  471. struct sata_fis_h2d h2d, *cfis = &h2d;
  472. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  473. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  474. cfis->pm_port_c = 0x80; /* is command */
  475. cfis->command = ATA_CMD_FLUSH;
  476. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  477. }
  478. static u32 fsl_sata_rw_cmd_ext(fsl_sata_t *sata, u32 start, u32 blkcnt,
  479. u8 *buffer, int is_write)
  480. {
  481. struct sata_fis_h2d h2d, *cfis = &h2d;
  482. u64 block;
  483. block = (u64)start;
  484. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  485. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  486. cfis->pm_port_c = 0x80; /* is command */
  487. cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
  488. : ATA_CMD_READ_EXT;
  489. cfis->lba_high_exp = (block >> 40) & 0xff;
  490. cfis->lba_mid_exp = (block >> 32) & 0xff;
  491. cfis->lba_low_exp = (block >> 24) & 0xff;
  492. cfis->lba_high = (block >> 16) & 0xff;
  493. cfis->lba_mid = (block >> 8) & 0xff;
  494. cfis->lba_low = block & 0xff;
  495. cfis->device = ATA_LBA;
  496. cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
  497. cfis->sector_count = blkcnt & 0xff;
  498. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
  499. return blkcnt;
  500. }
  501. static u32 fsl_sata_rw_ncq_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
  502. u8 *buffer, int is_write)
  503. {
  504. struct sata_fis_h2d h2d, *cfis = &h2d;
  505. int ncq_channel;
  506. u64 block;
  507. if (sata->lba48 != 1) {
  508. printf("execute FPDMA command on non-LBA48 hard disk\n\r");
  509. return -1;
  510. }
  511. block = (u64)start;
  512. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  513. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  514. cfis->pm_port_c = 0x80; /* is command */
  515. cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
  516. : ATA_CMD_FPDMA_READ;
  517. cfis->lba_high_exp = (block >> 40) & 0xff;
  518. cfis->lba_mid_exp = (block >> 32) & 0xff;
  519. cfis->lba_low_exp = (block >> 24) & 0xff;
  520. cfis->lba_high = (block >> 16) & 0xff;
  521. cfis->lba_mid = (block >> 8) & 0xff;
  522. cfis->lba_low = block & 0xff;
  523. cfis->device = ATA_LBA;
  524. cfis->features_exp = (blkcnt >> 8) & 0xff;
  525. cfis->features = blkcnt & 0xff;
  526. if (sata->queue_depth >= SATA_HC_MAX_CMD)
  527. ncq_channel = SATA_HC_MAX_CMD - 1;
  528. else
  529. ncq_channel = sata->queue_depth - 1;
  530. /* Use the latest queue */
  531. fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
  532. return blkcnt;
  533. }
  534. static void fsl_sata_flush_cache_ext(fsl_sata_t *sata)
  535. {
  536. struct sata_fis_h2d h2d, *cfis = &h2d;
  537. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  538. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  539. cfis->pm_port_c = 0x80; /* is command */
  540. cfis->command = ATA_CMD_FLUSH_EXT;
  541. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  542. }
  543. static void fsl_sata_init_wcache(fsl_sata_t *sata, u16 *id)
  544. {
  545. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  546. sata->wcache = 1;
  547. if (ata_id_has_flush(id))
  548. sata->flush = 1;
  549. if (ata_id_has_flush_ext(id))
  550. sata->flush_ext = 1;
  551. }
  552. static u32 ata_low_level_rw_lba48(fsl_sata_t *sata, u32 blknr, lbaint_t blkcnt,
  553. const void *buffer, int is_write)
  554. {
  555. u32 start, blks;
  556. u8 *addr;
  557. int max_blks;
  558. start = blknr;
  559. blks = blkcnt;
  560. addr = (u8 *)buffer;
  561. max_blks = ATA_MAX_SECTORS_LBA48;
  562. do {
  563. if (blks > max_blks) {
  564. if (sata->dma_flag != FLAGS_FPDMA)
  565. fsl_sata_rw_cmd_ext(sata, start, max_blks, addr,
  566. is_write);
  567. else
  568. fsl_sata_rw_ncq_cmd(sata, start, max_blks, addr,
  569. is_write);
  570. start += max_blks;
  571. blks -= max_blks;
  572. addr += ATA_SECT_SIZE * max_blks;
  573. } else {
  574. if (sata->dma_flag != FLAGS_FPDMA)
  575. fsl_sata_rw_cmd_ext(sata, start, blks, addr,
  576. is_write);
  577. else
  578. fsl_sata_rw_ncq_cmd(sata, start, blks, addr,
  579. is_write);
  580. start += blks;
  581. blks = 0;
  582. addr += ATA_SECT_SIZE * blks;
  583. }
  584. } while (blks != 0);
  585. return blkcnt;
  586. }
  587. static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt,
  588. const void *buffer, int is_write)
  589. {
  590. u32 start, blks;
  591. u8 *addr;
  592. int max_blks;
  593. start = blknr;
  594. blks = blkcnt;
  595. addr = (u8 *)buffer;
  596. max_blks = ATA_MAX_SECTORS;
  597. do {
  598. if (blks > max_blks) {
  599. fsl_sata_rw_cmd(sata, start, max_blks, addr, is_write);
  600. start += max_blks;
  601. blks -= max_blks;
  602. addr += ATA_SECT_SIZE * max_blks;
  603. } else {
  604. fsl_sata_rw_cmd(sata, start, blks, addr, is_write);
  605. start += blks;
  606. blks = 0;
  607. addr += ATA_SECT_SIZE * blks;
  608. }
  609. } while (blks != 0);
  610. return blkcnt;
  611. }
  612. /*
  613. * SATA interface between low level driver and command layer
  614. */
  615. #if !CONFIG_IS_ENABLED(BLK)
  616. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  617. {
  618. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  619. #else
  620. static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  621. void *buffer)
  622. {
  623. struct fsl_ata_priv *priv = dev_get_platdata(dev);
  624. fsl_sata_t *sata = priv->fsl_sata;
  625. #endif
  626. u32 rc;
  627. if (sata->lba48)
  628. rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
  629. READ_CMD);
  630. else
  631. rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
  632. READ_CMD);
  633. return rc;
  634. }
  635. #if !CONFIG_IS_ENABLED(BLK)
  636. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  637. {
  638. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  639. #else
  640. static ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  641. const void *buffer)
  642. {
  643. struct fsl_ata_priv *priv = dev_get_platdata(dev);
  644. fsl_sata_t *sata = priv->fsl_sata;
  645. #endif
  646. u32 rc;
  647. if (sata->lba48) {
  648. rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
  649. WRITE_CMD);
  650. if (sata->wcache && sata->flush_ext)
  651. fsl_sata_flush_cache_ext(sata);
  652. } else {
  653. rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
  654. WRITE_CMD);
  655. if (sata->wcache && sata->flush)
  656. fsl_sata_flush_cache(sata);
  657. }
  658. return rc;
  659. }
  660. static void fsl_sata_identify(fsl_sata_t *sata, u16 *id)
  661. {
  662. struct sata_fis_h2d h2d, *cfis = &h2d;
  663. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  664. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  665. cfis->pm_port_c = 0x80; /* is command */
  666. cfis->command = ATA_CMD_ID_ATA;
  667. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
  668. ata_swap_buf_le16(id, ATA_ID_WORDS);
  669. }
  670. #if !CONFIG_IS_ENABLED(BLK)
  671. int scan_sata(int dev)
  672. {
  673. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  674. #else
  675. static int scan_sata(struct udevice *dev)
  676. {
  677. struct blk_desc *desc = dev_get_uclass_platdata(dev);
  678. struct fsl_ata_priv *priv = dev_get_platdata(dev);
  679. fsl_sata_t *sata = priv->fsl_sata;
  680. #endif
  681. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  682. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  683. unsigned char product[ATA_ID_PROD_LEN + 1];
  684. u16 *id;
  685. u64 n_sectors;
  686. /* if no detected link */
  687. if (!sata->link)
  688. return -1;
  689. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  690. if (!id) {
  691. printf("id malloc failed\n\r");
  692. return -1;
  693. }
  694. /* Identify device to get information */
  695. fsl_sata_identify(sata, id);
  696. /* Serial number */
  697. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  698. /* Firmware version */
  699. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  700. /* Product model */
  701. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  702. /* Totoal sectors */
  703. n_sectors = ata_id_n_sectors(id);
  704. #ifdef CONFIG_LBA48
  705. /* Check if support LBA48 */
  706. if (ata_id_has_lba48(id)) {
  707. sata->lba48 = 1;
  708. debug("Device support LBA48\n\r");
  709. } else
  710. debug("Device supports LBA28\n\r");
  711. #endif
  712. #if !CONFIG_IS_ENABLED(BLK)
  713. memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
  714. memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
  715. memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
  716. sata_dev_desc[dev].lba = (u32)n_sectors;
  717. #ifdef CONFIG_LBA48
  718. sata_dev_desc[dev].lba48 = sata->lba48;
  719. #endif
  720. #else
  721. memcpy(desc->product, serial, sizeof(serial));
  722. memcpy(desc->revision, firmware, sizeof(firmware));
  723. memcpy(desc->vendor, product, sizeof(product));
  724. desc->lba = n_sectors;
  725. #ifdef CONFIG_LBA48
  726. desc->lba48 = sata->lba48;
  727. #endif
  728. #endif
  729. /* Get the NCQ queue depth from device */
  730. sata->queue_depth = ata_id_queue_depth(id);
  731. /* Get the xfer mode from device */
  732. fsl_sata_xfer_mode(sata, id);
  733. /* Get the write cache status from device */
  734. fsl_sata_init_wcache(sata, id);
  735. /* Set the xfer mode to highest speed */
  736. fsl_sata_set_features(sata);
  737. #ifdef DEBUG
  738. ata_dump_id(id);
  739. #endif
  740. free((void *)id);
  741. return 0;
  742. }
  743. #if CONFIG_IS_ENABLED(BLK)
  744. static const struct blk_ops sata_fsl_blk_ops = {
  745. .read = sata_read,
  746. .write = sata_write,
  747. };
  748. U_BOOT_DRIVER(sata_fsl_driver) = {
  749. .name = "sata_fsl_blk",
  750. .id = UCLASS_BLK,
  751. .ops = &sata_fsl_blk_ops,
  752. .platdata_auto_alloc_size = sizeof(struct fsl_ata_priv),
  753. };
  754. static int fsl_ata_ofdata_to_platdata(struct udevice *dev)
  755. {
  756. struct fsl_ata_priv *priv = dev_get_priv(dev);
  757. priv->number = dev_read_u32_default(dev, "sata-number", -1);
  758. priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
  759. priv->offset = dev_read_u32_default(dev, "sata-offset", -1);
  760. priv->base = dev_read_addr(dev);
  761. if (priv->base == FDT_ADDR_T_NONE)
  762. return -EINVAL;
  763. return 0;
  764. }
  765. static int fsl_ata_probe(struct udevice *dev)
  766. {
  767. struct fsl_ata_priv *blk_priv, *priv;
  768. struct udevice *blk;
  769. char sata_name[10];
  770. int nr_ports;
  771. int ret;
  772. int i;
  773. priv = dev_get_priv(dev);
  774. nr_ports = priv->number;
  775. nr_ports = min(nr_ports, CONFIG_SYS_SATA_MAX_DEVICE);
  776. for (i = 0; i < nr_ports; i++) {
  777. snprintf(sata_name, sizeof(sata_name), "fsl_sata%d", i);
  778. ret = blk_create_devicef(dev, "sata_fsl_blk", sata_name,
  779. IF_TYPE_SATA, -1, 512, 0, &blk);
  780. if (ret) {
  781. debug("Can't create device\n");
  782. return ret;
  783. }
  784. /* Init SATA port */
  785. ret = init_sata(priv, i);
  786. if (ret) {
  787. debug("%s: Failed to init sata\n", __func__);
  788. return ret;
  789. }
  790. blk_priv = dev_get_platdata(blk);
  791. blk_priv->fsl_sata = priv->fsl_sata;
  792. /* Scan SATA port */
  793. ret = scan_sata(blk);
  794. if (ret) {
  795. debug("%s: Failed to scan bus\n", __func__);
  796. return ret;
  797. }
  798. }
  799. return 0;
  800. }
  801. static int sata_fsl_scan(struct udevice *dev)
  802. {
  803. /* Nothing to do here */
  804. return 0;
  805. }
  806. struct ahci_ops sata_fsl_ahci_ops = {
  807. .scan = sata_fsl_scan,
  808. };
  809. static const struct udevice_id fsl_ata_ids[] = {
  810. { .compatible = "fsl,pq-sata-v2" },
  811. { }
  812. };
  813. U_BOOT_DRIVER(fsl_ahci) = {
  814. .name = "fsl_ahci",
  815. .id = UCLASS_AHCI,
  816. .of_match = fsl_ata_ids,
  817. .ops = &sata_fsl_ahci_ops,
  818. .ofdata_to_platdata = fsl_ata_ofdata_to_platdata,
  819. .probe = fsl_ata_probe,
  820. .priv_auto_alloc_size = sizeof(struct fsl_ata_priv),
  821. };
  822. #endif