Makefile 3.4 KB

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  1. #
  2. # Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. #
  4. # SPDX-License-Identifier: GPL-2.0+
  5. #
  6. DDR_SRC_PATH=lpddr4/src
  7. DDR_REGU_SRC=lpddr-regu
  8. DDR_FW_PATH=$(DDR_SRC_PATH)/ddr_phy_fw
  9. ifdef CONFIG_SPL_BUILD
  10. obj-y += spl.o
  11. obj-y += sys_clk.o
  12. ifdef CONFIG_PMIC_VOL_INIT
  13. obj-$(CONFIG_PMIC_VOL_INIT) += $(DDR_REGU_SRC)/ddr_regu.o
  14. obj-$(CONFIG_PMIC_VOL_INIT) += $(DDR_REGU_SRC)/dw_iic_ll.o
  15. endif
  16. ifdef CONFIG_TARGET_LIGHT_FPGA_FM_C910
  17. obj-y += ddr.o
  18. else # // CONFIG_TARGET_LIGHT_FPGA_FM_C910
  19. obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/init_ddr.o
  20. obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/pinmux.o
  21. obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/waitfwdone.o
  22. obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
  23. obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
  24. obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/lpddr4_init.o
  25. ifdef CONFIG_DDR_DBI_OFF
  26. obj-$(CONFIG_DDR_LP4X_4266_DUALRANK) += $(DDR_FW_PATH)/lp4x_4266_phy_train1d2d_dualrank_dbioff.o
  27. obj-$(CONFIG_DDR_LP4X_3733_DUALRANK) += $(DDR_FW_PATH)/lp4x_3733_phy_train1d2d_dualrank_dbioff.o
  28. obj-$(CONFIG_DDR_LP4X_3200_DUALRANK) += $(DDR_FW_PATH)/lp4x_3200_phy_train1d2d_dualrank_dbioff.o
  29. obj-$(CONFIG_DDR_LP4_4266_DUALRANK) += $(DDR_FW_PATH)/lp4_4266_phy_train1d2d_dualrank_dbioff.o
  30. obj-$(CONFIG_DDR_LP4_3733_DUALRANK) += $(DDR_FW_PATH)/lp4_3733_phy_train1d2d_dualrank_dbioff.o
  31. obj-$(CONFIG_DDR_LP4X_4266_SINGLERANK) += $(DDR_FW_PATH)/lp4x_4266_phy_train1d2d_dbioff.o
  32. obj-$(CONFIG_DDR_LP4X_3733_SINGLERANK) += $(DDR_FW_PATH)/lp4x_3733_phy_train1d2d_dbioff.o
  33. obj-$(CONFIG_DDR_LP4X_3200_SINGLERANK) += $(DDR_FW_PATH)/lp4x_3200_phy_train1d2d_dbioff.o
  34. obj-$(CONFIG_DDR_LP4_4266_SINGLERANK) += $(DDR_FW_PATH)/lp4_4266_phy_train1d2d_dbioff.o
  35. obj-$(CONFIG_DDR_LP4_3733_SINGLERANK) += $(DDR_FW_PATH)/lp4_3733_phy_train1d2d_dbioff.o
  36. else # // CONFIG_DDR_DBI_OFF
  37. obj-$(CONFIG_DDR_LP4X_4266_DUALRANK) += $(DDR_FW_PATH)/lp4x_4266_phy_train1d2d_dualrank.o
  38. obj-$(CONFIG_DDR_LP4X_3733_DUALRANK) += $(DDR_FW_PATH)/lp4x_3733_phy_train1d2d_dualrank.o
  39. obj-$(CONFIG_DDR_LP4X_3200_DUALRANK) += $(DDR_FW_PATH)/lp4x_3200_phy_train1d2d_dualrank.o
  40. obj-$(CONFIG_DDR_LP4X_2133_DUALRANK) += $(DDR_FW_PATH)/lp4x_2133_phy_train1d2d_dualrank.o
  41. obj-$(CONFIG_DDR_LP4_4266_DUALRANK) += $(DDR_FW_PATH)/lp4_4266_phy_train1d2d_dualrank.o
  42. obj-$(CONFIG_DDR_LP4_3733_DUALRANK) += $(DDR_FW_PATH)/lp4_3733_phy_train1d2d_dualrank.o
  43. obj-$(CONFIG_DDR_LP4X_4266_SINGLERANK) += $(DDR_FW_PATH)/lp4x_4266_phy_train1d2d.o
  44. obj-$(CONFIG_DDR_LP4X_3733_SINGLERANK) += $(DDR_FW_PATH)/lp4x_3733_phy_train1d2d.o
  45. obj-$(CONFIG_DDR_LP4X_3200_SINGLERANK) += $(DDR_FW_PATH)/lp4x_3200_phy_train1d2d.o
  46. obj-$(CONFIG_DDR_LP4X_2133_SINGLERANK) += $(DDR_FW_PATH)/lp4x_2133_phy_train1d2d.o
  47. obj-$(CONFIG_DDR_LP4_4266_SINGLERANK) += $(DDR_FW_PATH)/lp4_4266_phy_train1d2d.o
  48. obj-$(CONFIG_DDR_LP4_3733_SINGLERANK) += $(DDR_FW_PATH)/lp4_3733_phy_train1d2d.o
  49. endif # // CONFIG_DDR_DBI_OFF
  50. obj-$(CONFIG_LPDDR_EYE) += $(DDR_SRC_PATH)/lp4_diag_eye.o
  51. endif # // CONFIG_TARGET_LIGHT_FPGA_FM_C910
  52. else # // CONFIG_SPL_BUILD
  53. obj-y += light.o
  54. obj-y += board.o
  55. obj-$(CONFIG_THEAD_LIGHT_TIMER) += timer.o
  56. obj-$(CONFIG_THEAD_LIGHT_DIGITAL_SENSOR) += digital_sensor.o digital_sensor_test.o
  57. obj-y += clock_config.o
  58. obj-y += sec_check.o
  59. obj-y += boot.o
  60. ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910
  61. obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/ddr_common_func.o
  62. obj-$(CONFIG_LPDDR) += $(DDR_SRC_PATH)/common_lib.o
  63. endif
  64. obj-y += light-sv/pll_io_test.o
  65. obj-y += light-sv/adc_test.o
  66. obj-y += version_rollback.o
  67. endif