cpu.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004 Texas Insturments
  4. *
  5. * (C) Copyright 2002
  6. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. * Marius Groeger <mgroeger@sysgo.de>
  8. *
  9. * (C) Copyright 2002
  10. * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  11. */
  12. /*
  13. * CPU specific code
  14. */
  15. #include <common.h>
  16. #include <command.h>
  17. #include <cpu_func.h>
  18. #include <irq_func.h>
  19. #include <asm/system.h>
  20. static void cache_flush(void);
  21. int cleanup_before_linux (void)
  22. {
  23. /*
  24. * this function is called just before we call linux
  25. * it prepares the processor for linux
  26. *
  27. * we turn off caches etc ...
  28. */
  29. disable_interrupts();
  30. /* turn off I/D-cache */
  31. icache_disable();
  32. dcache_disable();
  33. /* flush I/D-cache */
  34. cache_flush();
  35. return 0;
  36. }
  37. static void cache_flush(void)
  38. {
  39. unsigned long i = 0;
  40. /* clean entire data cache */
  41. asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
  42. /* invalidate both caches and flush btb */
  43. asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
  44. /* mem barrier to sync things */
  45. asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
  46. }
  47. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  48. void invalidate_dcache_all(void)
  49. {
  50. asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
  51. }
  52. void flush_dcache_all(void)
  53. {
  54. asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
  55. asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
  56. }
  57. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  58. {
  59. if (!check_cache_range(start, stop))
  60. return;
  61. while (start < stop) {
  62. asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
  63. start += CONFIG_SYS_CACHELINE_SIZE;
  64. }
  65. }
  66. void flush_dcache_range(unsigned long start, unsigned long stop)
  67. {
  68. if (!check_cache_range(start, stop))
  69. return;
  70. while (start < stop) {
  71. asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
  72. start += CONFIG_SYS_CACHELINE_SIZE;
  73. }
  74. asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
  75. }
  76. #else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  77. void invalidate_dcache_all(void)
  78. {
  79. }
  80. void flush_dcache_all(void)
  81. {
  82. }
  83. #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  84. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  85. void enable_caches(void)
  86. {
  87. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  88. icache_enable();
  89. #endif
  90. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  91. dcache_enable();
  92. #endif
  93. }
  94. #endif