cache.h 1.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  4. */
  5. #ifndef __ASM_ARC_CACHE_H
  6. #define __ASM_ARC_CACHE_H
  7. #include <config.h>
  8. /*
  9. * As of today we may handle any L1 cache line length right in software.
  10. * For that essentially cache line length is a variable not constant.
  11. * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
  12. * that may exist in either L1 or L2 (AKA SLC) caches on ARC.
  13. */
  14. #define ARCH_DMA_MINALIGN 128
  15. /* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
  16. #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
  17. #if defined(ARC_MMU_ABSENT)
  18. #define CONFIG_ARC_MMU_VER 0
  19. #elif defined(CONFIG_ARC_MMU_V2)
  20. #define CONFIG_ARC_MMU_VER 2
  21. #elif defined(CONFIG_ARC_MMU_V3)
  22. #define CONFIG_ARC_MMU_VER 3
  23. #elif defined(CONFIG_ARC_MMU_V4)
  24. #define CONFIG_ARC_MMU_VER 4
  25. #endif
  26. #ifndef __ASSEMBLY__
  27. void cache_init(void);
  28. void flush_n_invalidate_dcache_all(void);
  29. void sync_n_cleanup_cache_all(void);
  30. static const inline int is_ioc_enabled(void)
  31. {
  32. return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
  33. }
  34. #endif /* __ASSEMBLY__ */
  35. #endif /* __ASM_ARC_CACHE_H */