arcregs.h 3.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
  4. */
  5. #ifndef _ASM_ARC_ARCREGS_H
  6. #define _ASM_ARC_ARCREGS_H
  7. #include <asm/cache.h>
  8. #include <config.h>
  9. /*
  10. * ARC architecture has additional address space - auxiliary registers.
  11. * These registers are mostly used for configuration purposes.
  12. * These registers are not memory mapped and special commands are used for
  13. * access: "lr"/"sr".
  14. */
  15. /*
  16. * Typically 8 least significant bits of Build Configuration Register (BCR)
  17. * describe version of the HW block in question. Moreover if decoded version
  18. * is 0 this means given HW block is absent - this is especially useful because
  19. * we may safely read BRC regardless HW block existence while an attempt to
  20. * access any other AUX regs associated with this HW block lead to imediate
  21. * "instruction error" exception.
  22. *
  23. * I.e. before using any cofigurable HW block it's required to make sure it
  24. * exists at all, and for that we introduce a special macro below.
  25. */
  26. #define ARC_BCR_VERSION_MASK GENMASK(7, 0)
  27. #define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK)
  28. #define ARC_AUX_IDENTITY 0x04
  29. #define ARC_AUX_STATUS32 0x0a
  30. /* STATUS32 Bits Positions */
  31. #define STATUS_AD_BIT 19 /* Enable unaligned access */
  32. /* Instruction cache related auxiliary registers */
  33. #define ARC_AUX_IC_IVIC 0x10
  34. #define ARC_AUX_IC_CTRL 0x11
  35. #define ARC_AUX_IC_IVIL 0x19
  36. #if (CONFIG_ARC_MMU_VER == 3)
  37. #define ARC_AUX_IC_PTAG 0x1E
  38. #endif
  39. #define ARC_BCR_IC_BUILD 0x77
  40. #define AUX_AUX_CACHE_LIMIT 0x5D
  41. #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
  42. /* ICCM and DCCM auxiliary registers */
  43. #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
  44. #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
  45. /* Timer related auxiliary registers */
  46. #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
  47. #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
  48. #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
  49. #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
  50. #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
  51. #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */
  52. #define ARC_AUX_INTR_VEC_BASE 0x25
  53. /* Data cache related auxiliary registers */
  54. #define ARC_AUX_DC_IVDC 0x47
  55. #define ARC_AUX_DC_CTRL 0x48
  56. #define ARC_AUX_DC_IVDL 0x4A
  57. #define ARC_AUX_DC_FLSH 0x4B
  58. #define ARC_AUX_DC_FLDL 0x4C
  59. #if (CONFIG_ARC_MMU_VER == 3)
  60. #define ARC_AUX_DC_PTAG 0x5C
  61. #endif
  62. #define ARC_BCR_DC_BUILD 0x72
  63. #define ARC_BCR_SLC 0xce
  64. #define ARC_AUX_SLC_CONFIG 0x901
  65. #define ARC_AUX_SLC_CTRL 0x903
  66. #define ARC_AUX_SLC_FLUSH 0x904
  67. #define ARC_AUX_SLC_INVALIDATE 0x905
  68. #define ARC_AUX_SLC_IVDL 0x910
  69. #define ARC_AUX_SLC_FLDL 0x912
  70. #define ARC_AUX_SLC_RGN_START 0x914
  71. #define ARC_AUX_SLC_RGN_START1 0x915
  72. #define ARC_AUX_SLC_RGN_END 0x916
  73. #define ARC_AUX_SLC_RGN_END1 0x917
  74. #define ARC_BCR_CLUSTER 0xcf
  75. /* MMU Management regs */
  76. #define ARC_AUX_MMU_BCR 0x6f
  77. /* IO coherency related auxiliary registers */
  78. #define ARC_AUX_IO_COH_ENABLE 0x500
  79. #define ARC_AUX_IO_COH_PARTIAL 0x501
  80. #define ARC_AUX_IO_COH_AP0_BASE 0x508
  81. #define ARC_AUX_IO_COH_AP0_SIZE 0x509
  82. /* XY-memory related */
  83. #define ARC_AUX_XY_BUILD 0x79
  84. /* DSP-extensions related auxiliary registers */
  85. #define ARC_AUX_DSP_BUILD 0x7A
  86. /* ARC Subsystems related auxiliary registers */
  87. #define ARC_AUX_SUBSYS_BUILD 0xF0
  88. #ifndef __ASSEMBLY__
  89. /* Accessors for auxiliary registers */
  90. #define read_aux_reg(reg) __builtin_arc_lr(reg)
  91. /* gcc builtin sr needs reg param to be long immediate */
  92. #define write_aux_reg(reg_immed, val) \
  93. __builtin_arc_sr((unsigned int)val, reg_immed)
  94. /* ARCNUM [15:8] - field to identify each core in a multi-core system */
  95. #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
  96. static const inline int is_isa_arcv2(void)
  97. {
  98. return IS_ENABLED(CONFIG_ISA_ARCV2);
  99. }
  100. static const inline int is_isa_arcompact(void)
  101. {
  102. return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
  103. }
  104. #endif /* __ASSEMBLY__ */
  105. #endif /* _ASM_ARC_ARCREGS_H */