iot_devkit.dts 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
  4. */
  5. /dts-v1/;
  6. #include "skeleton.dtsi"
  7. / {
  8. #address-cells = <1>;
  9. #size-cells = <1>;
  10. aliases {
  11. console = &uart0;
  12. };
  13. cpu_card {
  14. core_clk: core_clk {
  15. #clock-cells = <0>;
  16. compatible = "fixed-clock";
  17. clock-frequency = <144000000>;
  18. u-boot,dm-pre-reloc;
  19. };
  20. };
  21. uart0: serial0@80014000 {
  22. compatible = "snps,dw-apb-uart";
  23. clock-frequency = <16000000>;
  24. reg = <0x80014000 0x1000>;
  25. reg-shift = <2>;
  26. reg-io-width = <4>;
  27. };
  28. usb: usb@f0040000 {
  29. compatible = "snps,dwc2";
  30. reg = <0xf0040000 0x10000>;
  31. phys = <&usbphy>;
  32. phy-names = "usb2-phy";
  33. };
  34. usbphy: phy {
  35. compatible = "nop-phy";
  36. #phy-cells = <0>;
  37. };
  38. mmcclk_biu: mmcclk-biu {
  39. compatible = "fixed-clock";
  40. clock-frequency = <50000000>;
  41. #clock-cells = <0>;
  42. };
  43. mmcclk_ciu: mmcclk-ciu {
  44. compatible = "fixed-clock";
  45. clock-frequency = <50000000>;
  46. #clock-cells = <0>;
  47. };
  48. mmc: mmc0@f000b000 {
  49. compatible = "snps,dw-mshc";
  50. reg = <0xf000b000 0x400>;
  51. bus-width = <4>;
  52. fifo-depth = <128>;
  53. clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
  54. clock-names = "biu", "ciu";
  55. max-frequency = <25000000>;
  56. };
  57. };