hsdk.dts 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
  4. */
  5. /dts-v1/;
  6. #include "skeleton.dtsi"
  7. #include "dt-bindings/clock/snps,hsdk-cgu.h"
  8. / {
  9. model = "snps,hsdk";
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. aliases {
  13. console = &uart0;
  14. spi0 = &spi0;
  15. };
  16. cpu_card {
  17. core_clk: core_clk {
  18. #clock-cells = <0>;
  19. compatible = "fixed-clock";
  20. clock-frequency = <500000000>;
  21. u-boot,dm-pre-reloc;
  22. };
  23. };
  24. clk-fmeas {
  25. clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
  26. <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
  27. <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
  28. <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
  29. <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
  30. <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
  31. <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
  32. <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
  33. <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
  34. <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
  35. <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
  36. <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
  37. <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
  38. clock-names = "cpu-pll", "sys-pll",
  39. "tun-pll", "ddr-clk",
  40. "cpu-clk", "hdmi-pll",
  41. "tun-clk", "hdmi-clk",
  42. "apb-clk", "axi-clk",
  43. "eth-clk", "usb-clk",
  44. "sdio-clk", "hdmi-sys-clk",
  45. "gfx-core-clk", "gfx-dma-clk",
  46. "gfx-cfg-clk", "dmac-core-clk",
  47. "dmac-cfg-clk", "sdio-ref-clk",
  48. "spi-clk", "i2c-clk",
  49. "uart-clk", "ebi-clk",
  50. "rom-clk", "pwm-clk";
  51. };
  52. cgu_clk: cgu-clk@f0000000 {
  53. compatible = "snps,hsdk-cgu-clock";
  54. reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
  55. #clock-cells = <1>;
  56. };
  57. uart0: serial0@f0005000 {
  58. compatible = "snps,dw-apb-uart";
  59. reg = <0xf0005000 0x1000>;
  60. reg-shift = <2>;
  61. reg-io-width = <4>;
  62. };
  63. ethernet@f0008000 {
  64. #interrupt-cells = <1>;
  65. compatible = "snps,arc-dwmac-3.70a";
  66. reg = <0xf0008000 0x2000>;
  67. phy-mode = "gmii";
  68. };
  69. ehci@0xf0040000 {
  70. compatible = "generic-ehci";
  71. reg = <0xf0040000 0x100>;
  72. };
  73. ohci@0xf0060000 {
  74. compatible = "generic-ohci";
  75. reg = <0xf0060000 0x100>;
  76. };
  77. mmcclk_ciu: mmcclk-ciu {
  78. compatible = "fixed-clock";
  79. /*
  80. * DW sdio controller has external ciu clock divider
  81. * controlled via register in SDIO IP. Due to its
  82. * unexpected default value (it should divide by 1
  83. * but it divides by 8) SDIO IP uses wrong clock and
  84. * works unstable (see STAR 9001204800)
  85. * We switched to the minimum possible value of the
  86. * divisor (div-by-2) in HSDK platform code.
  87. * So default mmcclk ciu clock is 50000000 Hz.
  88. */
  89. clock-frequency = <50000000>;
  90. #clock-cells = <0>;
  91. };
  92. mmc: mmc0@f000a000 {
  93. compatible = "snps,dw-mshc";
  94. reg = <0xf000a000 0x400>;
  95. bus-width = <4>;
  96. fifo-depth = <256>;
  97. clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
  98. clock-names = "biu", "ciu";
  99. max-frequency = <25000000>;
  100. };
  101. spi0: spi@f0020000 {
  102. compatible = "snps,dw-apb-ssi";
  103. reg = <0xf0020000 0x1000>;
  104. #address-cells = <1>;
  105. #size-cells = <0>;
  106. spi-max-frequency = <4000000>;
  107. clocks = <&cgu_clk CLK_SYS_SPI_REF>;
  108. clock-names = "spi_clk";
  109. cs-gpio = <&cs_gpio 0>;
  110. spi_flash@0 {
  111. compatible = "jedec,spi-nor";
  112. reg = <0>;
  113. spi-max-frequency = <4000000>;
  114. };
  115. };
  116. cs_gpio: gpio@f00014b0 {
  117. compatible = "snps,creg-gpio";
  118. reg = <0xf00014b0 0x4>;
  119. gpio-controller;
  120. #gpio-cells = <1>;
  121. gpio-bank-name = "hsdk-spi-cs";
  122. gpio-count = <1>;
  123. gpio-first-shift = <0>;
  124. gpio-bit-per-line = <2>;
  125. gpio-activate-val = <2>;
  126. gpio-deactivate-val = <3>;
  127. gpio-default-val = <1>;
  128. };
  129. };