emsdp.dts 1.0 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
  4. */
  5. /dts-v1/;
  6. #include "skeleton.dtsi"
  7. / {
  8. model = "snps,emsdp";
  9. #address-cells = <1>;
  10. #size-cells = <1>;
  11. aliases {
  12. console = &uart0;
  13. };
  14. cpu_card {
  15. core_clk: core_clk {
  16. #clock-cells = <0>;
  17. compatible = "fixed-clock";
  18. clock-frequency = <40000000>;
  19. u-boot,dm-pre-reloc;
  20. };
  21. };
  22. uart0: serial0@f0004000 {
  23. compatible = "snps,dw-apb-uart";
  24. clock-frequency = <100000000>;
  25. reg = <0xf0004000 0x1000>;
  26. reg-shift = <2>;
  27. reg-io-width = <4>;
  28. };
  29. mmcclk_biu: mmcclk-biu {
  30. compatible = "fixed-clock";
  31. clock-frequency = <50000000>;
  32. #clock-cells = <0>;
  33. };
  34. mmcclk_ciu: mmcclk-ciu {
  35. compatible = "fixed-clock";
  36. clock-frequency = <100000000>;
  37. #clock-cells = <0>;
  38. };
  39. mmc: mmc0@f0010000 {
  40. compatible = "snps,dw-mshc";
  41. reg = <0xf0010000 0x400>;
  42. bus-width = <4>;
  43. fifo-depth = <256>;
  44. clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
  45. clock-names = "biu", "ciu";
  46. max-frequency = <25000000>;
  47. };
  48. };