axs10x_mb.dtsi 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
  4. */
  5. / {
  6. aliases {
  7. spi0 = &spi0;
  8. };
  9. axs10x_mb@e0000000 {
  10. compatible = "simple-bus";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. ranges = <0x00000000 0xe0000000 0x10000000>;
  14. u-boot,dm-pre-reloc;
  15. clocks {
  16. compatible = "simple-bus";
  17. u-boot,dm-pre-reloc;
  18. apbclk: apbclk {
  19. compatible = "fixed-clock";
  20. clock-frequency = <50000000>;
  21. #clock-cells = <0>;
  22. };
  23. uartclk: uartclk {
  24. compatible = "fixed-clock";
  25. clock-frequency = <33333333>;
  26. #clock-cells = <0>;
  27. u-boot,dm-pre-reloc;
  28. };
  29. mmcclk_ciu: mmcclk-ciu {
  30. compatible = "fixed-clock";
  31. /*
  32. * DW sdio controller has external ciu clock divider
  33. * controlled via register in SDIO IP. It divides
  34. * sdio_ref_clk (which comes from CGU) by 16 for
  35. * default. So default mmcclk clock (which comes
  36. * to sdk_in) is 25000000 Hz.
  37. */
  38. clock-frequency = <25000000>;
  39. #clock-cells = <0>;
  40. };
  41. mmcclk_biu: mmcclk-biu {
  42. compatible = "fixed-clock";
  43. clock-frequency = <50000000>;
  44. #clock-cells = <0>;
  45. };
  46. };
  47. ethernet@18000 {
  48. compatible = "snps,arc-dwmac-3.70a";
  49. reg = < 0x18000 0x2000 >;
  50. phy-mode = "gmii";
  51. snps,pbl = < 32 >;
  52. clocks = <&apbclk>;
  53. clock-names = "stmmaceth";
  54. max-speed = <100>;
  55. };
  56. ehci@0x40000 {
  57. compatible = "generic-ehci";
  58. reg = < 0x40000 0x100 >;
  59. };
  60. ohci@0x60000 {
  61. compatible = "generic-ohci";
  62. reg = < 0x60000 0x100 >;
  63. };
  64. mmc: mmc@15000 {
  65. compatible = "snps,dw-mshc";
  66. reg = <0x15000 0x400>;
  67. bus-width = <4>;
  68. clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
  69. clock-names = "biu", "ciu";
  70. max-frequency = <25000000>;
  71. };
  72. uart0: serial0@22000 {
  73. compatible = "snps,dw-apb-uart";
  74. reg = <0x22000 0x100>;
  75. clocks = <&uartclk>;
  76. reg-shift = <2>;
  77. reg-io-width = <4>;
  78. };
  79. spi0: spi@0 {
  80. compatible = "snps,dw-apb-ssi";
  81. reg = <0x0 0x100>;
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. spi-max-frequency = <4000000>;
  85. clocks = <&apbclk>;
  86. clock-names = "spi_clk";
  87. cs-gpio = <&cs_gpio 0>;
  88. spi_flash@0 {
  89. compatible = "jedec,spi-nor";
  90. reg = <0>;
  91. spi-max-frequency = <4000000>;
  92. };
  93. };
  94. cs_gpio: gpio@11218 {
  95. compatible = "snps,creg-gpio";
  96. reg = <0x11218 0x4>;
  97. gpio-controller;
  98. #gpio-cells = <1>;
  99. gpio-bank-name = "axs-spi-cs";
  100. gpio-count = <1>;
  101. gpio-first-shift = <0>;
  102. gpio-bit-per-line = <2>;
  103. gpio-activate-val = <1>;
  104. gpio-deactivate-val = <3>;
  105. gpio-default-val = <1>;
  106. };
  107. };
  108. };