xpedite517x.h 21 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009 Extreme Engineering Solutions, Inc.
  4. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  5. */
  6. /*
  7. * xpedite517x board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_SYS_BOARD_NAME "XPedite5170"
  15. #define CONFIG_SYS_FORM_3U_VPX 1
  16. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  17. #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
  18. #define CONFIG_ALTIVEC 1
  19. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  20. #define CONFIG_PCIE1 1 /* PCIE controller 1 */
  21. #define CONFIG_PCIE2 1 /* PCIE controller 2 */
  22. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  23. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  24. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  25. /*
  26. * DDR config
  27. */
  28. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  29. #define CONFIG_DDR_SPD
  30. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  31. #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
  32. #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
  33. #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
  34. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  35. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  36. #define CONFIG_DDR_ECC
  37. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  38. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  39. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  40. #define CONFIG_VERY_BIG_RAM
  41. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  42. /*
  43. * virtual address to be used for temporary mappings. There
  44. * should be 128k free at this VA.
  45. */
  46. #define CONFIG_SYS_SCRATCH_VA 0xe0000000
  47. #ifndef __ASSEMBLY__
  48. extern unsigned long get_board_sys_clk(unsigned long dummy);
  49. #endif
  50. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
  51. /*
  52. * L2CR setup
  53. */
  54. #define CONFIG_SYS_L2
  55. #define L2_INIT 0
  56. #define L2_ENABLE (L2CR_L2E)
  57. /*
  58. * Base addresses -- Note these are effective addresses where the
  59. * actual resources get mapped (not physical addresses)
  60. */
  61. #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
  62. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
  63. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  64. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
  65. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  66. /*
  67. * Diagnostics
  68. */
  69. #define CONFIG_SYS_MEMTEST_START 0x10000000
  70. #define CONFIG_SYS_MEMTEST_END 0x20000000
  71. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
  72. CONFIG_SYS_POST_I2C)
  73. /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
  74. #define I2C_ADDR_IGNORE_LIST {0x50}
  75. /*
  76. * Memory map
  77. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  78. * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
  79. * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
  80. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  81. * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
  82. * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
  83. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  84. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  85. * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
  86. * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
  87. */
  88. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
  89. /*
  90. * NAND flash configuration
  91. */
  92. #define CONFIG_SYS_NAND_BASE 0xef800000
  93. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  94. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
  95. #define CONFIG_SYS_MAX_NAND_DEVICE 2
  96. #define CONFIG_NAND_ACTL
  97. #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
  98. #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
  99. #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
  100. #define CONFIG_SYS_NAND_ACTL_DELAY 25
  101. #define CONFIG_JFFS2_NAND
  102. /*
  103. * NOR flash configuration
  104. */
  105. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  106. #define CONFIG_SYS_FLASH_BASE2 0xf0000000
  107. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  108. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  109. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  110. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  111. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  112. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
  113. {0xf7f00000, 0xc0000} }
  114. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  115. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  116. /*
  117. * Chip select configuration
  118. */
  119. /* NOR Flash 0 on CS0 */
  120. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
  121. BR_PS_16 |\
  122. BR_V)
  123. #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
  124. OR_GPCM_CSNT |\
  125. OR_GPCM_XACS |\
  126. OR_GPCM_ACS_DIV2 |\
  127. OR_GPCM_SCY_8 |\
  128. OR_GPCM_TRLX |\
  129. OR_GPCM_EHTR |\
  130. OR_GPCM_EAD)
  131. /* NOR Flash 1 on CS1 */
  132. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
  133. BR_PS_16 |\
  134. BR_V)
  135. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  136. /* NAND flash on CS2 */
  137. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
  138. BR_PS_8 |\
  139. BR_V)
  140. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
  141. OR_GPCM_BCTLD |\
  142. OR_GPCM_CSNT |\
  143. OR_GPCM_ACS_DIV4 |\
  144. OR_GPCM_SCY_4 |\
  145. OR_GPCM_TRLX |\
  146. OR_GPCM_EHTR)
  147. /* Optional NAND flash on CS3 */
  148. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
  149. BR_PS_8 |\
  150. BR_V)
  151. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  152. /*
  153. * Use L1 as initial stack
  154. */
  155. #define CONFIG_SYS_INIT_RAM_LOCK 1
  156. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  157. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  158. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  159. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  160. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  161. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  162. /*
  163. * Serial Port
  164. */
  165. #define CONFIG_SYS_NS16550_SERIAL
  166. #define CONFIG_SYS_NS16550_REG_SIZE 1
  167. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  168. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  169. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  170. #define CONFIG_SYS_BAUDRATE_TABLE \
  171. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  172. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  173. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  174. /*
  175. * I2C
  176. */
  177. #define CONFIG_SYS_I2C
  178. #define CONFIG_SYS_I2C_FSL
  179. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  180. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  181. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  182. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  183. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  184. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  185. /* PEX8518 slave I2C interface */
  186. #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
  187. /* I2C DS1631 temperature sensor */
  188. #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
  189. /* I2C EEPROM - AT24C128B */
  190. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
  191. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  192. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  193. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  194. /* I2C RTC */
  195. #define CONFIG_RTC_M41T11 1
  196. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  197. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  198. /* GPIO */
  199. #define CONFIG_PCA953X
  200. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  201. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
  202. #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
  203. #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
  204. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  205. #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
  206. /*
  207. * PU = pulled high, PD = pulled low
  208. * I = input, O = output, IO = input/output
  209. */
  210. /* PCA9557 @ 0x18*/
  211. #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
  212. #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
  213. #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
  214. #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
  215. #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
  216. #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
  217. /* PCA9557 @ 0x1c*/
  218. #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
  219. #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
  220. #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
  221. #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
  222. #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
  223. #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
  224. #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
  225. #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
  226. /* PCA9557 @ 0x1e*/
  227. #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
  228. #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
  229. #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
  230. #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
  231. #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
  232. #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
  233. #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
  234. /* PCA9557 @ 0x1f */
  235. #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
  236. #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
  237. #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
  238. #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
  239. /*
  240. * General PCI
  241. * Memory space is mapped 1-1, but I/O space must start from 0.
  242. */
  243. /* PCIE1 - PEX8518 */
  244. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  245. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  246. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
  247. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  248. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
  249. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  250. /* PCIE2 - VPX P1 */
  251. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  252. #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
  253. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  254. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  255. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
  256. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
  257. /*
  258. * Networking options
  259. */
  260. #define CONFIG_ETHPRIME "eTSEC1"
  261. #define CONFIG_TSEC1 1
  262. #define CONFIG_TSEC1_NAME "eTSEC1"
  263. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  264. #define TSEC1_PHY_ADDR 1
  265. #define TSEC1_PHYIDX 0
  266. #define CONFIG_HAS_ETH0
  267. #define CONFIG_TSEC2 1
  268. #define CONFIG_TSEC2_NAME "eTSEC2"
  269. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  270. #define TSEC2_PHY_ADDR 2
  271. #define TSEC2_PHYIDX 0
  272. #define CONFIG_HAS_ETH1
  273. /*
  274. * BAT mappings
  275. */
  276. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  277. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
  278. BATL_PP_RW |\
  279. BATL_CACHEINHIBIT |\
  280. BATL_GUARDEDSTORAGE)
  281. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
  282. BATU_BL_1M |\
  283. BATU_VS |\
  284. BATU_VP)
  285. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
  286. BATL_PP_RW |\
  287. BATL_CACHEINHIBIT)
  288. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  289. #endif
  290. /*
  291. * BAT0 2G Cacheable, non-guarded
  292. * 0x0000_0000 2G DDR
  293. */
  294. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  295. #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
  296. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  297. #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
  298. /*
  299. * BAT1 1G Cache-inhibited, guarded
  300. * 0x8000_0000 1G PCI-Express 1 Memory
  301. */
  302. #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
  303. BATL_PP_RW |\
  304. BATL_CACHEINHIBIT |\
  305. BATL_GUARDEDSTORAGE)
  306. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
  307. BATU_BL_1G |\
  308. BATU_VS |\
  309. BATU_VP)
  310. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
  311. BATL_PP_RW |\
  312. BATL_CACHEINHIBIT)
  313. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  314. /*
  315. * BAT2 512M Cache-inhibited, guarded
  316. * 0xc000_0000 512M PCI-Express 2 Memory
  317. */
  318. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
  319. BATL_PP_RW |\
  320. BATL_CACHEINHIBIT |\
  321. BATL_GUARDEDSTORAGE)
  322. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
  323. BATU_BL_512M |\
  324. BATU_VS |\
  325. BATU_VP)
  326. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
  327. BATL_PP_RW |\
  328. BATL_CACHEINHIBIT)
  329. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  330. /*
  331. * BAT3 1M Cache-inhibited, guarded
  332. * 0xe000_0000 1M CCSR
  333. */
  334. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
  335. BATL_PP_RW |\
  336. BATL_CACHEINHIBIT |\
  337. BATL_GUARDEDSTORAGE)
  338. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
  339. BATU_BL_1M |\
  340. BATU_VS |\
  341. BATU_VP)
  342. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
  343. BATL_PP_RW |\
  344. BATL_CACHEINHIBIT)
  345. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  346. /*
  347. * BAT4 32M Cache-inhibited, guarded
  348. * 0xe200_0000 16M PCI-Express 1 I/O
  349. * 0xe300_0000 16M PCI-Express 2 I/0
  350. */
  351. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
  352. BATL_PP_RW |\
  353. BATL_CACHEINHIBIT |\
  354. BATL_GUARDEDSTORAGE)
  355. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
  356. BATU_BL_32M |\
  357. BATU_VS |\
  358. BATU_VP)
  359. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
  360. BATL_PP_RW |\
  361. BATL_CACHEINHIBIT)
  362. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  363. /*
  364. * BAT5 128K Cacheable, non-guarded
  365. * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
  366. */
  367. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
  368. BATL_PP_RW |\
  369. BATL_MEMCOHERENCE)
  370. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
  371. BATU_BL_128K |\
  372. BATU_VS |\
  373. BATU_VP)
  374. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  375. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  376. /*
  377. * BAT6 256M Cache-inhibited, guarded
  378. * 0xf000_0000 256M FLASH
  379. */
  380. #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
  381. BATL_PP_RW |\
  382. BATL_CACHEINHIBIT |\
  383. BATL_GUARDEDSTORAGE)
  384. #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
  385. BATU_BL_256M |\
  386. BATU_VS |\
  387. BATU_VP)
  388. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
  389. BATL_PP_RW |\
  390. BATL_MEMCOHERENCE)
  391. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  392. /* Map the last 1M of flash where we're running from reset */
  393. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
  394. BATL_PP_RW |\
  395. BATL_CACHEINHIBIT |\
  396. BATL_GUARDEDSTORAGE)
  397. #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
  398. BATU_BL_1M |\
  399. BATU_VS |\
  400. BATU_VP)
  401. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
  402. BATL_PP_RW |\
  403. BATL_MEMCOHERENCE)
  404. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  405. /*
  406. * BAT7 64M Cache-inhibited, guarded
  407. * 0xe800_0000 64K NAND FLASH
  408. * 0xe804_0000 128K DUART Registers
  409. */
  410. #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
  411. BATL_PP_RW |\
  412. BATL_CACHEINHIBIT |\
  413. BATL_GUARDEDSTORAGE)
  414. #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
  415. BATU_BL_512K |\
  416. BATU_VS |\
  417. BATU_VP)
  418. #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
  419. BATL_PP_RW |\
  420. BATL_CACHEINHIBIT)
  421. #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
  422. /*
  423. * Miscellaneous configurable options
  424. */
  425. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  426. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  427. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  428. /*
  429. * For booting Linux, the board info and command line data
  430. * have to be in the first 16 MB of memory, since this is
  431. * the maximum mapped by the Linux kernel during initialization.
  432. */
  433. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  434. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  435. /*
  436. * Environment Configuration
  437. */
  438. /*
  439. * Flash memory map:
  440. * fffc0000 - ffffffff Pri FDT (256KB)
  441. * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
  442. * fff00000 - fff7ffff Pri U-Boot (512 KB)
  443. * fef00000 - ffefffff Pri OS image (16MB)
  444. * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
  445. *
  446. * f7fc0000 - f7ffffff Sec FDT (256KB)
  447. * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
  448. * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
  449. * f6f00000 - f7efffff Sec OS image (16MB)
  450. * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
  451. */
  452. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
  453. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
  454. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
  455. #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
  456. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  457. #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
  458. #define CONFIG_PROG_UBOOT1 \
  459. "$download_cmd $loadaddr $ubootfile; " \
  460. "if test $? -eq 0; then " \
  461. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  462. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  463. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  464. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  465. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  466. "if test $? -ne 0; then " \
  467. "echo PROGRAM FAILED; " \
  468. "else; " \
  469. "echo PROGRAM SUCCEEDED; " \
  470. "fi; " \
  471. "else; " \
  472. "echo DOWNLOAD FAILED; " \
  473. "fi;"
  474. #define CONFIG_PROG_UBOOT2 \
  475. "$download_cmd $loadaddr $ubootfile; " \
  476. "if test $? -eq 0; then " \
  477. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  478. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  479. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  480. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  481. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  482. "if test $? -ne 0; then " \
  483. "echo PROGRAM FAILED; " \
  484. "else; " \
  485. "echo PROGRAM SUCCEEDED; " \
  486. "fi; " \
  487. "else; " \
  488. "echo DOWNLOAD FAILED; " \
  489. "fi;"
  490. #define CONFIG_BOOT_OS_NET \
  491. "$download_cmd $osaddr $osfile; " \
  492. "if test $? -eq 0; then " \
  493. "if test -n $fdtaddr; then " \
  494. "$download_cmd $fdtaddr $fdtfile; " \
  495. "if test $? -eq 0; then " \
  496. "bootm $osaddr - $fdtaddr; " \
  497. "else; " \
  498. "echo FDT DOWNLOAD FAILED; " \
  499. "fi; " \
  500. "else; " \
  501. "bootm $osaddr; " \
  502. "fi; " \
  503. "else; " \
  504. "echo OS DOWNLOAD FAILED; " \
  505. "fi;"
  506. #define CONFIG_PROG_OS1 \
  507. "$download_cmd $osaddr $osfile; " \
  508. "if test $? -eq 0; then " \
  509. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  510. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  511. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  512. "if test $? -ne 0; then " \
  513. "echo OS PROGRAM FAILED; " \
  514. "else; " \
  515. "echo OS PROGRAM SUCCEEDED; " \
  516. "fi; " \
  517. "else; " \
  518. "echo OS DOWNLOAD FAILED; " \
  519. "fi;"
  520. #define CONFIG_PROG_OS2 \
  521. "$download_cmd $osaddr $osfile; " \
  522. "if test $? -eq 0; then " \
  523. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  524. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  525. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  526. "if test $? -ne 0; then " \
  527. "echo OS PROGRAM FAILED; " \
  528. "else; " \
  529. "echo OS PROGRAM SUCCEEDED; " \
  530. "fi; " \
  531. "else; " \
  532. "echo OS DOWNLOAD FAILED; " \
  533. "fi;"
  534. #define CONFIG_PROG_FDT1 \
  535. "$download_cmd $fdtaddr $fdtfile; " \
  536. "if test $? -eq 0; then " \
  537. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  538. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  539. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  540. "if test $? -ne 0; then " \
  541. "echo FDT PROGRAM FAILED; " \
  542. "else; " \
  543. "echo FDT PROGRAM SUCCEEDED; " \
  544. "fi; " \
  545. "else; " \
  546. "echo FDT DOWNLOAD FAILED; " \
  547. "fi;"
  548. #define CONFIG_PROG_FDT2 \
  549. "$download_cmd $fdtaddr $fdtfile; " \
  550. "if test $? -eq 0; then " \
  551. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  552. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  553. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  554. "if test $? -ne 0; then " \
  555. "echo FDT PROGRAM FAILED; " \
  556. "else; " \
  557. "echo FDT PROGRAM SUCCEEDED; " \
  558. "fi; " \
  559. "else; " \
  560. "echo FDT DOWNLOAD FAILED; " \
  561. "fi;"
  562. #define CONFIG_EXTRA_ENV_SETTINGS \
  563. "autoload=yes\0" \
  564. "download_cmd=tftp\0" \
  565. "console_args=console=ttyS0,115200\0" \
  566. "root_args=root=/dev/nfs rw\0" \
  567. "misc_args=ip=on\0" \
  568. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  569. "bootfile=/home/user/file\0" \
  570. "osfile=/home/user/board.uImage\0" \
  571. "fdtfile=/home/user/board.dtb\0" \
  572. "ubootfile=/home/user/u-boot.bin\0" \
  573. "fdtaddr=0x1e00000\0" \
  574. "osaddr=0x1000000\0" \
  575. "loadaddr=0x1000000\0" \
  576. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  577. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  578. "prog_os1="CONFIG_PROG_OS1"\0" \
  579. "prog_os2="CONFIG_PROG_OS2"\0" \
  580. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  581. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  582. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  583. "bootcmd_flash1=run set_bootargs; " \
  584. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  585. "bootcmd_flash2=run set_bootargs; " \
  586. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  587. "bootcmd=run bootcmd_flash1\0"
  588. #endif /* __CONFIG_H */