p2771-0000.h 1.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2013-2016, NVIDIA CORPORATION.
  4. */
  5. #ifndef _P2771_0000_H
  6. #define _P2771_0000_H
  7. #include <linux/sizes.h>
  8. #include "tegra186-common.h"
  9. /* High-level configuration options */
  10. #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
  11. /* Environment in eMMC, at the end of 2nd "boot sector" */
  12. #define CONFIG_SYS_MMC_ENV_DEV 0
  13. #define CONFIG_SYS_MMC_ENV_PART 2
  14. #define BOARD_EXTRA_ENV_SETTINGS \
  15. "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
  16. "ramdisk_addr_r\0" \
  17. "kernel_addr_r_align=00200000\0" \
  18. "kernel_addr_r_offset=00080000\0" \
  19. "kernel_addr_r_size=02000000\0" \
  20. "kernel_addr_r_aliases=loadaddr\0" \
  21. "fdt_addr_r_align=00200000\0" \
  22. "fdt_addr_r_offset=00000000\0" \
  23. "fdt_addr_r_size=00200000\0" \
  24. "scriptaddr_align=00200000\0" \
  25. "scriptaddr_offset=00000000\0" \
  26. "scriptaddr_size=00200000\0" \
  27. "pxefile_addr_r_align=00200000\0" \
  28. "pxefile_addr_r_offset=00000000\0" \
  29. "pxefile_addr_r_size=00200000\0" \
  30. "ramdisk_addr_r_align=00200000\0" \
  31. "ramdisk_addr_r_offset=00000000\0" \
  32. "ramdisk_addr_r_size=02000000\0"
  33. #include "tegra-common-post.h"
  34. /* Crystal is 38.4MHz. clk_m runs at half that rate */
  35. #define COUNTER_FREQUENCY 19200000
  36. #endif