kmp204x.h 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #if defined(CONFIG_KMCOGE4)
  9. #define CONFIG_HOSTNAME "kmcoge4"
  10. #define CONFIG_KM_BOARD_NAME "kmcoge4"
  11. #else
  12. #error ("Board not supported")
  13. #endif
  14. #define CONFIG_KMP204X
  15. #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
  16. /* an additionnal option is required for UBI as subpage access is
  17. * supported in u-boot
  18. */
  19. #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
  20. #define CONFIG_NAND_ECC_BCH
  21. /* common KM defines */
  22. #include "km/keymile-common.h"
  23. #define CONFIG_SYS_RAMBOOT
  24. #define CONFIG_RAMBOOT_PBL
  25. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  26. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  27. #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
  28. #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
  29. /* High Level Configuration Options */
  30. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  31. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  32. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  33. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  34. #define CONFIG_PCIE1 /* PCIE controller 1 */
  35. #define CONFIG_PCIE3 /* PCIE controller 3 */
  36. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  37. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  38. #define CONFIG_SYS_DPAA_RMAN /* RMan */
  39. /* Environment in SPI Flash */
  40. #define CONFIG_ENV_TOTAL_SIZE 0x020000
  41. #ifndef __ASSEMBLY__
  42. unsigned long get_board_sys_clk(unsigned long dummy);
  43. #endif
  44. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
  45. /*
  46. * These can be toggled for performance analysis, otherwise use default.
  47. */
  48. #define CONFIG_SYS_CACHE_STASHING
  49. #define CONFIG_BACKSIDE_L2_CACHE
  50. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  51. #define CONFIG_BTB /* toggle branch predition */
  52. #define CONFIG_ENABLE_36BIT_PHYS
  53. #define CONFIG_ADDR_MAP
  54. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  55. #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
  56. /*
  57. * Config the L3 Cache as L3 SRAM
  58. */
  59. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  60. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
  61. CONFIG_RAMBOOT_TEXT_BASE)
  62. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  63. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  64. #define CONFIG_SYS_DCSRBAR 0xf0000000
  65. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  66. /*
  67. * DDR Setup
  68. */
  69. #define CONFIG_VERY_BIG_RAM
  70. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  71. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  72. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  73. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  74. #define CONFIG_DDR_SPD
  75. #define CONFIG_SYS_SPD_BUS_NUM 0
  76. #define SPD_EEPROM_ADDRESS 0x54
  77. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  78. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  79. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  80. /******************************************************************************
  81. * (PRAM usage)
  82. * ... -------------------------------------------------------
  83. * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
  84. * ... |<------------------- pram -------------------------->|
  85. * ... -------------------------------------------------------
  86. * @END_OF_RAM:
  87. * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
  88. * @CONFIG_KM_PHRAM: address for /var
  89. * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
  90. * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
  91. */
  92. /* size of rootfs in RAM */
  93. #define CONFIG_KM_ROOTFSSIZE 0x0
  94. /* pseudo-non volatile RAM [hex] */
  95. #define CONFIG_KM_PNVRAM 0x80000
  96. /* physical RAM MTD size [hex] */
  97. #define CONFIG_KM_PHRAM 0x100000
  98. /* reserved pram area at the end of memory [hex]
  99. * u-boot reserves some memory for the MP boot page
  100. */
  101. #define CONFIG_KM_RESERVED_PRAM 0x1000
  102. /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
  103. * is not valid yet, which is the case for when u-boot copies itself to RAM
  104. */
  105. #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
  106. #define CONFIG_KM_CRAMFS_ADDR 0x2000000
  107. #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
  108. #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
  109. /*
  110. * Local Bus Definitions
  111. */
  112. /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
  113. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
  114. /* Nand Flash */
  115. #define CONFIG_NAND_FSL_ELBC
  116. #define CONFIG_SYS_NAND_BASE 0xffa00000
  117. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  118. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
  119. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  120. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  121. /* NAND flash config */
  122. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  123. | BR_PS_8 /* Port Size = 8 bit */ \
  124. | BR_MS_FCM /* MSEL = FCM */ \
  125. | BR_V) /* valid */
  126. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
  127. | OR_FCM_BCTLD /* LBCTL not ass */ \
  128. | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
  129. | OR_FCM_RST /* 1 clk read setup */ \
  130. | OR_FCM_PGS /* Large page size */ \
  131. | OR_FCM_CST) /* 0.25 command setup */
  132. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
  133. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  134. /* QRIO FPGA */
  135. #define CONFIG_SYS_QRIO_BASE 0xfb000000
  136. #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
  137. #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
  138. | BR_PS_8 /* Port Size 8 bits */ \
  139. | BR_DECC_OFF /* no error corr */ \
  140. | BR_MS_GPCM /* MSEL = GPCM */ \
  141. | BR_V) /* valid */
  142. #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
  143. | OR_GPCM_BCTLD /* no LCTL assert */ \
  144. | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
  145. | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
  146. | OR_GPCM_TRLX /* relaxed tmgs */ \
  147. | OR_GPCM_EAD) /* extra bus clk cycles */
  148. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
  149. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
  150. #define CONFIG_MISC_INIT_F
  151. #define CONFIG_HWCONFIG
  152. /* define to use L1 as initial stack */
  153. #define CONFIG_L1_INIT_RAM
  154. #define CONFIG_SYS_INIT_RAM_LOCK
  155. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  156. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  157. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  158. /* The assembler doesn't like typecast */
  159. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  160. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  161. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  162. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  163. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  164. GENERATED_GBL_DATA_SIZE)
  165. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  166. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  167. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  168. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  169. /* Serial Port - controlled on board with jumper J8
  170. * open - index 2
  171. * shorted - index 1
  172. */
  173. #define CONFIG_SYS_NS16550_SERIAL
  174. #define CONFIG_SYS_NS16550_REG_SIZE 1
  175. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
  176. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
  177. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600)
  178. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500)
  179. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600)
  180. #define CONFIG_KM_CONSOLE_TTY "ttyS0"
  181. /* I2C */
  182. #define CONFIG_SYS_I2C
  183. #define CONFIG_SYS_I2C_INIT_BOARD
  184. #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
  185. #define CONFIG_SYS_NUM_I2C_BUSES 3
  186. #define CONFIG_SYS_I2C_MAX_HOPS 1
  187. #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
  188. #define CONFIG_I2C_MULTI_BUS
  189. #define CONFIG_I2C_CMD_TREE
  190. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  191. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  192. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  193. #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
  194. {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
  195. {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
  196. }
  197. #ifndef __ASSEMBLY__
  198. void set_sda(int state);
  199. void set_scl(int state);
  200. int get_sda(void);
  201. int get_scl(void);
  202. #endif
  203. #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
  204. /*
  205. * eSPI - Enhanced SPI
  206. */
  207. /*
  208. * General PCI
  209. * Memory space is mapped 1-1, but I/O space must start from 0.
  210. */
  211. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  212. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  213. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  214. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  215. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  216. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  217. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  218. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  219. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  220. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  221. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  222. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  223. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  224. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  225. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
  226. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  227. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
  228. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  229. /* Qman/Bman */
  230. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  231. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  232. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  233. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  234. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  235. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  236. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  237. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  238. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  239. CONFIG_SYS_BMAN_CENA_SIZE)
  240. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  241. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  242. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  243. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  244. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  245. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  246. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  247. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  248. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  249. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  250. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  251. CONFIG_SYS_QMAN_CENA_SIZE)
  252. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  253. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  254. #define CONFIG_SYS_DPAA_FMAN
  255. #define CONFIG_SYS_DPAA_PME
  256. /* Default address of microcode for the Linux Fman driver
  257. * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
  258. * ucode is stored after env, so we got 0x120000.
  259. */
  260. #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
  261. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  262. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  263. #define CONFIG_PHYLIB_10G
  264. #define CONFIG_PCI_INDIRECT_BRIDGE
  265. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  266. /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
  267. #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
  268. #define CONFIG_SYS_TBIPA_VALUE 8
  269. #define CONFIG_ETHPRIME "FM1@DTSEC5"
  270. /*
  271. * Environment
  272. */
  273. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  274. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  275. /*
  276. * Hardware Watchdog
  277. */
  278. #define CONFIG_WATCHDOG /* enable CPU watchdog */
  279. #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
  280. #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
  281. /*
  282. * additionnal command line configuration.
  283. */
  284. /* we don't need flash support */
  285. #undef CONFIG_JFFS2_CMDLINE
  286. /*
  287. * For booting Linux, the board info and command line data
  288. * have to be in the first 64 MB of memory, since this is
  289. * the maximum mapped by the Linux kernel during initialization.
  290. */
  291. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
  292. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  293. #ifdef CONFIG_CMD_KGDB
  294. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  295. #endif
  296. #define __USB_PHY_TYPE utmi
  297. #define CONFIG_USB_EHCI_FSL
  298. /*
  299. * Environment Configuration
  300. */
  301. #define CONFIG_ENV_OVERWRITE
  302. #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
  303. #define CONFIG_KM_DEF_ENV "km-common=empty\0"
  304. #endif
  305. /* architecture specific default bootargs */
  306. #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
  307. /* FIXME: FDT_ADDR is unspecified */
  308. #define CONFIG_KM_DEF_ENV_CPU \
  309. "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
  310. "cramfsloadfdt=" \
  311. "cramfsload ${fdt_addr_r} " \
  312. "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
  313. "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
  314. "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0" \
  315. "update=" \
  316. "sf probe 0;sf erase 0 +${filesize};" \
  317. "sf write ${load_addr_r} 0 ${filesize};\0" \
  318. "set_fdthigh=true\0" \
  319. "checkfdt=true\0" \
  320. ""
  321. #define CONFIG_HW_ENV_SETTINGS \
  322. "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
  323. "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
  324. "usb_dr_mode=host\0"
  325. #define CONFIG_KM_NEW_ENV \
  326. "newenv=sf probe 0;" \
  327. "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
  328. __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
  329. /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
  330. #ifndef CONFIG_KM_DEF_ARCH
  331. #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
  332. #endif
  333. #define CONFIG_EXTRA_ENV_SETTINGS \
  334. CONFIG_KM_DEF_ENV \
  335. CONFIG_KM_DEF_ARCH \
  336. CONFIG_KM_NEW_ENV \
  337. CONFIG_HW_ENV_SETTINGS \
  338. "EEprom_ivm=pca9547:70:9\0" \
  339. ""
  340. /* App2 Local bus */
  341. #define CONFIG_SYS_LBAPP2_BASE 0xE0000000
  342. #define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull
  343. #define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
  344. | BR_PS_8 /* Port Size 8 bits */ \
  345. | BR_DECC_OFF /* no error corr */ \
  346. | BR_MS_GPCM /* MSEL = GPCM */ \
  347. | BR_V) /* valid */
  348. #define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
  349. | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
  350. | OR_GPCM_CSNT /* LCS 1/4 clk before */ \
  351. | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
  352. | OR_GPCM_TRLX /* relaxed tmgs */ \
  353. | OR_GPCM_EAD) /* extra bus clk cycles */
  354. /* Local bus app2 Base Address */
  355. #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
  356. /* Local bus app2 Options */
  357. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
  358. #endif /* __CONFIG_H */