grpeach.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuration settings for the Renesas GRPEACH board
  4. *
  5. * Copyright (C) 2017-2019 Renesas Electronics
  6. */
  7. #ifndef __GRPEACH_H
  8. #define __GRPEACH_H
  9. /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
  10. #define CONFIG_SYS_CLK_FREQ 66666666
  11. /* Serial Console */
  12. #define CONFIG_BAUDRATE 115200
  13. /* Miscellaneous */
  14. #define CONFIG_SYS_PBSIZE 256
  15. #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
  16. #define CONFIG_CMDLINE_TAG
  17. /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
  18. #define CONFIG_SYS_SDRAM_BASE 0x20000000
  19. #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
  20. #define CONFIG_SYS_INIT_SP_ADDR \
  21. (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
  22. #define CONFIG_SYS_LOAD_ADDR \
  23. (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
  24. #define CONFIG_ENV_OVERWRITE 1
  25. /* Malloc */
  26. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  27. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  28. /* Kernel Boot */
  29. #define CONFIG_BOOTARGS "ignore_loglevel"
  30. /* Network interface */
  31. #define CONFIG_SH_ETHER_USE_PORT 0
  32. #define CONFIG_SH_ETHER_PHY_ADDR 0
  33. #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
  34. #define CONFIG_SH_ETHER_CACHE_WRITEBACK
  35. #define CONFIG_SH_ETHER_CACHE_INVALIDATE
  36. #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
  37. #define CONFIG_BITBANGMII
  38. #define CONFIG_BITBANGMII_MULTI
  39. #endif /* __GRPEACH_H */