cyrus.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Based on corenet_ds.h
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
  8. #error Must call Cyrus CONFIG with a specific CPU enabled.
  9. #endif
  10. #define CONFIG_SDCARD
  11. #define CONFIG_FSL_SATA_V2
  12. #define CONFIG_PCIE3
  13. #define CONFIG_PCIE4
  14. #ifdef CONFIG_ARCH_P5020
  15. #define CONFIG_SYS_FSL_RAID_ENGINE
  16. #define CONFIG_SYS_DPAA_RMAN
  17. #endif
  18. #define CONFIG_SYS_DPAA_PME
  19. /*
  20. * Corenet DS style board configuration file
  21. */
  22. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  23. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  24. #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
  25. #if defined(CONFIG_ARCH_P5020)
  26. #define CONFIG_SYS_CLK_FREQ 133000000
  27. #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
  28. #elif defined(CONFIG_ARCH_P5040)
  29. #define CONFIG_SYS_CLK_FREQ 100000000
  30. #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
  31. #endif
  32. /* High Level Configuration Options */
  33. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  34. #define CONFIG_SYS_MMC_MAX_DEVICE 1
  35. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  36. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  37. #define CONFIG_PCIE1 /* PCIE controller 1 */
  38. #define CONFIG_PCIE2 /* PCIE controller 2 */
  39. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  40. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  41. #define CONFIG_ENV_OVERWRITE
  42. #if defined(CONFIG_SDCARD)
  43. #define CONFIG_FSL_FIXED_MMC_LOCATION
  44. #define CONFIG_SYS_MMC_ENV_DEV 0
  45. #endif
  46. /*
  47. * These can be toggled for performance analysis, otherwise use default.
  48. */
  49. #define CONFIG_SYS_CACHE_STASHING
  50. #define CONFIG_BACKSIDE_L2_CACHE
  51. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  52. #define CONFIG_BTB /* toggle branch predition */
  53. #define CONFIG_DDR_ECC
  54. #ifdef CONFIG_DDR_ECC
  55. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  56. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  57. #endif
  58. #define CONFIG_ENABLE_36BIT_PHYS
  59. #ifdef CONFIG_PHYS_64BIT
  60. #define CONFIG_ADDR_MAP
  61. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  62. #endif
  63. /* test POST memory test */
  64. #undef CONFIG_POST
  65. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  66. #define CONFIG_SYS_MEMTEST_END 0x00400000
  67. /*
  68. * Config the L3 Cache as L3 SRAM
  69. */
  70. #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  71. #ifdef CONFIG_PHYS_64BIT
  72. #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  73. #else
  74. #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  75. #endif
  76. #define CONFIG_SYS_L3_SIZE (1024 << 10)
  77. #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  78. #ifdef CONFIG_PHYS_64BIT
  79. #define CONFIG_SYS_DCSRBAR 0xf0000000
  80. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  81. #endif
  82. /*
  83. * DDR Setup
  84. */
  85. #define CONFIG_VERY_BIG_RAM
  86. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  87. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  88. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  89. #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  90. #define CONFIG_DDR_SPD
  91. #define CONFIG_SYS_SPD_BUS_NUM 1
  92. #define SPD_EEPROM_ADDRESS1 0x51
  93. #define SPD_EEPROM_ADDRESS2 0x52
  94. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  95. /*
  96. * Local Bus Definitions
  97. */
  98. #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
  99. #ifdef CONFIG_PHYS_64BIT
  100. #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
  101. #else
  102. #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
  103. #endif
  104. #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
  105. #ifdef CONFIG_PHYS_64BIT
  106. #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
  107. #else
  108. #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
  109. #endif
  110. /* Set the local bus clock 1/16 of platform clock */
  111. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
  112. #define CONFIG_SYS_BR0_PRELIM \
  113. (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
  114. #define CONFIG_SYS_BR1_PRELIM \
  115. (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
  116. #define CONFIG_SYS_OR0_PRELIM 0xfff00010
  117. #define CONFIG_SYS_OR1_PRELIM 0xfff00010
  118. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  119. #if defined(CONFIG_RAMBOOT_PBL)
  120. #define CONFIG_SYS_RAMBOOT
  121. #endif
  122. #define CONFIG_HWCONFIG
  123. /* define to use L1 as initial stack */
  124. #define CONFIG_L1_INIT_RAM
  125. #define CONFIG_SYS_INIT_RAM_LOCK
  126. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  127. #ifdef CONFIG_PHYS_64BIT
  128. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  129. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  130. /* The assembler doesn't like typecast */
  131. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  132. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  133. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  134. #else
  135. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
  136. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  137. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  138. #endif
  139. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  140. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  141. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  142. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  143. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  144. /* Serial Port - controlled on board with jumper J8
  145. * open - index 2
  146. * shorted - index 1
  147. */
  148. #define CONFIG_SYS_NS16550_SERIAL
  149. #define CONFIG_SYS_NS16550_REG_SIZE 1
  150. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  151. #define CONFIG_SYS_BAUDRATE_TABLE \
  152. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  153. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  154. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  155. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  156. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  157. /* I2C */
  158. #define CONFIG_SYS_I2C
  159. #define CONFIG_SYS_I2C_FSL
  160. #define CONFIG_I2C_MULTI_BUS
  161. #define CONFIG_I2C_CMD_TREE
  162. #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
  163. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  164. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  165. #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
  166. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  167. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  168. #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
  169. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  170. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  171. #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
  172. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  173. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  174. #define CONFIG_ID_EEPROM
  175. #define CONFIG_SYS_I2C_EEPROM_NXID
  176. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  177. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  178. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  179. #define CONFIG_SYS_I2C_GENERIC_MAC
  180. #define CONFIG_SYS_I2C_MAC1_BUS 3
  181. #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
  182. #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
  183. #define CONFIG_SYS_I2C_MAC2_BUS 0
  184. #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
  185. #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
  186. #define CONFIG_RTC_MCP79411 1
  187. #define CONFIG_SYS_RTC_BUS_NUM 3
  188. #define CONFIG_SYS_I2C_RTC_ADDR 0x6f
  189. /*
  190. * eSPI - Enhanced SPI
  191. */
  192. /*
  193. * General PCI
  194. * Memory space is mapped 1-1, but I/O space must start from 0.
  195. */
  196. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  197. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  198. #ifdef CONFIG_PHYS_64BIT
  199. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  200. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  201. #else
  202. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  203. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  204. #endif
  205. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  206. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  207. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  208. #ifdef CONFIG_PHYS_64BIT
  209. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  210. #else
  211. #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
  212. #endif
  213. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  214. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  215. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  216. #ifdef CONFIG_PHYS_64BIT
  217. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  218. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  219. #else
  220. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  221. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  222. #endif
  223. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  224. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  225. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  226. #ifdef CONFIG_PHYS_64BIT
  227. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  228. #else
  229. #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
  230. #endif
  231. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  232. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  233. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  234. #ifdef CONFIG_PHYS_64BIT
  235. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  236. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  237. #else
  238. #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
  239. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
  240. #endif
  241. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  242. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  243. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  244. #ifdef CONFIG_PHYS_64BIT
  245. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  246. #else
  247. #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
  248. #endif
  249. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  250. /* controller 4, Base address 203000 */
  251. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  252. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  253. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  254. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  255. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  256. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  257. /* Qman/Bman */
  258. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  259. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  260. #ifdef CONFIG_PHYS_64BIT
  261. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  262. #else
  263. #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  264. #endif
  265. #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  266. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  267. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  268. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  269. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  270. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  271. CONFIG_SYS_BMAN_CENA_SIZE)
  272. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  273. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  274. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  275. #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  276. #ifdef CONFIG_PHYS_64BIT
  277. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  278. #else
  279. #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  280. #endif
  281. #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  282. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  283. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  284. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  285. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  286. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  287. CONFIG_SYS_QMAN_CENA_SIZE)
  288. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  289. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  290. #define CONFIG_SYS_DPAA_FMAN
  291. /* Default address of microcode for the Linux Fman driver */
  292. /*
  293. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  294. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  295. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  296. */
  297. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  298. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  299. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  300. #ifdef CONFIG_PCI
  301. #define CONFIG_PCI_INDIRECT_BRIDGE
  302. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  303. #endif /* CONFIG_PCI */
  304. /* SATA */
  305. #ifdef CONFIG_FSL_SATA_V2
  306. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  307. #define CONFIG_SATA1
  308. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  309. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  310. #define CONFIG_SATA2
  311. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  312. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  313. #define CONFIG_LBA48
  314. #endif
  315. #ifdef CONFIG_FMAN_ENET
  316. #define CONFIG_SYS_TBIPA_VALUE 8
  317. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  318. #endif
  319. /*
  320. * Environment
  321. */
  322. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  323. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  324. /*
  325. * USB
  326. */
  327. #define CONFIG_HAS_FSL_DR_USB
  328. #define CONFIG_HAS_FSL_MPH_USB
  329. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  330. #define CONFIG_USB_EHCI_FSL
  331. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  332. #define CONFIG_EHCI_IS_TDI
  333. /* _VIA_CONTROL_EP */
  334. #endif
  335. #ifdef CONFIG_MMC
  336. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  337. #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  338. #endif
  339. /*
  340. * Miscellaneous configurable options
  341. */
  342. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  343. /*
  344. * For booting Linux, the board info and command line data
  345. * have to be in the first 64 MB of memory, since this is
  346. * the maximum mapped by the Linux kernel during initialization.
  347. */
  348. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  349. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  350. #ifdef CONFIG_CMD_KGDB
  351. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  352. #endif
  353. /*
  354. * Environment Configuration
  355. */
  356. #define CONFIG_ROOTPATH "/opt/nfsroot"
  357. #define CONFIG_BOOTFILE "uImage"
  358. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  359. /* default location for tftp and bootm */
  360. #define CONFIG_LOADADDR 1000000
  361. #define __USB_PHY_TYPE utmi
  362. #define CONFIG_EXTRA_ENV_SETTINGS \
  363. "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  364. "bank_intlv=cs0_cs1;" \
  365. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  366. "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  367. "netdev=eth0\0" \
  368. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  369. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  370. "consoledev=ttyS0\0" \
  371. "ramdiskaddr=2000000\0" \
  372. "fdtaddr=1e00000\0" \
  373. "bdev=sda3\0"
  374. #define CONFIG_HDBOOT \
  375. "setenv bootargs root=/dev/$bdev rw " \
  376. "console=$consoledev,$baudrate $othbootargs;" \
  377. "tftp $loadaddr $bootfile;" \
  378. "tftp $fdtaddr $fdtfile;" \
  379. "bootm $loadaddr - $fdtaddr"
  380. #define CONFIG_NFSBOOTCOMMAND \
  381. "setenv bootargs root=/dev/nfs rw " \
  382. "nfsroot=$serverip:$rootpath " \
  383. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  384. "console=$consoledev,$baudrate $othbootargs;" \
  385. "tftp $loadaddr $bootfile;" \
  386. "tftp $fdtaddr $fdtfile;" \
  387. "bootm $loadaddr - $fdtaddr"
  388. #define CONFIG_RAMBOOTCOMMAND \
  389. "setenv bootargs root=/dev/ram rw " \
  390. "console=$consoledev,$baudrate $othbootargs;" \
  391. "tftp $ramdiskaddr $ramdiskfile;" \
  392. "tftp $loadaddr $bootfile;" \
  393. "tftp $fdtaddr $fdtfile;" \
  394. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  395. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  396. #include <asm/fsl_secure_boot.h>
  397. #endif /* __CONFIG_H */