MPC832XEMDS.h 8.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. /*
  8. * High Level Configuration Options
  9. */
  10. #define CONFIG_E300 1 /* E300 family */
  11. /*
  12. * System IO Config
  13. */
  14. #define CONFIG_SYS_SICRL 0x00000000
  15. /*
  16. * DDR Setup
  17. */
  18. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
  19. #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
  20. #undef CONFIG_SPD_EEPROM
  21. #if defined(CONFIG_SPD_EEPROM)
  22. /* Determine DDR configuration from I2C interface
  23. */
  24. #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
  25. #else
  26. /* Manually set up DDR parameters
  27. */
  28. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  29. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  30. | CSCONFIG_AP \
  31. | CSCONFIG_ODT_WR_CFG \
  32. | CSCONFIG_ROW_BIT_13 \
  33. | CSCONFIG_COL_BIT_10)
  34. /* 0x80840102 */
  35. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  36. | (0 << TIMING_CFG0_WRT_SHIFT) \
  37. | (0 << TIMING_CFG0_RRT_SHIFT) \
  38. | (0 << TIMING_CFG0_WWT_SHIFT) \
  39. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  40. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  41. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  42. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  43. /* 0x00220802 */
  44. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  45. | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  46. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  47. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  48. | (13 << TIMING_CFG1_REFREC_SHIFT) \
  49. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  50. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  51. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  52. /* 0x3935D322 */
  53. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  54. | (31 << TIMING_CFG2_CPO_SHIFT) \
  55. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  56. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  57. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  58. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  59. | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
  60. /* 0x0F9048CA */
  61. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  62. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  63. /* 0x02000000 */
  64. #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  65. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  66. /* 0x44400232 */
  67. #define CONFIG_SYS_DDR_MODE2 0x8000c000
  68. #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  69. | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  70. /* 0x03200064 */
  71. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  72. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  73. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  74. | SDRAM_CFG_32_BE)
  75. /* 0x43080000 */
  76. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  77. #endif
  78. /*
  79. * Memory test
  80. */
  81. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  82. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  83. #define CONFIG_SYS_MEMTEST_END 0x00100000
  84. /*
  85. * The reserved memory
  86. */
  87. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  88. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  89. #define CONFIG_SYS_RAMBOOT
  90. #else
  91. #undef CONFIG_SYS_RAMBOOT
  92. #endif
  93. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  94. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  95. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  96. /*
  97. * Initial RAM Base Address Setup
  98. */
  99. #define CONFIG_SYS_INIT_RAM_LOCK 1
  100. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
  101. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  102. #define CONFIG_SYS_GBL_DATA_OFFSET \
  103. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  104. /*
  105. * FLASH on the Local Bus
  106. */
  107. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  108. #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
  109. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  110. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  111. #undef CONFIG_SYS_FLASH_CHECKSUM
  112. /*
  113. * BCSR on the Local Bus
  114. */
  115. #define CONFIG_SYS_BCSR 0xF8000000
  116. /* Access window base at BCSR base */
  117. /*
  118. * Windows to access PIB via local bus
  119. */
  120. /* PIB window base 0xF8008000 */
  121. #define CONFIG_SYS_PIB_BASE 0xF8008000
  122. #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
  123. /*
  124. * CS2 on Local Bus, to PIB
  125. */
  126. /*
  127. * CS3 on Local Bus, to PIB
  128. */
  129. /*
  130. * Serial Port
  131. */
  132. #define CONFIG_SYS_NS16550_SERIAL
  133. #define CONFIG_SYS_NS16550_REG_SIZE 1
  134. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  135. #define CONFIG_SYS_BAUDRATE_TABLE \
  136. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  137. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  138. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  139. /* I2C */
  140. #define CONFIG_SYS_I2C
  141. #define CONFIG_SYS_I2C_FSL
  142. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  143. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  144. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  145. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  146. /*
  147. * Config on-board RTC
  148. */
  149. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  150. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  151. /*
  152. * General PCI
  153. * Addresses are mapped 1-1.
  154. */
  155. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  156. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  157. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  158. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  159. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  160. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  161. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  162. #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
  163. #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
  164. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
  165. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
  166. #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
  167. #ifdef CONFIG_PCI
  168. #define CONFIG_PCI_INDIRECT_BRIDGE
  169. #define CONFIG_83XX_PCI_STREAMING
  170. #undef CONFIG_EEPRO100
  171. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  172. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  173. #endif /* CONFIG_PCI */
  174. /*
  175. * QE UEC ethernet configuration
  176. */
  177. #define CONFIG_UEC_ETH
  178. #define CONFIG_ETHPRIME "UEC0"
  179. #define CONFIG_UEC_ETH1 /* ETH3 */
  180. #ifdef CONFIG_UEC_ETH1
  181. #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
  182. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
  183. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
  184. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  185. #define CONFIG_SYS_UEC1_PHY_ADDR 3
  186. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
  187. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  188. #endif
  189. #define CONFIG_UEC_ETH2 /* ETH4 */
  190. #ifdef CONFIG_UEC_ETH2
  191. #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
  192. #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
  193. #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
  194. #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
  195. #define CONFIG_SYS_UEC2_PHY_ADDR 4
  196. #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
  197. #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
  198. #endif
  199. /*
  200. * Environment
  201. */
  202. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  203. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  204. /*
  205. * BOOTP options
  206. */
  207. #define CONFIG_BOOTP_BOOTFILESIZE
  208. /*
  209. * Command line configuration.
  210. */
  211. #undef CONFIG_WATCHDOG /* watchdog disabled */
  212. /*
  213. * Miscellaneous configurable options
  214. */
  215. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  216. /*
  217. * For booting Linux, the board info and command line data
  218. * have to be in the first 256 MB of memory, since this is
  219. * the maximum mapped by the Linux kernel during initialization.
  220. */
  221. /* Initial Memory map for Linux */
  222. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  223. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  224. #if defined(CONFIG_CMD_KGDB)
  225. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  226. #endif
  227. /*
  228. * Environment Configuration
  229. */ #define CONFIG_ENV_OVERWRITE
  230. #if defined(CONFIG_UEC_ETH)
  231. #define CONFIG_HAS_ETH0
  232. #define CONFIG_HAS_ETH1
  233. #endif
  234. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  235. #define CONFIG_EXTRA_ENV_SETTINGS \
  236. "netdev=eth0\0" \
  237. "consoledev=ttyS0\0" \
  238. "ramdiskaddr=1000000\0" \
  239. "ramdiskfile=ramfs.83xx\0" \
  240. "fdtaddr=780000\0" \
  241. "fdtfile=mpc832x_mds.dtb\0" \
  242. ""
  243. #define CONFIG_NFSBOOTCOMMAND \
  244. "setenv bootargs root=/dev/nfs rw " \
  245. "nfsroot=$serverip:$rootpath " \
  246. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  247. "$netdev:off " \
  248. "console=$consoledev,$baudrate $othbootargs;" \
  249. "tftp $loadaddr $bootfile;" \
  250. "tftp $fdtaddr $fdtfile;" \
  251. "bootm $loadaddr - $fdtaddr"
  252. #define CONFIG_RAMBOOTCOMMAND \
  253. "setenv bootargs root=/dev/ram rw " \
  254. "console=$consoledev,$baudrate $othbootargs;" \
  255. "tftp $ramdiskaddr $ramdiskfile;" \
  256. "tftp $loadaddr $bootfile;" \
  257. "tftp $fdtaddr $fdtfile;" \
  258. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  259. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  260. #endif /* __CONFIG_H */