M5275EVB.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Motorola MC5275EVB board.
  4. *
  5. * By Arthur Shipkowski <art@videon-central.com>
  6. * Copyright (C) 2005 Videon Central, Inc.
  7. *
  8. * Based off of M5272C3 board code by Josef Baumgartner
  9. * <josef.baumgartner@telex.de>
  10. */
  11. /*
  12. * board/config.h - configuration options, board specific
  13. */
  14. #ifndef _M5275EVB_H
  15. #define _M5275EVB_H
  16. /*
  17. * High Level Configuration Options
  18. * (easy to change)
  19. */
  20. #define CONFIG_MCFTMR
  21. #define CONFIG_MCFUART
  22. #define CONFIG_SYS_UART_PORT (0)
  23. /* Configuration for environment
  24. * Environment is embedded in u-boot in the second sector of the flash
  25. */
  26. #define LDS_BOARD_TEXT \
  27. . = DEFINED(env_offset) ? env_offset : .; \
  28. env/embedded.o(.text);
  29. /*
  30. * BOOTP options
  31. */
  32. #define CONFIG_BOOTP_BOOTFILESIZE
  33. /* Available command configuration */
  34. #define CONFIG_MCFFEC
  35. #ifdef CONFIG_MCFFEC
  36. #define CONFIG_MII_INIT 1
  37. #define CONFIG_SYS_DISCOVER_PHY
  38. #define CONFIG_SYS_RX_ETH_BUFFER 8
  39. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  40. #define CONFIG_SYS_FEC0_PINMUX 0
  41. #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  42. #define CONFIG_SYS_FEC1_PINMUX 0
  43. #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
  44. #define MCFFEC_TOUT_LOOP 50000
  45. #define CONFIG_HAS_ETH1
  46. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  47. #ifndef CONFIG_SYS_DISCOVER_PHY
  48. #define FECDUPLEX FULL
  49. #define FECSPEED _100BASET
  50. #else
  51. #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  52. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  53. #endif
  54. #endif
  55. #endif
  56. /* I2C */
  57. #define CONFIG_SYS_I2C
  58. #define CONFIG_SYS_I2C_FSL
  59. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  60. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  61. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
  62. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  63. #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
  64. #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
  65. #define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
  66. #define CONFIG_SYS_LOAD_ADDR 0x800000
  67. #define CONFIG_BOOTCOMMAND "bootm ffe40000"
  68. #define CONFIG_SYS_MEMTEST_START 0x400
  69. #define CONFIG_SYS_MEMTEST_END 0x380000
  70. #ifdef CONFIG_MCFFEC
  71. # define CONFIG_NET_RETRY_COUNT 5
  72. # define CONFIG_OVERWRITE_ETHADDR_ONCE
  73. #endif /* FEC_ENET */
  74. #define CONFIG_EXTRA_ENV_SETTINGS \
  75. "netdev=eth0\0" \
  76. "loadaddr=10000\0" \
  77. "uboot=u-boot.bin\0" \
  78. "load=tftp ${loadaddr} ${uboot}\0" \
  79. "upd=run load; run prog\0" \
  80. "prog=prot off ffe00000 ffe3ffff;" \
  81. "era ffe00000 ffe3ffff;" \
  82. "cp.b ${loadaddr} ffe00000 ${filesize};"\
  83. "save\0" \
  84. ""
  85. #define CONFIG_SYS_CLK 150000000
  86. /*
  87. * Low Level Configuration Settings
  88. * (address mappings, register initial values, etc.)
  89. * You should know what you are doing if you make changes here.
  90. */
  91. #define CONFIG_SYS_MBAR 0x40000000
  92. /*-----------------------------------------------------------------------
  93. * Definitions for initial stack pointer and data area (in DPRAM)
  94. */
  95. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  96. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
  97. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  98. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  99. /*-----------------------------------------------------------------------
  100. * Start addresses for the final memory configuration
  101. * (Set up by the startup code)
  102. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  103. */
  104. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  105. #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
  106. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  107. #ifdef CONFIG_MONITOR_IS_IN_RAM
  108. #define CONFIG_SYS_MONITOR_BASE 0x20000
  109. #else
  110. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  111. #endif
  112. #define CONFIG_SYS_MONITOR_LEN 0x20000
  113. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  114. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  115. /*
  116. * For booting Linux, the board info and command line data
  117. * have to be in the first 8 MB of memory, since this is
  118. * the maximum mapped by the Linux kernel during initialization ??
  119. */
  120. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  121. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  122. /*-----------------------------------------------------------------------
  123. * FLASH organization
  124. */
  125. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  126. #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
  127. #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
  128. #define CONFIG_SYS_FLASH_SIZE 0x200000
  129. /*-----------------------------------------------------------------------
  130. * Cache Configuration
  131. */
  132. #define CONFIG_SYS_CACHELINE_SIZE 16
  133. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  134. CONFIG_SYS_INIT_RAM_SIZE - 8)
  135. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  136. CONFIG_SYS_INIT_RAM_SIZE - 4)
  137. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
  138. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  139. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  140. CF_ACR_EN | CF_ACR_SM_ALL)
  141. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
  142. CF_CACR_DISD | CF_CACR_INVI | \
  143. CF_CACR_CEIB | CF_CACR_DCM | \
  144. CF_CACR_EUSP)
  145. /*-----------------------------------------------------------------------
  146. * Memory bank definitions
  147. */
  148. #define CONFIG_SYS_CS0_BASE 0xffe00000
  149. #define CONFIG_SYS_CS0_CTRL 0x00001980
  150. #define CONFIG_SYS_CS0_MASK 0x001F0001
  151. #define CONFIG_SYS_CS1_BASE 0x30000000
  152. #define CONFIG_SYS_CS1_CTRL 0x00001900
  153. #define CONFIG_SYS_CS1_MASK 0x00070001
  154. /*-----------------------------------------------------------------------
  155. * Port configuration
  156. */
  157. #define CONFIG_SYS_FECI2C 0x0FA0
  158. #endif /* _M5275EVB_H */