sys_clk.c 11 KB

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  1. /*
  2. * Copyright (C) 2017-2021 Alibaba Group Holding Limited
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #define LIGHT_APCLK_ADDRBASE 0xffff011000
  9. #define LIGHT_AONCLK_ADDRBASE 0xfffff46000
  10. #define LIGHT_DDRCLK_ADDRBASE 0xffff005000
  11. #define LIGHT_MISC_SUBSYS_ADDRBASE 0xfffc02d000
  12. #define LIGHT_VI_SUBSYS_ADDRBASE 0xfff4041000
  13. #define LIGHT_VO_SUBSYS_ADDRBASE 0xffff401000
  14. #define LIGHT_VO_SUBSYS_R_ADDRBASE 0xffef528000
  15. #define LIGHT_VP_SUBSYS_ADDRBASE 0xfffcc01000
  16. #define LIGHT_DSP_SUBSYS_ADDRBASE 0xffff041000
  17. #define LIGHT_AUDIO_SUBSYS_ADDRBASE 0xffcb000000
  18. #define LIGHT_APSYS_RSTGEN_ADDRBASE 0xffff015000
  19. #define LIGHT_DPU_CLOCK_GATING_CTRL0 0xffef601A28
  20. #define LIGHT_DPU_CLOCK_GATING_CTRL1 0xffef601A2C
  21. void show_sys_clk(void)
  22. {
  23. /* Do nothing for FPGA */
  24. }
  25. void cpu_clk_config(uint32_t cpu_freq)
  26. {
  27. #ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910 /* for sillicon */
  28. unsigned int tmp;
  29. /* 4. update c910_cclk to 750Mhz */
  30. /* set cpu_pll1_foutpostdiv to 750Mhz */
  31. writel(0x20000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
  32. writel(0x01407d01, (void *)LIGHT_APCLK_ADDRBASE + 0x10);
  33. writel(0x23000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
  34. udelay(3);
  35. writel(0x03000000, (void *)LIGHT_APCLK_ADDRBASE + 0x14);
  36. readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
  37. readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
  38. while(!(readl((void *)LIGHT_APCLK_ADDRBASE + 0x80) & 0x10));
  39. udelay(11);
  40. /* config bus: cpu clk ratio to 1:1 */
  41. writel((readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x7<<8))) | (0x0<<8), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // ratio=0
  42. writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) & (~(0x1<<11)), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=0
  43. writel(readl(LIGHT_APCLK_ADDRBASE + 0x100) | (0x1<<11), (void *)(LIGHT_APCLK_ADDRBASE + 0x100)); // sync=1
  44. /* switch c910_cclk to cpu_pll1_foutpostdiv */
  45. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x100);
  46. tmp |= 0x1;
  47. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x100);
  48. udelay(1);
  49. #endif
  50. }
  51. void sys_clk_config(void)
  52. {
  53. #ifndef CONFIG_TARGET_LIGHT_FPGA_FM_C910 /* for sillicon */
  54. unsigned int tmp;
  55. /* 1. double check all pll lock */
  56. udelay(60);
  57. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x80);
  58. if (!((tmp & 0x3fe) == 0x3fe))
  59. return;
  60. /* 2. update sys_pll to frac mode, 2438.5536MHz */
  61. /* switch share_sram_clk to audio_pll_foutvco */
  62. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
  63. tmp |= 0x2000;
  64. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104);
  65. /* switch audio_c906_cclk to audio_pll_foutvco */
  66. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x110);
  67. tmp |= 0x2000;
  68. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x110);
  69. /* switch audio_subsys_aclk to audio_pll_foutvco */
  70. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x108);
  71. tmp |= 0x2000;
  72. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x108);
  73. /* disable audio_i2s_src_clk */
  74. tmp = readl((void *)LIGHT_AUDIO_SUBSYS_ADDRBASE + 0x4);
  75. tmp &= ~0x20200;
  76. writel(tmp, (void *)LIGHT_AUDIO_SUBSYS_ADDRBASE + 0x4);
  77. /* disable peri_i2s_src_clk */
  78. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1f0);
  79. tmp &= ~0x2;
  80. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1f0);
  81. udelay(1);
  82. /* set sys_pll_foutvco to 2438.5536MHz */
  83. writel(0x20000000, (void *)LIGHT_AONCLK_ADDRBASE + 0x14);
  84. writel(0x03606501, (void *)LIGHT_AONCLK_ADDRBASE + 0x10);
  85. writel(0x209b3d08, (void *)LIGHT_AONCLK_ADDRBASE + 0x14);
  86. udelay(3);
  87. writel(0x009b3d08, (void *)LIGHT_AONCLK_ADDRBASE + 0x14);
  88. readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90);
  89. readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90);
  90. while(!(readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90) & 0x2));
  91. udelay(11);
  92. /* switch share_sram_clk to sys_pll_foutvco */
  93. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
  94. tmp &= ~0x2000;
  95. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104);
  96. /* switch audio_c906_cclk to sys_pll_foutvco */
  97. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x110);
  98. tmp &= ~0x2000;
  99. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x110);
  100. /* swith audio_subsys_aclk to sys_pll_foutvco */
  101. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x108);
  102. tmp &= ~0x2000;
  103. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x108);
  104. /* 3. update audio_pll, to frac mode, 884.736MHz */
  105. /* switch aonsys_clk to pad_osc_clk */
  106. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x100);
  107. tmp |= 0x10;
  108. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x100);
  109. /* set audio_pll_foutvco to frac mode, 884.736MHz */
  110. writel(0x20000000, (void *)LIGHT_AONCLK_ADDRBASE + 0x04);
  111. writel(0x01302401, (void *)LIGHT_AONCLK_ADDRBASE + 0x00);
  112. writel(0x20dd2f70, (void *)LIGHT_AONCLK_ADDRBASE + 0x04);
  113. udelay(3);
  114. writel(0x00dd2f70, (void *)LIGHT_AONCLK_ADDRBASE + 0x04);
  115. readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90);
  116. readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90);
  117. while(!(readl((void *)LIGHT_AONCLK_ADDRBASE + 0x90) & 0x1));
  118. udelay(11);
  119. /* switch aonsys_clk to audio_pll_foutpostdiv */
  120. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x100);
  121. tmp &= ~0x10;
  122. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x100);
  123. /* switch aoi2c_ic_clk to audio_pll_fout3 */
  124. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x11c);
  125. tmp &= ~0x1;
  126. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x11c);
  127. /* enable audio_i2s_src_clk */
  128. tmp = readl((void *)LIGHT_AUDIO_SUBSYS_ADDRBASE + 0x4);
  129. tmp |= 0x20200;
  130. writel(tmp, (void *)LIGHT_AUDIO_SUBSYS_ADDRBASE + 0x4);
  131. /* enable peri_i2s_src_clk */
  132. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1f0);
  133. tmp |= 0x2;
  134. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1f0);
  135. /* set apb3_cpusys_pclk to ahb2_cpusys_hclk/2 */
  136. /* CPU AHB 125MHz CPU pclk 125MHz */
  137. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x130);
  138. tmp &= ~0x8;
  139. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x130);
  140. udelay(1);
  141. tmp &= ~0x7;
  142. tmp |= 0x1;
  143. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x130);
  144. udelay(1);
  145. tmp |= 0x8;
  146. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x130);
  147. udelay(1);
  148. /* CPU AHB 125MHz CPU pclk 62.5MHz */
  149. /* set ahb2_cpusys_hclk to 250Mhz */
  150. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x120);
  151. tmp |= 0x20;
  152. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
  153. udelay(1);
  154. tmp &= ~0x10;
  155. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
  156. udelay(1);
  157. tmp &= ~0x7;
  158. tmp |= 0x2;
  159. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
  160. udelay(1);
  161. tmp |= 0x10;
  162. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
  163. udelay(1);
  164. tmp &= ~0x20;
  165. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x120);
  166. udelay(1);
  167. /* CPU AHB 250MHz CPU pclk 125MHz */
  168. /* perisys_apb_pclk to perisys_ahb_hclk/4 */
  169. /* perisys_ahb_hclk 62.5MHz perisys_apb_pclk 62.5MHz */
  170. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x150);
  171. tmp &= ~0x8;
  172. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x150);
  173. udelay(1);
  174. tmp &= ~0x7;
  175. tmp |= 0x3;
  176. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x150);
  177. udelay(1);
  178. tmp |= 0x8;
  179. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x150);
  180. udelay(1);
  181. /* perisys_ahb_hclk 62.5MHz perisys_apb_pclk 15.625MHz */
  182. /* perisys_ahb_hclk to 250MHz */
  183. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x140);
  184. tmp |= 0x20;
  185. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
  186. udelay(1);
  187. /* perisys_ahb_hclk 24MHz perisys_apb_pclk 6MHz */
  188. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x140);
  189. tmp &= ~0x10;
  190. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
  191. udelay(1);
  192. tmp &= ~0xf;
  193. tmp |= 0x2;
  194. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
  195. /* perisys_ahb_hclk 24MHz perisys_apb_pclk 6MHz */
  196. udelay(1);
  197. tmp |= 0x10;
  198. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
  199. udelay(1);
  200. tmp &= ~0x20;
  201. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x140);
  202. /* perisys_ahb_hclk 250MHz perisys_apb_pclk 62.5MHz */
  203. /* set dpu0_pll_div_clk to dpu0_pll_foutpostdiv/16 as 74.25MHz */
  204. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1e8);
  205. tmp &= ~0x100;
  206. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e8);
  207. udelay(1);
  208. tmp &= ~0xff;
  209. tmp |= 0x10;
  210. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e8);
  211. udelay(1);
  212. tmp |= 0x100;
  213. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e8);
  214. udelay(1);
  215. /* set dpu1_pll_div_clk to dpu1_pll_foutpostdiv/16 as 74.25MHz */
  216. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1ec);
  217. tmp &= ~0x100;
  218. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1ec);
  219. udelay(1);
  220. tmp &= ~0xff;
  221. tmp |= 0x10;
  222. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1ec);
  223. udelay(1);
  224. tmp |= 0x100;
  225. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1ec);
  226. udelay(1);
  227. /*5. enable necessary gates */
  228. /* enable dsp_subsys, vi_subsys, vo_subsys all clocls */
  229. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x220);
  230. tmp |= 0x7;
  231. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x220);
  232. /* AP rst_gen: VP/VO/VI/DSP */
  233. writel(0xf, (void *)LIGHT_APSYS_RSTGEN_ADDRBASE + 0x220);
  234. /* enable dsp0/1_cclk, dsp0/1_pclk */
  235. tmp = readl((void *)LIGHT_DSP_SUBSYS_ADDRBASE + 0x24);
  236. tmp |= 0xf;
  237. writel(tmp, (void *)LIGHT_DSP_SUBSYS_ADDRBASE + 0x24);
  238. /* enable gpu_core_clk, gpu_cfg_aclk */
  239. tmp = readl((void *)LIGHT_VO_SUBSYS_ADDRBASE + 0x50);
  240. tmp |= 0x18;
  241. writel(tmp, (void *)LIGHT_VO_SUBSYS_ADDRBASE + 0x50);
  242. tmp = readl((void *)LIGHT_VO_SUBSYS_R_ADDRBASE + 0x50);
  243. tmp |= 0x3ff;
  244. writel(tmp, (void *)LIGHT_VO_SUBSYS_R_ADDRBASE + 0x50);
  245. /* enable dpu_pixelclk0/1, dpu_hclk, dpu_aclk, dpu_cclk */
  246. tmp = readl((void *)LIGHT_VO_SUBSYS_ADDRBASE + 0x50);
  247. tmp |= 0x3e0;
  248. writel(tmp, (void *)LIGHT_VO_SUBSYS_ADDRBASE + 0x50);
  249. /* enable npu_axi_aclk, npu_core_clk */
  250. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
  251. tmp |= 0x30;
  252. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
  253. /* The boards other than the LightA board perform the bus down-speed operation */
  254. #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
  255. /* axi_sram_clk: 812.8512MHz -> 688.128MHz */
  256. tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
  257. tmp |= 0x2000;
  258. writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104);
  259. /* visys_aclk_m decrease frequency 792MHZ->594MHZ */
  260. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
  261. tmp &= ~0x00100000;
  262. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
  263. tmp &= ~0x000f0000;
  264. tmp |= 0x00140000;
  265. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
  266. /* vosys_aclk_m:792MHz->594MHz */
  267. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
  268. tmp &= ~0x00000020;
  269. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
  270. tmp &= ~0x0000000f;
  271. tmp |= 0x00000024;
  272. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
  273. /* vpsys_axi_aclk:792MHz->594MHz */
  274. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
  275. tmp &= ~0x00001000;
  276. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
  277. tmp &= ~0x00000f00;
  278. tmp |= 0x00001400;
  279. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
  280. /* npu_cclk:1000MHz->792MHz */
  281. tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
  282. tmp |= 0x00000040;
  283. writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
  284. /* Enable dpu auto clock gating */
  285. writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL0);
  286. writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL1);
  287. #endif
  288. #endif
  289. }
  290. void ddr_clk_config(int ddr_freq)
  291. {
  292. /* Do nothing for FPGA */
  293. }