spl.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433
  1. /*
  2. * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <linux/types.h>
  7. #include <common.h>
  8. #include <console.h>
  9. #include <cpu_func.h>
  10. #include <asm/csr.h>
  11. #include <asm/io.h>
  12. #include <asm/barrier.h>
  13. #include <spl.h>
  14. #include <asm/spl.h>
  15. #include <asm/arch-thead/boot_mode.h>
  16. #include <string.h>
  17. #include <asm/global_data.h>
  18. #include <linux/libfdt.h>
  19. #include <fdt_support.h>
  20. #include <fdtdec.h>
  21. #include "../common/uart.h"
  22. #include "../common/mini_printf.h"
  23. #include "lpddr-regu/ddr_regu.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. extern void init_ddr(void);
  26. extern void cpu_clk_config(int cpu_freq);
  27. extern void sys_clk_config(void);
  28. extern void ddr_clk_config(int ddr_freq);
  29. extern void show_sys_clk(void);
  30. extern int riscv_get_time(u64 *time);
  31. extern int pmic_reset_apcpu_voltage(void);
  32. struct light_reset_list {
  33. u32 val;
  34. u64 reg;
  35. };
  36. static struct light_reset_list light_pre_reset_lists[] = {
  37. {0x00000037, 0xFFFFF4403C}, /* Aon: Audio sys rst */
  38. };
  39. static struct light_reset_list light_post_reset_lists[] = {
  40. {0x00000001, 0xFFFF0151B0}, /* AP rst_gen: NPU rst */
  41. {0xFFFFFFFF, 0xFFFF041028}, /* DSP sys_reg: DSP rst */
  42. {0x00000002, 0xFFEF528000}, /* VO sys_reg: GPU rst */
  43. {0x00000003, 0xFFEF528000}, /* VO sys_reg: GPU rst */
  44. {0x00000007, 0xFFFF529004}, /* VO sys_reg: DPU rst */
  45. };
  46. static void light_pre_reset_config(void)
  47. {
  48. /* Reset VI/VO/VP/DSP/NPU/GPU/DPU */
  49. int i = 0;
  50. int entry_size;
  51. entry_size = ARRAY_SIZE(light_pre_reset_lists);
  52. while (i < entry_size) {
  53. writel(light_pre_reset_lists[i].val, (void *)(light_pre_reset_lists[i].reg));
  54. i++;
  55. }
  56. }
  57. static void light_post_reset_config(void)
  58. {
  59. /* Reset VI/VO/VP/DSP/NPU/GPU/DPU */
  60. int i = 0;
  61. int entry_size;
  62. entry_size = ARRAY_SIZE(light_post_reset_lists);
  63. while (i < entry_size) {
  64. writel(light_post_reset_lists[i].val, (void *)(light_post_reset_lists[i].reg));
  65. udelay(2);
  66. i++;
  67. }
  68. }
  69. void setup_ddr_pmp(void)
  70. {
  71. /* clear pmp entry0,entry1 setting in bootrom */
  72. writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x104));
  73. writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x100));
  74. writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x10c));
  75. writel(0x0 >> 12, (void *)(PMP_BASE_ADDR + 0x108));
  76. writel(0, (void *)(PMP_BASE_ADDR + 0x000));
  77. sync_is();
  78. }
  79. int get_rng(unsigned int *rng, int cnt)
  80. {
  81. int i;
  82. u64 seed;
  83. riscv_get_time(&seed);
  84. srand((unsigned int)seed);
  85. for (i = 0; i < cnt; i++)
  86. rng[i] = rand();
  87. return 0;
  88. }
  89. struct axiscr_region {
  90. long start;
  91. long end;
  92. };
  93. #define AXISCR_MAX_REGION_CNT 8
  94. #define OFFSET_AXISCR_LOCK 0x4
  95. #define OFFSET_AXISCR_MISC 0x8
  96. #define OFFSET_AXISCR_CYPHER 0x14
  97. #define OFFSET_AXISCR_REGION 0x40
  98. #define OFFSET_AXISCR_TRNG 0x100
  99. void setup_ddr_scramble(void)
  100. {
  101. int node, scr;
  102. unsigned int i, tmp;
  103. long base_addr, start, size, end;
  104. const fdt32_t *reg;
  105. const char *status;
  106. int lock_r, lock_w;
  107. const void *blob = (const void *)gd->fdt_blob;
  108. const char path[] = "/soc/axiscr";
  109. struct axiscr_region region[AXISCR_MAX_REGION_CNT] = {0};
  110. unsigned int rng[AXISCR_MAX_REGION_CNT*2] = {0}; // dual word per region
  111. int cnt = 0;
  112. node = fdt_path_offset(blob, path);
  113. if (node < 0) {
  114. printf("found no %s node in fdt\n", path);
  115. return;
  116. }
  117. reg = fdt_getprop(blob, node, "reg", NULL);
  118. if (!reg) {
  119. printf("Warning: device tree node '%s' has no address.\n", path);
  120. return;
  121. }
  122. base_addr = fdt_translate_address(blob, node, reg);
  123. status = fdt_getprop(blob, node, "lock-read", NULL);
  124. lock_r = (!strcmp(status, "okay")) ? 1:0;
  125. status = fdt_getprop(blob, node, "lock-write", NULL);
  126. lock_w = (!strcmp(status, "okay")) ? 1:0;
  127. for (scr = fdt_first_subnode(blob, node);
  128. scr >= 0; scr = fdt_next_subnode(blob, scr)) {
  129. if (!strcmp("okay", fdt_getprop(blob, scr, "status", NULL))) {
  130. reg = fdt_getprop(blob, scr, "region", NULL);
  131. start = fdt_translate_address(blob, scr, reg);
  132. reg += 2;
  133. size = fdt_translate_address(blob, scr, reg);
  134. end = start + size;
  135. region[cnt].start = start;
  136. region[cnt++].end = end;
  137. // TODO, check overlap
  138. }
  139. }
  140. if (cnt > 0) {
  141. if (cnt > AXISCR_MAX_REGION_CNT) {
  142. printf("failed to setup ddr scramble, since illegal axiscr region cnt<%d>", cnt);
  143. return;
  144. }
  145. get_rng(rng, cnt*2);
  146. for (i=0; i< cnt; i++) {
  147. // config region
  148. writel(region[i].start >> 12, (void *)(base_addr + OFFSET_AXISCR_REGION + i*8));
  149. writel(region[i].end >> 12, (void *)(base_addr + OFFSET_AXISCR_REGION + i*8+4));
  150. // config rng
  151. writel(rng[i*2], (void *)(base_addr + OFFSET_AXISCR_TRNG + i*8));
  152. writel(rng[i*2+1], (void *)(base_addr + OFFSET_AXISCR_TRNG + i*8+4));
  153. }
  154. // enable axi scramble
  155. tmp = readl((void *)(base_addr + OFFSET_AXISCR_MISC));
  156. tmp |= 1 << 18;
  157. writel(tmp, (void *)(base_addr + OFFSET_AXISCR_MISC));
  158. writel(1 << 0, (void *)(base_addr + OFFSET_AXISCR_CYPHER));
  159. tmp = readl((void *)(base_addr + OFFSET_AXISCR_MISC));
  160. tmp &= ~(0xff << 24);
  161. tmp |= 1 << 24;
  162. writel(tmp, (void *)(base_addr + OFFSET_AXISCR_MISC));
  163. // lock r/w
  164. tmp = readl((void *)(base_addr + OFFSET_AXISCR_LOCK));
  165. if (lock_r) {
  166. tmp |= 1 << 7;
  167. writel(tmp, (void *)(base_addr + OFFSET_AXISCR_LOCK));
  168. }
  169. if (lock_w) {
  170. tmp |= 1 << 8;
  171. writel(tmp, (void *)(base_addr + OFFSET_AXISCR_LOCK));
  172. }
  173. sync_is();
  174. }
  175. }
  176. struct axiparity_region {
  177. long start;
  178. long size;
  179. };
  180. #define AXIPARITY_MAX_REGION_CNT 8
  181. #define OFFSET_AXIPARITY_CFG 0x0
  182. #define OFFSET_AXIPARITY_REGION_CFG0 0x4
  183. #define OFFSET_AXIPARITY_REGION_CFG1 0x8
  184. #define OFFSET_AXIPARITY_SLFT_CFG0 0x44
  185. #define OFFSET_AXIPARITY_SLFT_CFG1 0x48
  186. #define OFFSET_AXIPARITY_SLFT_CFG2 0x4C
  187. void setup_ddr_parity(void)
  188. {
  189. int node, parity;
  190. unsigned int i, tmp;
  191. long base_addr, start, size;
  192. const fdt32_t *reg;
  193. const char *status;
  194. int lock;
  195. const void *blob = (const void *)gd->fdt_blob;
  196. const char path[] = "/soc/axiparity";
  197. struct axiparity_region region[AXIPARITY_MAX_REGION_CNT] = {0};
  198. int cnt = 0;
  199. node = fdt_path_offset(blob, path);
  200. if (node < 0) {
  201. printf("found no %s node in fdt\n", path);
  202. return;
  203. }
  204. reg = fdt_getprop(blob, node, "reg", NULL);
  205. if (!reg) {
  206. printf("Warning: device tree node '%s' has no address.\n", path);
  207. return;
  208. }
  209. base_addr = fdt_translate_address(blob, node, reg);
  210. status = fdt_getprop(blob, node, "lock", NULL);
  211. lock = (!strcmp(status, "okay")) ? 1:0;
  212. for (parity = fdt_first_subnode(blob, node);
  213. parity >= 0; parity = fdt_next_subnode(blob, parity)) {
  214. if (!strcmp("okay", fdt_getprop(blob, parity, "status", NULL))) {
  215. reg = fdt_getprop(blob, parity, "region", NULL);
  216. start = fdt_translate_address(blob, parity, reg);
  217. reg += 2;
  218. size = fdt_translate_address(blob, parity, reg);
  219. region[cnt].start = start;
  220. region[cnt++].size = size;
  221. // TODO, check overlap
  222. }
  223. }
  224. if (cnt > 0) {
  225. if (cnt > AXIPARITY_MAX_REGION_CNT) {
  226. printf("failed to setup ddr parity, since illegal axiparity region cnt<%d>", cnt);
  227. return;
  228. }
  229. for (i=0; i< cnt; i++) {
  230. // config region
  231. writel(region[i].start >> 12, (void *)(base_addr + OFFSET_AXIPARITY_REGION_CFG0 + i*8));
  232. writel(region[i].size >> 12, (void *)(base_addr + OFFSET_AXIPARITY_REGION_CFG1 + i*8));
  233. }
  234. // parity region number
  235. tmp = readl((void *)(base_addr + OFFSET_AXIPARITY_CFG));
  236. tmp |= cnt << 0;
  237. writel(tmp, (void *)(base_addr + OFFSET_AXIPARITY_CFG));
  238. for (i=0; i< cnt; i++) {
  239. // selftest config
  240. writel((region[i].start >> 12) << 8, (void *)(base_addr + OFFSET_AXIPARITY_SLFT_CFG0 + i*0xc));
  241. writel((region[i].size >> 12) << 8, (void *)(base_addr + OFFSET_AXIPARITY_SLFT_CFG1 + i*0xc));
  242. writel(1 << 0, (void *)(base_addr + OFFSET_AXIPARITY_SLFT_CFG2 + i*0xc));
  243. }
  244. mdelay(10); //4ms for 4GB SLFT
  245. // enable axi parity
  246. tmp = readl((void *)(base_addr + OFFSET_AXIPARITY_CFG));
  247. tmp &= ~(0xff << 24);
  248. tmp |= 1 << 24;
  249. writel(tmp, (void *)(base_addr + OFFSET_AXIPARITY_CFG));
  250. // lock
  251. if (lock) {
  252. tmp = readl((void *)(base_addr + OFFSET_AXIPARITY_CFG));
  253. tmp |= 1 << 8;
  254. writel(tmp, (void *)(base_addr + OFFSET_AXIPARITY_CFG));
  255. }
  256. sync_is();
  257. }
  258. }
  259. void cpu_performance_enable(void)
  260. {
  261. #define CSR_MHINT2_E 0x7cc
  262. #define CSR_MHINT4 0x7ce
  263. csr_write(CSR_SMPEN, 0x1);
  264. csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x20000);
  265. csr_write(CSR_MHINT4, csr_read(CSR_MHINT4) | 0x410);
  266. csr_write(CSR_MCCR2, 0xe2490009);
  267. csr_write(CSR_MHCR, 0x117f); // clear bit7 to disable indirect brantch prediction
  268. csr_write(CSR_MXSTATUS, 0x638000);
  269. csr_write(CSR_MHINT, 0x6e30c | (1<<22)); // set bit22 to close fence broadcast
  270. }
  271. static int bl1_img_have_head(unsigned long img_src_addr)
  272. {
  273. uint8_t *buffer = (uint8_t *)img_src_addr;
  274. if (memcmp(header_magic, &buffer[4], 4) == 0) {
  275. return 1;
  276. }
  277. return 0;
  278. }
  279. static void light_board_init_r(gd_t *gd, ulong dummy)
  280. {
  281. void (*entry)(long, long);
  282. void *sram_uboot_start;
  283. cpu_performance_enable();
  284. sram_uboot_start = (void *)(CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE);
  285. if (bl1_img_have_head((unsigned long)SRAM_BASE_ADDR) == 1) {
  286. uint32_t sign_en, encrypt_en;
  287. img_header_t *phead;
  288. phead = (img_header_t *)SRAM_BASE_ADDR;
  289. sign_en = phead->option_flag & 0x1;
  290. encrypt_en = phead->option_flag & 0x2;
  291. printf("image has header, sign %s, encrypt %s\n",
  292. sign_en ? "en" : "disabled",
  293. encrypt_en ? "en" : "disabled");
  294. } else {
  295. printf("image has no header\n");
  296. }
  297. memcpy((void *)CONFIG_SYS_TEXT_BASE, sram_uboot_start, CONFIG_SYS_MONITOR_LEN);
  298. entry = (void (*)(long, long))CONFIG_SYS_TEXT_BASE;
  299. invalidate_icache_all();
  300. flush_dcache_range(CONFIG_SYS_TEXT_BASE, CONFIG_SYS_TEXT_BASE + CONFIG_SYS_MONITOR_LEN);
  301. entry(0, 0);
  302. while (1);
  303. }
  304. void board_init_f(ulong dummy)
  305. {
  306. int ret;
  307. light_pre_reset_config();
  308. sys_clk_config();
  309. ret = spl_early_init();
  310. if (ret) {
  311. printf("spl_early_init() failed: %d\n", ret);
  312. hang();
  313. }
  314. arch_cpu_init_dm();
  315. light_post_reset_config();
  316. preloader_console_init();
  317. #ifdef CONFIG_PMIC_VOL_INIT
  318. ret = pmic_ddr_regu_init();
  319. if (ret) {
  320. printf("%s pmic init failed %d \n",__func__,ret);
  321. hang();
  322. }
  323. ret = pmic_ddr_set_voltage();
  324. if (ret) {
  325. printf("%s set ddr voltage failed \n",__func__);
  326. hang();
  327. }
  328. ret = pmic_reset_apcpu_voltage();
  329. if (ret) {
  330. printf("%s set apcpu voltage failed \n",__func__);
  331. hang();
  332. }
  333. #endif
  334. ddr_clk_config(0);
  335. cpu_clk_config(0);
  336. init_ddr();
  337. setup_ddr_scramble();
  338. setup_ddr_parity();
  339. setup_ddr_pmp();
  340. printf("ddr initialized, jump to uboot\n");
  341. light_board_init_r(NULL, 0);
  342. }
  343. void board_boot_order(u32 *spl_boot_list)
  344. {
  345. #define SOC_OM_ADDRBASE 0xffef018010
  346. switch (readl((void *)SOC_OM_ADDRBASE) & 0x7) {
  347. case 0:
  348. case 1:
  349. case 2:
  350. case 3:
  351. /* usb boot */
  352. break;
  353. case 4:
  354. /* emmc boot */
  355. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  356. break;
  357. case 5:
  358. /* sd boot */
  359. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  360. break;
  361. case 6:
  362. /* qspi-nand boot */
  363. spl_boot_list[0] = BOOT_DEVICE_NAND;
  364. break;
  365. case 7:
  366. /* spi-nor boot */
  367. spl_boot_list[0] = BOOT_DEVICE_SPI;
  368. break;
  369. default:
  370. spl_boot_list[0] = BOOT_DEVICE_NONE;
  371. }
  372. cpu_performance_enable();
  373. }