dw_iic_ll.h 29 KB

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  1. /*
  2. * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. */
  4. /******************************************************************************
  5. * @file dw_iic_ll.h
  6. * @brief header file for iic ll driver
  7. * @version V1.0
  8. * @date 10. Mar 2020
  9. ******************************************************************************/
  10. #ifndef _DW_IIC_LL_H_
  11. #define _DW_IIC_LL_H_
  12. #ifdef __cplusplus
  13. extern "C" {
  14. #endif
  15. /*
  16. * I2C register bit definitions
  17. */
  18. /* IC_CON, offset: 0x00 */
  19. #define DW_IIC_CON_DEFAUL (0x23U)
  20. #define DW_IIC_CON_MASTER_Pos (0U)
  21. #define DW_IIC_CON_MASTER_Msk (0x1U << DW_IIC_CON_MASTER_Pos)
  22. #define DW_IIC_CON_MASTER_EN DW_IIC_CON_MASTER_Msk
  23. #define DW_IIC_CON_SPEEDL_Pos (1U)
  24. #define DW_IIC_CON_SPEEDL_Msk (0x1U << DW_IIC_CON_SPEEDL_Pos)
  25. #define DW_IIC_CON_SPEEDL_EN DW_IIC_CON_SPEEDL_Msk
  26. #define DW_IIC_CON_SPEEDH_Pos (2U)
  27. #define DW_IIC_CON_SPEEDH_Msk (0x1U << DW_IIC_CON_SPEEDH_Pos)
  28. #define DW_IIC_CON_SPEEDH_EN DW_IIC_CON_SPEEDH_Msk
  29. #define DW_IIC_CON_SLAVE_ADDR_MODE_Pos (3U)
  30. #define DW_IIC_CON_SLAVE_ADDR_MODE_Msk (0x1U << DW_IIC_CON_SLAVE_ADDR_MODE_Pos)
  31. #define DW_IIC_CON_SLAVE_ADDR_MODE DW_IIC_CON_SLAVE_ADDR_MODE_Msk
  32. #define DW_IIC_CON_RESTART_Pos (5U)
  33. #define DW_IIC_CON_RESTART_Msk (0x1U << DW_IIC_CON_RESTART_Pos)
  34. #define DW_IIC_CON_RESTART_EN DW_IIC_CON_RESTART_Msk
  35. #define DW_IIC_CON_SLAVE_Pos (6U)
  36. #define DW_IIC_CON_SLAVE_Msk (0x1U << DW_IIC_CON_SLAVE_Pos)
  37. #define DW_IIC_CON_SLAVE_EN DW_IIC_CON_SLAVE_Msk
  38. /* IC_TAR, offset: 0x04 */
  39. #define DW_IIC_TAR_GC_OR_START_Pos (10U)
  40. #define DW_IIC_TAR_GC_OR_START_Msk (0x1U << DW_IIC_TAR_GC_OR_START_Pos)
  41. #define DW_IIC_TAR_GC_OR_START DW_IIC_TAR_GC_OR_START_Msk
  42. #define DW_IIC_TAR_SPECIAL_Pos (11U)
  43. #define DW_IIC_TAR_SPECIAL_Msk (0x1U << DW_IIC_TAR_SPECIAL_Pos)
  44. #define DW_IIC_TAR_SPECIAL DW_IIC_TAR_SPECIAL_Msk
  45. #define DW_IIC_TAR_MASTER_ADDR_MODE_Pos (12U)
  46. #define DW_IIC_TAR_MASTER_ADDR_MODE_Msk (0x1U << DW_IIC_TAR_MASTER_ADDR_MODE_Pos)
  47. #define DW_IIC_TAR_MASTER_ADDR_MODE DW_IIC_TAR_MASTER_ADDR_MODE_Msk
  48. /* IC_DATA_CMD, offset: 0x10 */
  49. #define DW_IIC_DATA_CMD_Pos (8U)
  50. #define DW_IIC_DATA_CMD_Msk (0x1U << DW_IIC_DATA_CMD_Pos)
  51. #define DW_IIC_DATA_CMD DW_IIC_DATA_CMD_Msk
  52. #define DW_IIC_DATA_SR_CMD (1<<8|1<<10)
  53. /* IC_INTR_STAT, offset: 0x2C */
  54. #define DW_IIC_INTR_RX_UNDER_Pos (0U)
  55. #define DW_IIC_INTR_RX_UNDER_Msk (0x1U << DW_IIC_INTR_RX_UNDER_Pos)
  56. #define DW_IIC_INTR_RX_UNDER DW_IIC_INTR_RX_UNDER_Msk
  57. #define DW_IIC_INTR_RX_OVER_Pos (1U)
  58. #define DW_IIC_INTR_RX_OVER_Msk (0x1U << DW_IIC_INTR_RX_OVER_Pos)
  59. #define DW_IIC_INTR_RX_OVER DW_IIC_INTR_RX_OVER_Msk
  60. #define DW_IIC_INTR_RX_FULL_Pos (2U)
  61. #define DW_IIC_INTR_RX_FULL_Msk (0x1U << DW_IIC_INTR_RX_FULL_Pos)
  62. #define DW_IIC_INTR_RX_FULL DW_IIC_INTR_RX_FULL_Msk
  63. #define DW_IIC_INTR_TX_OVER_Pos (3U)
  64. #define DW_IIC_INTR_TX_OVER_Msk (0x1U << DW_IIC_INTR_TX_OVER_Pos)
  65. #define DW_IIC_INTR_TX_OVER DW_IIC_INTR_TX_OVER_Msk
  66. #define DW_IIC_INTR_TX_EMPTY_Pos (4U)
  67. #define DW_IIC_INTR_TX_EMPTY_Msk (0x1U << DW_IIC_INTR_TX_EMPTY_Pos)
  68. #define DW_IIC_INTR_TX_EMPTY DW_IIC_INTR_TX_EMPTY_Msk
  69. #define DW_IIC_INTR_RD_REQ_Pos (5U)
  70. #define DW_IIC_INTR_RD_REQ_Msk (0x1U << DW_IIC_INTR_RD_REQ_Pos)
  71. #define DW_IIC_INTR_RD_REQ DW_IIC_INTR_RD_REQ_Msk
  72. #define DW_IIC_INTR_TX_ABRT_Pos (6U)
  73. #define DW_IIC_INTR_TX_ABRT_Msk (0x1U << DW_IIC_INTR_TX_ABRT_Pos)
  74. #define DW_IIC_INTR_TX_ABRT DW_IIC_INTR_TX_ABRT_Msk
  75. #define DW_IIC_INTR_RX_DONE_Pos (7U)
  76. #define DW_IIC_INTR_RX_DONE_Msk (0x1U << DW_IIC_INTR_RX_DONE_Pos)
  77. #define DW_IIC_INTR_RX_DONE DW_IIC_INTR_RX_DONE_Msk
  78. #define DW_IIC_INTR_ACTIVITY_Pos (8U)
  79. #define DW_IIC_INTR_ACTIVITY_Msk (0x1U << DW_IIC_INTR_ACTIVITY_Pos)
  80. #define DW_IIC_INTR_ACTIVITY DW_IIC_INTR_ACTIVITY_Msk
  81. #define DW_IIC_INTR_STOP_DET_Pos (9U)
  82. #define DW_IIC_INTR_STOP_DET_Msk (0x1U << DW_IIC_INTR_STOP_DET_Pos)
  83. #define DW_IIC_INTR_STOP_DET DW_IIC_INTR_STOP_DET_Msk
  84. #define DW_IIC_INTR_START_DET_Pos (10U)
  85. #define DW_IIC_INTR_START_DET_Msk (0x1U << DW_IIC_INTR_START_DET_Pos)
  86. #define DW_IIC_INTR_START_DET DW_IIC_INTR_START_DET_Msk
  87. #define DW_IIC_INTR_GEN_CALL_Pos (11U)
  88. #define DW_IIC_INTR_GEN_CALL_Msk (0x1U << DW_IIC_INTR_GEN_CALL_Pos)
  89. #define DW_IIC_INTR_GEN_CALL DW_IIC_INTR_GEN_CALL_Msk
  90. /* IC_INTR_MASK, offset: 0x30 */
  91. #define DW_IIC_M_RX_UNDER_Pos (0U)
  92. #define DW_IIC_M_RX_UNDER_Msk (0x1U << DW_IIC_INTR_RX_UNDER_Pos)
  93. #define DW_IIC_M_RX_UNDER DW_IIC_INTR_RX_UNDER_Msk
  94. #define DW_IIC_M_RX_OVER_Pos (1U)
  95. #define DW_IIC_M_RX_OVER_Msk (0x1U << DW_IIC_INTR_RX_OVER_Pos)
  96. #define DW_IIC_M_RX_OVER DW_IIC_INTR_RX_OVER_Msk
  97. #define DW_IIC_M_RX_FULL_Pos (2U)
  98. #define DW_IIC_M_RX_FULL_Msk (0x1U << DW_IIC_INTR_RX_FULL_Pos)
  99. #define DW_IIC_M_RX_FULL DW_IIC_INTR_RX_FULL_Msk
  100. #define DW_IIC_M_TX_OVER_Pos (3U)
  101. #define DW_IIC_M_TX_OVER_Msk (0x1U << DW_IIC_INTR_TX_OVER_Pos)
  102. #define DW_IIC_M_TX_OVER DW_IIC_INTR_TX_OVER_Msk
  103. #define DW_IIC_M_TX_EMPTY_Pos (4U)
  104. #define DW_IIC_M_TX_EMPTY_Msk (0x1U << DW_IIC_INTR_TX_EMPTY_Pos)
  105. #define DW_IIC_M_TX_EMPTY DW_IIC_INTR_TX_EMPTY_Msk
  106. #define DW_IIC_M_RD_REQ_Pos (5U)
  107. #define DW_IIC_M_RD_REQ_Msk (0x1U << DW_IIC_INTR_RD_REQ_Pos)
  108. #define DW_IIC_M_RD_REQ DW_IIC_INTR_RD_REQ_Msk
  109. #define DW_IIC_M_TX_ABRT_Pos (6U)
  110. #define DW_IIC_M_TX_ABRT_Msk (0x1U << DW_IIC_INTR_TX_ABRT_Pos)
  111. #define DW_IIC_M_TX_ABRT DW_IIC_INTR_TX_ABRT_Msk
  112. #define DW_IIC_M_RX_DONE_Pos (7U)
  113. #define DW_IIC_M_RX_DONE_Msk (0x1U << DW_IIC_INTR_RX_DONE_Pos)
  114. #define DW_IIC_M_RX_DONE DW_IIC_INTR_RX_DONE_Msk
  115. #define DW_IIC_M_ACTIVITY_Pos (8U)
  116. #define DW_IIC_M_ACTIVITY_Msk (0x1U << DW_IIC_INTR_ACTIVITY_Pos)
  117. #define DW_IIC_M_ACTIVITY DW_IIC_INTR_ACTIVITY_Msk
  118. #define DW_IIC_M_STOP_DET_Pos (9U)
  119. #define DW_IIC_M_STOP_DET_Msk (0x1U << DW_IIC_INTR_STOP_DET_Pos)
  120. #define DW_IIC_M_STOP_DET DW_IIC_INTR_STOP_DET_Msk
  121. #define DW_IIC_M_START_DET_Pos (10U)
  122. #define DW_IIC_M_START_DET_Msk (0x1U << DW_IIC_INTR_START_DET_Pos)
  123. #define DW_IIC_M_START_DET DW_IIC_INTR_START_DET_Msk
  124. #define DW_IIC_M_GEN_CALL_Pos (11U)
  125. #define DW_IIC_M_GEN_CALL_Msk (0x1U << DW_IIC_INTR_GEN_CALL_Pos)
  126. #define DW_IIC_M_GEN_CALL DW_IIC_INTR_GEN_CALL_Msk
  127. #define DW_IIC_INTR_DEFAULT_MASK ( DW_IIC_M_RX_FULL | DW_IIC_M_TX_EMPTY | DW_IIC_M_TX_ABRT | DW_IIC_M_STOP_DET)
  128. /* IC_RAW_INTR_STAT, offset: 0x34 */
  129. #define DW_IIC_RAW_RX_UNDER_Pos (0U)
  130. #define DW_IIC_RAW_RX_UNDER_Msk (0x1U << DW_IIC_INTR_RX_UNDER_Pos)
  131. #define DW_IIC_RAW_RX_UNDER DW_IIC_INTR_RX_UNDER_Msk
  132. #define DW_IIC_RAW_RX_OVER_Pos (1U)
  133. #define DW_IIC_RAW_RX_OVER_Msk (0x1U << DW_IIC_INTR_RX_OVER_Pos)
  134. #define DW_IIC_RAW_RX_OVER DW_IIC_INTR_RX_OVER_Msk
  135. #define DW_IIC_RAW_RX_FULL_Pos (2U)
  136. #define DW_IIC_RAW_RX_FULL_Msk (0x1U << DW_IIC_INTR_RX_FULL_Pos)
  137. #define DW_IIC_RAW_RX_FULL DW_IIC_INTR_RX_FULL_Msk
  138. #define DW_IIC_RAW_TX_OVER_Pos (3U)
  139. #define DW_IIC_RAW_TX_OVER_Msk (0x1U << DW_IIC_INTR_TX_OVER_Pos)
  140. #define DW_IIC_RAW_TX_OVER DW_IIC_INTR_TX_OVER_Msk
  141. #define DW_IIC_RAW_TX_EMPTY_Pos (4U)
  142. #define DW_IIC_RAW_TX_EMPTY_Msk (0x1U << DW_IIC_INTR_TX_EMPTY_Pos)
  143. #define DW_IIC_RAW_TX_EMPTY DW_IIC_INTR_TX_EMPTY_Msk
  144. #define DW_IIC_RAW_RD_REQ_Pos (5U)
  145. #define DW_IIC_RAW_RD_REQ_Msk (0x1U << DW_IIC_INTR_RD_REQ_Pos)
  146. #define DW_IIC_RAW_RD_REQ DW_IIC_INTR_RD_REQ_Msk
  147. #define DW_IIC_RAW_TX_ABRT_Pos (6U)
  148. #define DW_IIC_RAW_TX_ABRT_Msk (0x1U << DW_IIC_INTR_TX_ABRT_Pos)
  149. #define DW_IIC_RAW_TX_ABRT DW_IIC_INTR_TX_ABRT_Msk
  150. #define DW_IIC_RAW_RX_DONE_Pos (7U)
  151. #define DW_IIC_RAW_RX_DONE_Msk (0x1U << DW_IIC_INTR_RX_DONE_Pos)
  152. #define DW_IIC_RAW_RX_DONE DW_IIC_INTR_RX_DONE_Msk
  153. #define DW_IIC_RAW_ACTIVITY_Pos (8U)
  154. #define DW_IIC_RAW_ACTIVITY_Msk (0x1U << DW_IIC_INTR_ACTIVITY_Pos)
  155. #define DW_IIC_RAW_ACTIVITY DW_IIC_INTR_ACTIVITY_Msk
  156. #define DW_IIC_RAW_STOP_DET_Pos (9U)
  157. #define DW_IIC_RAW_STOP_DET_Msk (0x1U << DW_IIC_INTR_STOP_DET_Pos)
  158. #define DW_IIC_RAW_STOP_DET DW_IIC_INTR_STOP_DET_Msk
  159. #define DW_IIC_RAW_START_DET_Pos (10U)
  160. #define DW_IIC_RAW_START_DET_Msk (0x1U << DW_IIC_INTR_START_DET_Pos)
  161. #define DW_IIC_RAW_START_DET DW_IIC_INTR_START_DET_Msk
  162. #define DW_IIC_RAW_GEN_CALL_Pos (11U)
  163. #define DW_IIC_RAW_GEN_CALL_Msk (0x1U << DW_IIC_INTR_GEN_CALL_Pos)
  164. #define DW_IIC_RAW_GEN_CALL DW_IIC_INTR_GEN_CALL_Msk
  165. /* IC_ENABLE, offset: 0x6C */
  166. #define DW_IIC_ENABLE_Pos (0U)
  167. #define DW_IIC_ENABLE_Msk (0x1U << DW_IIC_ENABLE_Pos)
  168. #define DW_IIC_EN DW_IIC_ENABLE_Msk
  169. /* IC_STATUS, offset: 0x70 */
  170. #define DW_IIC_STATUS_ACTIVITY_Pos (0U)
  171. #define DW_IIC_STATUS_ACTIVITY_Msk (0x1U << DW_IIC_STATUS_ACTIVITY_Pos)
  172. #define DW_IIC_STATUS_ACTIVITY_STATE DW_IIC_STATUS_ACTIVITY_Msk
  173. #define DW_IIC_STATUS_TFNE_Pos (1U)
  174. #define DW_IIC_STATUS_TFNE_Msk (0x1U << DW_IIC_STATUS_TFNE_Pos)
  175. #define DW_IIC_TXFIFO_NOT_FULL_STATE DW_IIC_STATUS_TFNE_Msk
  176. #define DW_IIC_STATUS_TFE_Pos (2U)
  177. #define DW_IIC_STATUS_TFE_Msk (0x1U << DW_IIC_STATUS_TFE_Pos)
  178. #define DW_IIC_TXFIFO_EMPTY_STATE DW_IIC_STATUS_TFE_Msk
  179. #define DW_IIC_STATUS_RFNE_Pos (3U)
  180. #define DW_IIC_STATUS_RFNE_Msk (0x1U << DW_IIC_STATUS_RFNE_Pos)
  181. #define DW_IIC_RXFIFO_NOT_EMPTY_STATE DW_IIC_STATUS_RFNE_Msk
  182. #define DW_IIC_STATUS_REF_Pos (4U)
  183. #define DW_IIC_STATUS_REF_Msk (0x1U << DW_IIC_STATUS_REF_Pos)
  184. #define DW_IIC_RXFIFO_FULL_STATE DW_IIC_STATUS_REF_Msk
  185. #define DW_IIC_STATUS_MST_ACTIVITY_Pos (5U)
  186. #define DW_IIC_STATUS_MST_ACTIVITY_Msk (0x1U << DW_IIC_STATUS_MST_ACTIVITY_Pos)
  187. #define DW_IIC_MST_ACTIVITY_STATE DW_IIC_STATUS_MST_ACTIVITY_Msk
  188. #define DW_IIC_STATUS_SLV_ACTIVITY_Pos (6U)
  189. #define DW_IIC_STATUS_SLV_ACTIVITY_Msk (0x1U << DW_IIC_STATUS_SLV_ACTIVITY_Pos)
  190. #define DW_IIC_SLV_ACTIVITY_STATE DW_IIC_STATUS_SLV_ACTIVITY_Msk
  191. /* IC_TX_ABRT_SOURCE, offset: 0x80 */
  192. #define DW_IIC_TX_ABRT_7B_ADDR_NOACK_Pos (0U)
  193. #define DW_IIC_TX_ABRT_7B_ADDR_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_7B_ADDR_NOACK_Pos)
  194. #define DW_IIC_TX_ABRT_7B_ADDR_NOACK DW_IIC_TX_ABRT_7B_ADDR_NOACK_Msk
  195. #define DW_IIC_TX_ABRT_10ADDR1_NOACK_Pos (1U)
  196. #define DW_IIC_TX_ABRT_10ADDR1_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_10ADDR1_NOACK_Pos)
  197. #define DW_IIC_TX_ABRT_10ADDR1_NOACK DW_IIC_TX_ABRT_10ADDR1_NOACK_Msk
  198. #define DW_IIC_TX_ABRT_10ADDR2_NOACK_Pos (2U)
  199. #define DW_IIC_TX_ABRT_10ADDR2_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_10ADDR2_NOACK_Pos)
  200. #define DW_IIC_TX_ABRT_10ADDR2_NOACK DW_IIC_TX_ABRT_10ADDR2_NOACK_Msk
  201. #define DW_IIC_TX_ABRT_TXDATA_NOACK_Pos (3U)
  202. #define DW_IIC_TX_ABRT_TXDATA_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_TXDATA_NOACK_Pos)
  203. #define DW_IIC_TX_ABRT_TXDATA_NOACK DW_IIC_TX_ABRT_TXDATA_NOACK_Msk
  204. #define DW_IIC_TX_ABRT_GCALL_NOACK_Pos (4U)
  205. #define DW_IIC_TX_ABRT_GCALL_NOACK_Msk (0x1U << DW_IIC_TX_ABRT_GCALL_NOACK_Pos)
  206. #define DW_IIC_TX_ABRT_GCALL_NOACK DW_IIC_TX_ABRT_GCALL_NOACK_Msk
  207. #define DW_IIC_TX_ABRT_GCALL_READ_Pos (5U)
  208. #define DW_IIC_TX_ABRT_GCALL_READ_Msk (0x1U << DW_IIC_TX_ABRT_GCALL_READ_Pos)
  209. #define DW_IIC_TX_ABRT_GCALL_READ DW_IIC_TX_ABRT_GCALL_READ_Msk
  210. #define DW_IIC_TX_ABRT_HS_ACKDET_Pos (6U)
  211. #define DW_IIC_TX_ABRT_HS_ACKDET_Msk (0x1U << DW_IIC_TX_ABRT_HS_ACKDET_Pos)
  212. #define DW_IIC_TX_ABRT_HS_ACKDET DW_IIC_TX_ABRT_HS_ACKDET_Msk
  213. #define DW_IIC_TX_ABRT_SBYTE_ACKDET_Pos (7U)
  214. #define DW_IIC_TX_ABRT_SBYTE_ACKDET_Msk (0x1U << DW_IIC_TX_ABRT_SBYTE_ACKDET_Pos)
  215. #define DW_IIC_TX_ABRT_SBYTE_ACKDET DW_IIC_TX_ABRT_SBYTE_ACKDET_Msk
  216. #define DW_IIC_TX_ABRT_HS_NORSTRT_Pos (8U)
  217. #define DW_IIC_TX_ABRT_HS_NORSTRT_Msk (0x1U << DW_IIC_TX_ABRT_HS_NORSTRT_Pos)
  218. #define DW_IIC_TX_ABRT_HS_NORSTRT DW_IIC_TX_ABRT_HS_NORSTRT_Msk
  219. #define DW_IIC_TX_ABRT_SBYTE_NORSTRT_Pos (9U)
  220. #define DW_IIC_TX_ABRT_SBYTE_NORSTRT_Msk (0x1U << DW_IIC_TX_ABRT_SBYTE_NORSTRT_Pos)
  221. #define DW_IIC_TX_ABRT_SBYTE_NORSTRT DW_IIC_TX_ABRT_SBYTE_NORSTRT_Msk
  222. #define DW_IIC_TX_ABRT_10B_RD_NORSTRT_Pos (10U)
  223. #define DW_IIC_TX_ABRT_10B_RD_NORSTRT_Msk (0x1U << DW_IIC_TX_ABRT_10B_RD_NORSTRT_Pos)
  224. #define DW_IIC_TX_ABRT_10B_RD_NORSTRT DW_IIC_TX_ABRT_10B_RD_NORSTRT_Msk
  225. #define DW_IIC_TX_ABRT_ARB_MASTER_DIS_Pos (11U)
  226. #define DW_IIC_TX_ABRT_ARB_MASTER_DIS_Msk (0x1U << DW_IIC_TX_ABRT_ARB_MASTER_DIS_Pos)
  227. #define DW_IIC_TX_ABRT_ARB_MASTER_DIS DW_IIC_TX_ABRT_ARB_MASTER_DIS_Msk
  228. #define DW_IIC_TX_ABRT_ARB_LOST_Pos (12U)
  229. #define DW_IIC_TX_ABRT_ARB_LOST_Msk (0x1U << DW_IIC_TX_ABRT_ARB_LOST_Pos)
  230. #define DW_IIC_TX_ABRT_ARB_LOST DW_IIC_TX_ABRT_ARB_LOST_Msk
  231. #define DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO_Pos (13U)
  232. #define DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO_Msk (0x1U << DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO_Pos)
  233. #define DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO DW_IIC_TX_ABRT_SLVFLUSH_TXFIFO_Msk
  234. #define DW_IIC_TX_ABRT_SLV_ARBLOST_Pos (14U)
  235. #define DW_IIC_TX_ABRT_SLV_ARBLOST_Msk (0x1U << DW_IIC_TX_ABRT_SLV_ARBLOST_Pos)
  236. #define DW_IIC_TX_ABRT_SLV_ARBLOST DW_IIC_TX_ABRT_SLV_ARBLOST_Msk
  237. #define DW_IIC_TX_ABRT_SLVRD_INTX_Pos (15U)
  238. #define DW_IIC_TX_ABRT_SLVRD_INTX_Msk (0x1U << DW_IIC_TX_ABRT_SLVRD_INTX_Pos)
  239. #define DW_IIC_TX_ABRT_SLVRD_INTX DW_IIC_TX_ABRT_SLVRD_INTX_Msk
  240. /* IC_DMA_CR, offset: 0x88 */
  241. #define DW_IIC_DMA_CR_RDMAE_Pos (0U)
  242. #define DW_IIC_DMA_CR_RDMAE_Msk (0x1U << DW_IIC_DMA_CR_RDMAE_Pos)
  243. #define DW_IIC_DMA_CR_RDMAE DW_IIC_DMA_CR_RDMAE_Msk
  244. #define DW_IIC_DMA_CR_TDMAE_Pos (1U)
  245. #define DW_IIC_DMA_CR_TDMAE_Msk (0x1U << DW_IIC_DMA_CR_TDMAE_Pos)
  246. #define DW_IIC_DMA_CR_TDMAE DW_IIC_DMA_CR_TDMAE_Msk
  247. /* IC_DMA_TDLR, offset: 0x8C */
  248. #define DW_IIC_DMA_TDLR_Msk (0x7U)
  249. /* IC_DMA_RDLR, offset: 0x90 */
  250. #define DW_IIC_DMA_RDLR_Msk (0x7U)
  251. /* IC_GEN_CALL_EN, offset: 0xA0 */
  252. #define DW_IIC_GEN_CALL_EN_Pos (0U)
  253. #define DW_IIC_GEN_CALL_EN_Msk (0x1U << DW_IIC_GEN_CALL_EN_Pos)
  254. #define DW_IIC_GEN_CALL_EN DW_IIC_GEN_CALL_EN_Msk
  255. /* IC_FIFO_RST_EN, offset: 0xA4 */
  256. #define DW_IIC_FIFO_RST_EN_Pos (0U)
  257. #define DW_IIC_FIFO_RST_EN_Msk (0x1U << DW_IIC_FIFO_RST_EN_Pos)
  258. #define DW_IIC_FIFO_RST_EN DW_IIC_FIFO_RST_EN_Msk
  259. #define TXFIFO_IRQ_TH (0x4U)
  260. #define RXFIFO_IRQ_TH (0x2U)
  261. #define IIC_MAX_FIFO (0x8U)
  262. /* IIC default value definitions */
  263. #define DW_IIC_TIMEOUT_DEF_VAL 0x10000000U
  264. #define DW_IIC_EEPROM_MAX_WRITE_LEN 0X1U
  265. typedef struct {
  266. volatile uint32_t IC_CON; /* Offset: 0x000 (R/W) I2C Control */
  267. volatile uint32_t IC_TAR; /* Offset: 0x004 (R/W) I2C target address */
  268. volatile uint32_t IC_SAR; /* Offset: 0x008 (R/W) I2C slave address */
  269. volatile uint32_t IC_HS_MADDR; /* Offset: 0x00C (R/W) I2C HS Master Mode Code Address */
  270. volatile uint32_t IC_DATA_CMD; /* Offset: 0x010 (R/W) I2C RX/TX Data Buffer and Command */
  271. volatile uint32_t IC_SS_SCL_HCNT; /* Offset: 0x014 (R/W) Standard speed I2C Clock SCL High Count */
  272. volatile uint32_t IC_SS_SCL_LCNT; /* Offset: 0x018 (R/W) Standard speed I2C Clock SCL Low Count */
  273. volatile uint32_t IC_FS_SCL_HCNT; /* Offset: 0x01C (R/W) Fast speed I2C Clock SCL High Count */
  274. volatile uint32_t IC_FS_SCL_LCNT; /* Offset: 0x020 (R/W) Fast speed I2C Clock SCL Low Count */
  275. volatile uint32_t IC_HS_SCL_HCNT; /* Offset: 0x024 (R/W) High speed I2C Clock SCL High Count*/
  276. volatile uint32_t IC_HS_SCL_LCNT; /* Offset: 0x028 (R/W) High speed I2C Clock SCL Low Count */
  277. volatile uint32_t IC_INTR_STAT; /* Offset: 0x02C (R) I2C Interrupt Status */
  278. volatile uint32_t IC_INTR_MASK; /* Offset: 0x030 (R/W) I2C Interrupt Mask */
  279. volatile uint32_t IC_RAW_INTR_STAT; /* Offset: 0x034 (R) I2C Raw Interrupt Status */
  280. volatile uint32_t IC_RX_TL; /* Offset: 0x038 (R/W) I2C Receive FIFO Threshold */
  281. volatile uint32_t IC_TX_TL; /* Offset: 0x03C (R/W) I2C Transmit FIFO Threshold */
  282. volatile uint32_t IC_CLR_INTR; /* Offset: 0x040 (R) Clear combined and individual interrupts*/
  283. volatile uint32_t IC_CLR_RX_UNDER; /* Offset: 0x044 (R) I2C Clear RX_UNDER interrupt */
  284. volatile uint32_t IC_CLR_RX_OVER; /* Offset: 0x048 (R) I2C Clear RX_OVER interrupt */
  285. volatile uint32_t IC_CLR_TX_OVER; /* Offset: 0x04C (R) I2C Clear TX_OVER interrupt */
  286. volatile uint32_t IC_CLR_RD_REQ; /* Offset: 0x050 (R) I2C Clear RD_REQ interrupt */
  287. volatile uint32_t IC_CLR_TX_ABRT; /* Offset: 0x054 (R) I2C Clear TX_ABRT interrupt */
  288. volatile uint32_t IC_CLR_RX_DONE; /* Offset: 0x058 (R) I2C Clear RX_DONE interrupt */
  289. volatile uint32_t IC_CLR_ACTIVITY; /* Offset: 0x05C (R) I2C Clear ACTIVITY interrupt */
  290. volatile uint32_t IC_CLR_STOP_DET; /* Offset: 0x060 (R) I2C Clear STOP_DET interrupt */
  291. volatile uint32_t IC_CLR_START_DET; /* Offset: 0x064 (R) I2C Clear START_DET interrupt */
  292. volatile uint32_t IC_CLR_GEN_CALL; /* Offset: 0x068 (R) I2C Clear GEN_CAL interrupt */
  293. volatile uint32_t IC_ENABLE; /* Offset: 0x06C (R/W) I2C enable */
  294. volatile uint32_t IC_STATUS; /* Offset: 0x070 (R) I2C status register */
  295. volatile uint32_t IC_TXFLR; /* Offset: 0x074 (R) Transmit FIFO Level register */
  296. volatile uint32_t IC_RXFLR; /* Offset: 0x078 (R) Receive FIFO Level Register */
  297. uint32_t RESERVED; /* Offset: 0x07C (R) RESERVED */
  298. volatile uint32_t IC_TX_ABRT_SOURCE; /* Offset: 0x080 (R/W) I2C Transmit Abort Status Register */
  299. volatile uint32_t IC_SAR1; /* Offset: 0x084 (R/W) I2C Slave Address1 */
  300. volatile uint32_t IC_DMA_CR; /* Offset: 0x088 (R/W) DMA Control Register for transmit and receive handshaking interface */
  301. volatile uint32_t IC_DMA_TDLR; /* Offset: 0x08C (R/W) DMA Transmit Data Level */
  302. volatile uint32_t IC_DMA_RDLR; /* Offset: 0x090 (R/W) DMA Receive Data Level */
  303. volatile uint32_t IC_SAR2; /* Offset: 0x094 (R/W) I2C Slave Address2 */
  304. volatile uint32_t IC_SAR3; /* Offset: 0x098 (R/W) I2C Slave Address3 */
  305. volatile uint32_t IC_MULTI_SLAVE; /* Offset: 0x09C (R/W) I2C address number in slave mode */
  306. volatile uint32_t IC_GEN_CALL_EN; /* Offset: 0x0A0 (R/W) I2C general call mask register when I2C is in the slave mode */
  307. volatile uint32_t IC_FIFO_RST_EN; /* Offset: 0x0A4 (R/W) I2C FIFO flush register when I2C is in the slave transfer mode*/
  308. } dw_iic_regs_t;
  309. static inline void dw_iic_enable(dw_iic_regs_t *iic_base)
  310. {
  311. iic_base->IC_ENABLE = DW_IIC_EN;
  312. }
  313. static inline void dw_iic_disable(dw_iic_regs_t *iic_base)
  314. {
  315. /* First clear ACTIVITY, then Disable IIC */
  316. iic_base->IC_CLR_ACTIVITY;
  317. iic_base->IC_ENABLE = ~DW_IIC_EN;
  318. }
  319. static inline uint32_t dw_iic_get_iic_status(dw_iic_regs_t *iic_base)
  320. {
  321. return iic_base->IC_ENABLE;
  322. }
  323. static inline void dw_iic_enable_restart(dw_iic_regs_t *iic_base)
  324. {
  325. iic_base->IC_CON |= DW_IIC_CON_RESTART_EN;
  326. }
  327. static inline void dw_iic_master_enable_transmit_irq(dw_iic_regs_t *iic_base)
  328. {
  329. iic_base->IC_INTR_MASK = DW_IIC_INTR_TX_EMPTY | DW_IIC_INTR_TX_OVER | DW_IIC_INTR_STOP_DET;
  330. iic_base->IC_CLR_INTR;
  331. }
  332. static inline void dw_iic_slave_enable_transmit_irq(dw_iic_regs_t *iic_base)
  333. {
  334. iic_base->IC_INTR_MASK = DW_IIC_INTR_RD_REQ | DW_IIC_INTR_STOP_DET;
  335. iic_base->IC_CLR_INTR;
  336. }
  337. static inline void dw_iic_master_enable_receive_irq(dw_iic_regs_t *iic_base)
  338. {
  339. iic_base->IC_INTR_MASK = DW_IIC_INTR_STOP_DET | DW_IIC_INTR_RX_FULL | DW_IIC_INTR_RX_OVER;
  340. iic_base->IC_CLR_INTR;
  341. }
  342. static inline void dw_iic_slave_enable_receive_irq(dw_iic_regs_t *iic_base)
  343. {
  344. iic_base->IC_INTR_MASK = DW_IIC_INTR_STOP_DET | DW_IIC_INTR_RX_FULL;
  345. iic_base->IC_CLR_INTR;
  346. }
  347. static inline void dw_iic_clear_all_irq(dw_iic_regs_t *iic_base)
  348. {
  349. iic_base->IC_CLR_INTR;
  350. iic_base->IC_CLR_RX_UNDER;
  351. iic_base->IC_CLR_RX_OVER;
  352. iic_base->IC_CLR_TX_OVER;
  353. iic_base->IC_CLR_RD_REQ;
  354. iic_base->IC_CLR_TX_ABRT;
  355. iic_base->IC_CLR_RX_DONE;
  356. iic_base->IC_CLR_ACTIVITY;
  357. iic_base->IC_CLR_STOP_DET;
  358. iic_base->IC_CLR_START_DET;
  359. iic_base->IC_CLR_GEN_CALL;
  360. }
  361. static inline void dw_iic_set_slave_10bit_addr_mode(dw_iic_regs_t *iic_base)
  362. {
  363. iic_base->IC_CON |= DW_IIC_CON_SLAVE_ADDR_MODE;
  364. }
  365. static inline void dw_iic_set_slave_7bit_addr_mode(dw_iic_regs_t *iic_base)
  366. {
  367. iic_base->IC_CON &= ~DW_IIC_CON_SLAVE_ADDR_MODE;
  368. }
  369. static inline void dw_iic_set_master_10bit_addr_mode(dw_iic_regs_t *iic_base)
  370. {
  371. iic_base->IC_TAR |= DW_IIC_TAR_MASTER_ADDR_MODE;
  372. }
  373. static inline void dw_iic_set_master_7bit_addr_mode(dw_iic_regs_t *iic_base)
  374. {
  375. iic_base->IC_TAR &= ~DW_IIC_TAR_MASTER_ADDR_MODE;
  376. }
  377. static inline void dw_iic_set_standard_scl_hcnt(dw_iic_regs_t *iic_base, uint32_t cnt)
  378. {
  379. iic_base->IC_SS_SCL_HCNT = cnt;
  380. }
  381. static inline void dw_iic_set_standard_scl_lcnt(dw_iic_regs_t *iic_base, uint32_t cnt)
  382. {
  383. iic_base->IC_SS_SCL_LCNT = cnt;
  384. }
  385. static inline void dw_iic_set_fast_scl_hcnt(dw_iic_regs_t *iic_base, uint32_t cnt)
  386. {
  387. iic_base->IC_FS_SCL_HCNT = cnt;
  388. }
  389. static inline void dw_iic_set_fast_scl_lcnt(dw_iic_regs_t *iic_base, uint32_t cnt)
  390. {
  391. iic_base->IC_FS_SCL_LCNT = cnt;
  392. }
  393. static inline void dw_iic_set_high_scl_hcnt(dw_iic_regs_t *iic_base, uint32_t cnt)
  394. {
  395. iic_base->IC_HS_SCL_HCNT = cnt;
  396. }
  397. static inline void dw_iic_set_high_scl_lcnt(dw_iic_regs_t *iic_base, uint32_t cnt)
  398. {
  399. iic_base->IC_HS_SCL_LCNT = cnt;
  400. }
  401. static inline void dw_iic_set_own_address(dw_iic_regs_t *iic_base, uint32_t address)
  402. {
  403. iic_base->IC_SAR = address;
  404. }
  405. static inline void dw_iic_set_transmit_fifo_threshold(dw_iic_regs_t *iic_base, uint32_t level)
  406. {
  407. iic_base->IC_TX_TL = level;
  408. }
  409. static inline void dw_iic_set_receive_fifo_threshold(dw_iic_regs_t *iic_base, uint32_t level)
  410. {
  411. iic_base->IC_RX_TL = level - 1U;
  412. }
  413. static inline uint32_t dw_iic_get_transmit_fifo_num(dw_iic_regs_t *iic_base)
  414. {
  415. return iic_base->IC_TXFLR;
  416. }
  417. static inline uint32_t dw_iic_get_receive_fifo_num(dw_iic_regs_t *iic_base)
  418. {
  419. return iic_base->IC_RXFLR;
  420. }
  421. static inline void dw_iic_transmit_data(dw_iic_regs_t *iic_base, uint8_t data)
  422. {
  423. iic_base->IC_DATA_CMD = data;
  424. }
  425. static inline uint32_t dw_iic_get_iic_state(dw_iic_regs_t *iic_base)
  426. {
  427. return iic_base->IC_STATUS;
  428. }
  429. static inline uint8_t dw_iic_receive_data(dw_iic_regs_t *iic_base)
  430. {
  431. return (uint8_t)iic_base->IC_DATA_CMD;
  432. }
  433. static inline void dw_iic_data_cmd(dw_iic_regs_t *iic_base)
  434. {
  435. iic_base->IC_DATA_CMD = DW_IIC_DATA_CMD;
  436. }
  437. static inline void dw_iic_data_sr_cmd(dw_iic_regs_t *iic_base)
  438. {
  439. iic_base->IC_DATA_CMD = DW_IIC_DATA_SR_CMD;
  440. }
  441. static inline void dw_iic_fifo_rst(dw_iic_regs_t *iic_base, uint32_t en)
  442. {
  443. iic_base->IC_FIFO_RST_EN = (en & DW_IIC_FIFO_RST_EN_Msk);
  444. }
  445. static inline void dw_iic_dma_transmit_enable(dw_iic_regs_t *iic_base)
  446. {
  447. iic_base->IC_DMA_CR |= DW_IIC_DMA_CR_TDMAE;
  448. }
  449. static inline void dw_iic_dma_transmit_disable(dw_iic_regs_t *iic_base)
  450. {
  451. iic_base->IC_DMA_CR &= ~DW_IIC_DMA_CR_TDMAE;
  452. }
  453. static inline void dw_iic_dma_receive_enable(dw_iic_regs_t *iic_base)
  454. {
  455. iic_base->IC_DMA_CR |= DW_IIC_DMA_CR_RDMAE;
  456. }
  457. static inline void dw_iic_dma_receive_disable(dw_iic_regs_t *iic_base)
  458. {
  459. iic_base->IC_DMA_CR &= ~DW_IIC_DMA_CR_RDMAE;
  460. }
  461. static inline void dw_iic_dma_transmit_level(dw_iic_regs_t *iic_base, uint8_t level)
  462. {
  463. iic_base->IC_DMA_TDLR = ((uint32_t)level & DW_IIC_DMA_TDLR_Msk);
  464. }
  465. static inline void dw_iic_dma_receive_level(dw_iic_regs_t *iic_base, uint8_t level)
  466. {
  467. iic_base->IC_DMA_RDLR = ((uint32_t)level & DW_IIC_DMA_RDLR_Msk);
  468. }
  469. static inline uint32_t dw_iic_get_raw_interrupt_state(dw_iic_regs_t *iic_base)
  470. {
  471. return iic_base->IC_RAW_INTR_STAT;
  472. }
  473. static inline void dw_iic_disable_all_irq(dw_iic_regs_t *iic_base)
  474. {
  475. iic_base->IC_INTR_MASK = 0U;
  476. }
  477. static inline uint32_t dw_iic_read_clear_intrbits(dw_iic_regs_t *iic_base)
  478. {
  479. uint32_t stat = 0U;
  480. stat = iic_base->IC_INTR_STAT;
  481. if (stat & DW_IIC_INTR_RX_UNDER) {
  482. iic_base->IC_CLR_RX_UNDER;
  483. }
  484. if (stat & DW_IIC_INTR_RX_OVER) {
  485. iic_base->IC_CLR_RX_OVER;
  486. }
  487. if (stat & DW_IIC_INTR_TX_OVER) {
  488. iic_base->IC_CLR_TX_OVER;
  489. }
  490. if (stat & DW_IIC_INTR_RD_REQ) {
  491. iic_base->IC_CLR_RD_REQ;
  492. }
  493. if (stat & DW_IIC_INTR_TX_ABRT) {
  494. iic_base->IC_TX_ABRT_SOURCE;
  495. }
  496. if (stat & DW_IIC_INTR_RX_DONE) {
  497. iic_base->IC_CLR_RX_DONE;
  498. }
  499. if (stat & DW_IIC_INTR_ACTIVITY) {
  500. iic_base->IC_CLR_ACTIVITY;
  501. }
  502. if (stat & DW_IIC_INTR_STOP_DET) {
  503. iic_base->IC_CLR_STOP_DET;
  504. }
  505. if (stat & DW_IIC_INTR_START_DET) {
  506. iic_base->IC_CLR_START_DET;
  507. }
  508. if (stat & DW_IIC_INTR_GEN_CALL) {
  509. iic_base->IC_CLR_GEN_CALL;
  510. }
  511. return stat;
  512. }
  513. static inline uint32_t dw_iic_get_intrrupt_state(dw_iic_regs_t *iic_base)
  514. {
  515. return iic_base->IC_INTR_STAT;
  516. }
  517. extern void dw_iic_set_target_address(dw_iic_regs_t *iic_base, uint32_t address);
  518. extern void dw_iic_set_transfer_speed_high(dw_iic_regs_t *iic_base);
  519. extern void dw_iic_set_transfer_speed_fast(dw_iic_regs_t *iic_base);
  520. extern void dw_iic_set_transfer_speed_standard(dw_iic_regs_t *iic_base);
  521. extern void dw_iic_set_master_mode(dw_iic_regs_t *iic_base);
  522. extern void dw_iic_set_slave_mode(dw_iic_regs_t *iic_base);
  523. extern uint32_t dw_iic_find_max_prime_num(uint32_t num);
  524. extern int dw_iic_wait_bus_idle(dw_iic_regs_t *iic_base, uint32_t timeout);
  525. #ifdef __cplusplus
  526. }
  527. #endif
  528. #endif /* _DW_IIC_LL_H_ */