ddr_regu.c 30 KB

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  1. /*
  2. * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/types.h>
  9. #include <linux/bitops.h>
  10. #include <linux/delay.h>
  11. #include "dw_iic_ll.h"
  12. #include "iic.h"
  13. #include "ddr_regu.h"
  14. #define IOPMP_EMMC 0
  15. #define IOPMP_SDIO0 1
  16. #define IOPMP_SDIO1 2
  17. #define IOPMP_USB0 3
  18. #define IOPMP_AO 4
  19. #define IOPMP_AUD 5
  20. #define IOPMP_CHIP_DBG 6
  21. #define IOPMP_EIP120I 7
  22. #define IOPMP_EIP120II 8
  23. #define IOPMP_EIP120III 9
  24. #define IOPMP_ISP0 10
  25. #define IOPMP_ISP1 11
  26. #define IOPMP_DW200 12
  27. #define IOPMP_VIPRE 13
  28. #define IOPMP_VENC 14
  29. #define IOPMP_VDEC 15
  30. #define IOPMP_G2D 16
  31. #define IOPMP_FCE 17
  32. #define IOPMP_NPU 18
  33. #define IOPMP0_DPU 19
  34. #define IOPMP1_DPU 20
  35. #define IOPMP_GPU 21
  36. #define IOPMP_GMAC1 22
  37. #define IOPMP_GMAC2 23
  38. #define IOPMP_DMAC 24
  39. #define IOPMP_TEE_DMAC 25
  40. #define IOPMP_DSP0 26
  41. #define IOPMP_DSP1 27
  42. #define IIC_IDX_AONIIC 0
  43. #define IIC_IDX_APIIC 1
  44. #define DDR_VDD_REGU_0V6 0
  45. #define DDR_VDD_REGU_0V8 1
  46. #define DDR_VDD_REGU_1V1 2
  47. #define LCD0_EN 3
  48. #define APCPU_REGU_VDD 0
  49. #define APCPU_REGU_VDD1 1
  50. #define APCPU_REGU_VDDM 2
  51. struct regulator_t {
  52. uint8_t iic_id; ///< iic ctrl id
  53. uint8_t regu_id; ///< regulator id
  54. uint8_t dev_addr; ///< pmic-dev addr
  55. uint8_t reg_alen; ///< lenght of addr, range in [1..2] uint in bytes
  56. uint16_t reg_addr; ///< reg_addr offset within pmic-dev
  57. uint16_t reg_addr1; ///< reg_addr1 offset within pmic-dev
  58. uint8_t b_iic_read_sr; ///< Sr timing between write and read
  59. uint8_t rev[3]; ///< reverse
  60. uint32_t regu_vol_target; ///< target uv
  61. uint32_t regu_vol_min; ///< min uv
  62. uint32_t regu_vol_max; ///< max uv
  63. uint32_t regu_vol_step; ///< step uv
  64. };
  65. #define REGU_ID_DEF(ctrl_id, regu_idx, devaddr, regaddr,regaddr1, addrlen, vol_target, vol_min, vol_max, vol_step, iic_read_Sr) \
  66. .iic_id=ctrl_id, \
  67. .regu_id=regu_idx, \
  68. .dev_addr=devaddr, \
  69. .reg_alen = addrlen, \
  70. .reg_addr = regaddr, \
  71. .reg_addr1 = regaddr1, \
  72. .regu_vol_target=vol_target, \
  73. .regu_vol_max=vol_max, \
  74. .regu_vol_min=vol_min, \
  75. .regu_vol_step=vol_step, \
  76. .b_iic_read_sr = iic_read_Sr
  77. #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A)
  78. /**
  79. * board for EB068A10/EB065A10
  80. *
  81. */
  82. static const struct regulator_t g_regu_id_list[] = {
  83. {
  84. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_0V6,0x32,0x36,0,1,CONFIG_DDR_REGU_0V6,600000,3500000,12500,1),
  85. },
  86. {
  87. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_0V8,0x31,0x36,0,1,CONFIG_DDR_REGU_0V8,600000,3500000,12500,1),
  88. },
  89. {
  90. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_1V1,0x32,0x37,0,1,CONFIG_DDR_REGU_1V1,600000,3500000,12500,1),
  91. },
  92. };
  93. static const struct regulator_t g_apcpu_regu_id_list[] = {
  94. {
  95. REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDD,0x31,0x38,0,1,800000,600000,3500000,12500,1),
  96. },
  97. {
  98. REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
  99. },
  100. };
  101. #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
  102. /**
  103. * board for EB068A10/EB065A10
  104. *
  105. */
  106. static const struct regulator_t g_regu_id_list[] = {
  107. {
  108. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_0V6,0x32,0x36,0,1,CONFIG_DDR_REGU_0V6,600000,3500000,12500,1),
  109. },
  110. {
  111. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_0V8,0x31,0x36,0,1,CONFIG_DDR_REGU_0V8,600000,3500000,12500,1),
  112. },
  113. {
  114. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_1V1,0x32,0x37,0,1,CONFIG_DDR_REGU_1V1,600000,3500000,12500,1),
  115. },
  116. /*lcd0-en*/
  117. {
  118. REGU_ID_DEF(IIC_IDX_AONIIC,LCD0_EN,0x31,0x50,0,1,1800000,900000,3500000,25000,1),
  119. }
  120. };
  121. static const struct regulator_t g_apcpu_regu_id_list[] = {
  122. {
  123. REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDD,0x31,0x38,0,1,800000,600000,3500000,12500,1),
  124. },
  125. {
  126. REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
  127. },
  128. };
  129. #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
  130. /**
  131. * board for ant-ref
  132. *
  133. */
  134. static const struct regulator_t g_regu_id_list[] = {
  135. {
  136. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_0V6,0x5A,0xA5,0,1,CONFIG_DDR_REGU_0V6,530000,1200000,10000,0),
  137. },
  138. {
  139. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_0V8,0x5A,0xA8,0,1,CONFIG_DDR_REGU_0V8,800000,1200000,20000,0),
  140. },
  141. {
  142. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_1V1,0x5A,0xA6,0,1,CONFIG_DDR_REGU_1V1,800000,1500000,20000,0),
  143. },
  144. };
  145. static const struct regulator_t g_apcpu_regu_id_list[] = {
  146. {
  147. REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDD,0x5A,0xA4,0xB5,1,800000,300000,1500000,10000,0),
  148. },
  149. {
  150. REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDD1,0x5A,0xA3,0xB4,1,800000,300000,1500000,10000,0),
  151. },
  152. {
  153. REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x5A,0xA7,0xB8,1,800000,800000,1500000,20000,0),
  154. }
  155. };
  156. #else
  157. /**
  158. * board for EB064A10/EB064A11
  159. *
  160. */
  161. static const struct regulator_t g_regu_id_list[] = {
  162. {
  163. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_0V6,0x5A,0xA5,0,1,CONFIG_DDR_REGU_0V6,530000,1200000,10000,0),
  164. },
  165. {
  166. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_0V8,0x5A,0xA8,0,1,CONFIG_DDR_REGU_0V8,800000,1200000,20000,0),
  167. },
  168. {
  169. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_1V1,0x5A,0xA6,0,1,CONFIG_DDR_REGU_1V1,800000,1500000,20000,0),
  170. },
  171. {
  172. REGU_ID_DEF(IIC_IDX_AONIIC,DDR_VDD_REGU_1V1,0x5A,0xA7,0,1,CONFIG_DDR_REGU_1V1,800000,1500000,20000,0),
  173. }
  174. };
  175. static const struct regulator_t g_apcpu_regu_id_list[] = {
  176. {
  177. REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDD,0x5A,0xA4,0xB5,1,800000,300000,1500000,10000,0),
  178. },
  179. {
  180. REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x5A,0xA3,0xB4,1,800000,300000,1500000,10000,0),
  181. },
  182. };
  183. #endif
  184. #define HANDLE_REG_BASE(handle) (handle->dev.reg_base)
  185. static int wait_iic_transmit(dw_iic_regs_t *iic_base, uint32_t timeout)
  186. {
  187. int ret = 0;
  188. do {
  189. uint32_t timecount = 0;
  190. while ((dw_iic_get_transmit_fifo_num(iic_base) != 0U) && (ret == 0)) {
  191. udelay(1000);
  192. timecount++;
  193. if (timecount >= timeout) {
  194. ret = -3;
  195. }
  196. }
  197. } while (0);
  198. return ret;
  199. }
  200. static int wait_iic_receive(dw_iic_regs_t *iic_base, uint32_t wait_data_num, uint32_t timeout)
  201. {
  202. int ret = 0;
  203. do {
  204. uint32_t timecount = 0;
  205. while ((dw_iic_get_receive_fifo_num(iic_base) < wait_data_num) && (ret == 0)) {
  206. udelay(1000);
  207. timecount++;
  208. if (timecount >= timeout) {
  209. ret = -3;
  210. }
  211. }
  212. } while (0);
  213. return ret;
  214. }
  215. unsigned long soc_get_iic_freq(uint32_t idx)
  216. {
  217. if (idx == IIC_IDX_AONIIC){
  218. return 49152000U;
  219. }else if (idx == IIC_IDX_APIIC ){
  220. return 50000000U ;
  221. }else
  222. return 0U;
  223. }
  224. int target_get(uint32_t idx, csi_dev_t *dev)
  225. {
  226. if(dev == NULL)
  227. return -1;
  228. switch(idx)
  229. {
  230. case IIC_IDX_AONIIC:
  231. dev->idx= idx;
  232. dev->reg_base = 0xfffff4c000;
  233. dev->irq_num = 79;
  234. break;
  235. case IIC_IDX_APIIC:
  236. dev->idx= idx;
  237. dev->reg_base = 0xffe7f20000;
  238. dev->irq_num = 44 ;
  239. break;
  240. default:
  241. return -1;
  242. };
  243. return 0;
  244. }
  245. static csi_iic_t g_iic_aoniic,g_iic_apiic;
  246. csi_iic_t* pmic_get_iic_handle(uint32_t regu_id)
  247. {
  248. switch(regu_id){
  249. case IIC_IDX_AONIIC:
  250. return (csi_iic_t*)&g_iic_aoniic;
  251. break;
  252. case IIC_IDX_APIIC:
  253. return (csi_iic_t*)&g_iic_apiic;
  254. break;
  255. default:
  256. return NULL;
  257. }
  258. return NULL;
  259. }
  260. int csi_iic_init(csi_iic_t *iic, uint32_t idx)
  261. {
  262. int ret = 0;
  263. dw_iic_regs_t *iic_base;
  264. ret = target_get(idx, &iic->dev);
  265. if (ret == 0) {
  266. iic_base = (dw_iic_regs_t *)HANDLE_REG_BASE(iic);
  267. iic_base->IC_SAR = 0;
  268. dw_iic_disable(iic_base);
  269. dw_iic_clear_all_irq(iic_base);
  270. dw_iic_disable_all_irq(iic_base);
  271. iic_base->IC_FIFO_RST_EN = 0;
  272. }
  273. iic->state.writeable = 1U;
  274. iic->state.readable = 1U;
  275. iic->state.error = 0U;
  276. iic->send = NULL;
  277. iic->receive = NULL;
  278. iic->callback = NULL;
  279. return ret;
  280. }
  281. int csi_iic_mode(csi_iic_t *iic, csi_iic_mode_t mode)
  282. {
  283. dw_iic_regs_t *iic_base;
  284. int ret = -1;
  285. iic_base = (dw_iic_regs_t *)HANDLE_REG_BASE(iic);
  286. dw_iic_disable(iic_base);
  287. /* This register can be written only when the I2C is disabled */
  288. if (mode == IIC_MODE_MASTER) {
  289. iic->mode = IIC_MODE_MASTER;
  290. dw_iic_set_master_mode(iic_base);
  291. dw_iic_enable_restart(iic_base);
  292. ret = 0;
  293. } else if (mode == IIC_MODE_SLAVE) {
  294. iic->mode = IIC_MODE_SLAVE;
  295. dw_iic_set_slave_mode(iic_base);
  296. dw_iic_enable_restart(iic_base);
  297. ret = 0;
  298. }
  299. return ret;
  300. }
  301. int csi_iic_addr_mode(csi_iic_t *iic, csi_iic_addr_mode_t addr_mode)
  302. {
  303. dw_iic_regs_t *iic_base;
  304. int ret = -1;
  305. iic_base = (dw_iic_regs_t *)HANDLE_REG_BASE(iic);
  306. dw_iic_disable(iic_base);
  307. /* This register can be written only when the I2C is disabled */
  308. if (addr_mode == IIC_ADDRESS_7BIT) {
  309. dw_iic_set_master_7bit_addr_mode(iic_base);
  310. dw_iic_set_slave_7bit_addr_mode(iic_base);
  311. ret = 0;
  312. } else if (addr_mode == IIC_ADDRESS_10BIT) {
  313. dw_iic_set_master_10bit_addr_mode(iic_base);
  314. dw_iic_set_slave_10bit_addr_mode(iic_base);
  315. ret = 0;
  316. }
  317. return ret;
  318. }
  319. int csi_iic_speed(csi_iic_t *iic, csi_iic_speed_t speed)
  320. {
  321. dw_iic_regs_t *iic_base;
  322. int ret = -1;
  323. iic_base = (dw_iic_regs_t *)HANDLE_REG_BASE(iic);
  324. uint32_t ic_clk;
  325. dw_iic_disable(iic_base);
  326. /* This register can be written only when the I2C is disabled */
  327. if (speed == IIC_BUS_SPEED_STANDARD) {
  328. dw_iic_set_transfer_speed_standard(iic_base);
  329. ic_clk = soc_get_iic_freq((uint32_t)iic->dev.idx) / 1000000U;
  330. dw_iic_set_standard_scl_hcnt(iic_base, ((5U * ic_clk) - 8U));
  331. dw_iic_set_standard_scl_lcnt(iic_base, ((5U * ic_clk) - 1U));
  332. ret = 0;
  333. } else if (speed == IIC_BUS_SPEED_FAST) {
  334. dw_iic_set_transfer_speed_fast(iic_base);
  335. ic_clk = soc_get_iic_freq((uint32_t)iic->dev.idx) / 1000000U;
  336. dw_iic_set_fast_scl_hcnt(iic_base, (((125U * ic_clk) / 100U) - 8U));
  337. dw_iic_set_fast_scl_lcnt(iic_base, (((125U * ic_clk) / 100U) - 1U));
  338. ret = 0;
  339. } else if (speed == IIC_BUS_SPEED_FAST_PLUS) {
  340. ret = -4;
  341. } else if (speed == IIC_BUS_SPEED_HIGH) {
  342. dw_iic_set_transfer_speed_high(iic_base);
  343. ic_clk = soc_get_iic_freq((uint32_t)iic->dev.idx) / 10000000U;
  344. dw_iic_set_high_scl_hcnt(iic_base, (((147U * ic_clk) / 100U) - 8U));
  345. dw_iic_set_high_scl_lcnt(iic_base, (((147U * ic_clk) / 100U) - 1U));
  346. ret = 0;
  347. }
  348. return ret;
  349. }
  350. int32_t csi_iic_master_send(csi_iic_t *iic, uint32_t devaddr, const void *data, uint32_t size, uint32_t timeout)
  351. {
  352. int ret = 0;
  353. int32_t send_count = 0;
  354. uint32_t stop_time = 0U;
  355. uint8_t *send_data = (void *)data;
  356. uint32_t timecount = 0;
  357. if ((send_data == NULL) || (size == 0U)) {
  358. send_count = (int32_t)-1;
  359. } else {
  360. dw_iic_regs_t *iic_base;
  361. iic_base = (dw_iic_regs_t *)HANDLE_REG_BASE(iic);
  362. ret = dw_iic_wait_bus_idle(iic_base, timeout);
  363. if(ret)
  364. return ret;
  365. dw_iic_disable(iic_base);
  366. dw_iic_set_target_address(iic_base, devaddr);
  367. dw_iic_enable(iic_base);
  368. while (1) {
  369. if (size < IIC_MAX_FIFO) {
  370. for (uint8_t i = 0U; i < size; i++) {
  371. dw_iic_transmit_data(iic_base, *(send_data++));
  372. }
  373. ret = wait_iic_transmit(iic_base, timeout); ///< wait data send
  374. if (ret != 0) {
  375. send_count = (int32_t)ret;
  376. break;
  377. }
  378. send_count += (int32_t)size;
  379. } else {
  380. while (send_count < size) {
  381. uint8_t send_num = IIC_MAX_FIFO - dw_iic_get_transmit_fifo_num(iic_base);
  382. for (uint8_t i = 0U; i < send_num; i++) {
  383. dw_iic_transmit_data(iic_base, *(send_data++));
  384. }
  385. send_count += send_num;
  386. if (timeout >= timecount) {
  387. ret = -7;
  388. break;
  389. }
  390. }
  391. if (ret != 0) {
  392. break;
  393. }
  394. }
  395. if ((send_count == (int32_t)size) && (ret == 0)) {
  396. stop_time = 0;
  397. while (!(dw_iic_get_raw_interrupt_state(iic_base) & DW_IIC_RAW_STOP_DET)) {
  398. udelay(1000);
  399. stop_time++;
  400. if (stop_time > timeout) {
  401. ret = -3;
  402. break;
  403. }
  404. }
  405. break;
  406. }
  407. }
  408. }
  409. return send_count;
  410. }
  411. int32_t csi_iic_master_receive(csi_iic_t *iic, uint32_t devaddr, void *data, uint32_t size, uint32_t timeout)
  412. {
  413. int ret = 0;
  414. int32_t read_count = 0;
  415. uint8_t *receive_data = (void *)data;
  416. if ((receive_data == NULL) || (size == 0U)) {
  417. read_count = (int32_t)-1;
  418. } else {
  419. dw_iic_regs_t *iic_base;
  420. uint32_t cmd_num;
  421. iic_base = (dw_iic_regs_t *)HANDLE_REG_BASE(iic);
  422. ret = dw_iic_wait_bus_idle(iic_base, timeout);
  423. if(ret)
  424. return ret;
  425. dw_iic_disable(iic_base);
  426. dw_iic_set_target_address(iic_base, devaddr);
  427. dw_iic_enable(iic_base);
  428. if (size < IIC_MAX_FIFO) {
  429. for (read_count = 0; read_count < (int32_t)size; read_count++) {
  430. dw_iic_data_cmd(iic_base);
  431. }
  432. ret = wait_iic_receive(iic_base, size, timeout);
  433. if (ret == 0) {
  434. for (read_count = 0; read_count < (int32_t)size; read_count++) {
  435. *(receive_data++) = dw_iic_receive_data(iic_base);
  436. }
  437. } else {
  438. read_count = (int32_t)ret;
  439. }
  440. } else {
  441. read_count = 0;
  442. for (cmd_num = size; cmd_num > (size - IIC_MAX_FIFO); cmd_num--) {
  443. dw_iic_data_cmd(iic_base);
  444. }
  445. while (read_count < size) {
  446. ret = wait_iic_receive(iic_base, 1U, timeout);
  447. if (ret != 0) {
  448. read_count = (int32_t)ret;
  449. break;
  450. }
  451. *(receive_data++) = dw_iic_receive_data(iic_base);
  452. read_count ++;
  453. if (cmd_num > 0U) {
  454. dw_iic_data_cmd(iic_base);
  455. cmd_num --;
  456. }
  457. }
  458. uint32_t timecount = 0;
  459. while (!(dw_iic_get_raw_interrupt_state(iic_base) & DW_IIC_RAW_STOP_DET)) {
  460. udelay(1000);
  461. timecount++;
  462. if (timecount >= timeout) {
  463. ret = -3;
  464. break;
  465. }
  466. }
  467. }
  468. }
  469. return read_count;
  470. }
  471. int32_t csi_iic_mem_receive_sr(csi_iic_t *iic, uint32_t devaddr, uint16_t memaddr, csi_iic_mem_addr_size_t memaddr_size, void *data, uint32_t size, uint32_t timeout)
  472. {
  473. int ret = 0;
  474. int32_t read_count = 0;
  475. uint32_t stop_time = 0U;
  476. uint8_t *receive_data = (void *)data;
  477. uint8_t mem_addr_flag = 1U;
  478. if ((receive_data == NULL) || (size == 0U)) {
  479. read_count = (int32_t)-1;
  480. } else {
  481. dw_iic_regs_t *iic_base;
  482. iic_base = (dw_iic_regs_t *)HANDLE_REG_BASE(iic);
  483. ret = dw_iic_wait_bus_idle(iic_base, timeout);
  484. if(ret)
  485. return ret;
  486. dw_iic_disable(iic_base);
  487. dw_iic_set_target_address(iic_base, devaddr);
  488. dw_iic_enable(iic_base);
  489. if (memaddr_size == IIC_MEM_ADDR_SIZE_8BIT) {
  490. dw_iic_transmit_data(iic_base, (uint8_t)memaddr);
  491. }
  492. if (memaddr_size == IIC_MEM_ADDR_SIZE_16BIT) {
  493. dw_iic_transmit_data(iic_base, (uint8_t)(memaddr >> 8));
  494. dw_iic_transmit_data(iic_base, (uint8_t)memaddr);
  495. }
  496. uint32_t cmd_num;
  497. if (mem_addr_flag == 1U) {
  498. if (size < IIC_MAX_FIFO) {
  499. for (read_count = 0; read_count < (int32_t)size; read_count++) {
  500. if(read_count == 0 )
  501. dw_iic_data_sr_cmd(iic_base);
  502. else
  503. dw_iic_data_cmd(iic_base);
  504. }
  505. ret = wait_iic_receive(iic_base, size, timeout);
  506. if (ret == 0) {
  507. for (read_count = 0; read_count < (int32_t)size; read_count++) {
  508. *(receive_data++) = dw_iic_receive_data(iic_base);
  509. }
  510. } else {
  511. read_count = (int32_t)ret;
  512. }
  513. } else {
  514. read_count = 0;
  515. for (cmd_num = size; cmd_num > (size - IIC_MAX_FIFO); cmd_num--) {
  516. if(cmd_num == size )
  517. dw_iic_data_sr_cmd(iic_base);
  518. else
  519. dw_iic_data_cmd(iic_base);
  520. }
  521. while (mem_addr_flag) {
  522. ret = wait_iic_receive(iic_base, 1U, timeout);
  523. if (ret != 0) {
  524. read_count = (int32_t)ret;
  525. break;
  526. }
  527. *(receive_data++) = dw_iic_receive_data(iic_base);
  528. read_count ++;
  529. if (read_count == (int32_t)size) {
  530. while (!(dw_iic_get_raw_interrupt_state(iic_base) & DW_IIC_RAW_STOP_DET)) {
  531. stop_time ++;
  532. if (stop_time > DW_IIC_TIMEOUT_DEF_VAL) {
  533. ret = -3;
  534. break;
  535. }
  536. }
  537. break;
  538. }
  539. if (cmd_num > 0U) {
  540. dw_iic_data_cmd(iic_base);
  541. cmd_num --;
  542. }
  543. }
  544. }
  545. } else {
  546. read_count = (int32_t)-1;
  547. }
  548. }
  549. return read_count;
  550. }
  551. static int pmic_read_reg_sr(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
  552. {
  553. int32_t num;
  554. uint8_t temp[2] = {0};
  555. num = csi_iic_mem_receive_sr(iic_handle,dev_addr,offset,(offset>>8)?IIC_MEM_ADDR_SIZE_16BIT:IIC_MEM_ADDR_SIZE_8BIT,&temp,1,10);
  556. if(num != 1) {
  557. return -1;
  558. }
  559. *val = temp[0];
  560. return 0;
  561. }
  562. static int pmic_write_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t val)
  563. {
  564. int32_t num;
  565. uint8_t temp[6] = {0};
  566. uint32_t len = 0;
  567. if((offset >> 8) & 0xff ){
  568. /*16 bit addr*/
  569. temp[len++] = (offset >> 8) & 0xff;
  570. temp[len++] = offset & 0xff;
  571. temp[len++]= (uint8_t)val;
  572. }else{
  573. /*8bit addr*/
  574. temp[len++] = offset & 0xff;
  575. temp[len++] = (uint8_t)val;
  576. }
  577. num = csi_iic_master_send(iic_handle,dev_addr,temp,len,10);
  578. if(num != len) {
  579. return -1;
  580. }
  581. return 0;
  582. }
  583. static int pmic_read_reg(csi_iic_t *iic_handle,uint16_t dev_addr,uint32_t offset, uint32_t *val)
  584. {
  585. int32_t num;
  586. uint8_t temp[2] = {0};
  587. uint32_t len = 0;
  588. if ((offset >> 8) & 0xff)
  589. {
  590. temp[len++] = (offset >> 8) & 0xff;
  591. temp[len++] = offset & 0xff;
  592. }
  593. else
  594. {
  595. temp[len++] = offset & 0xff;
  596. }
  597. num = csi_iic_master_send(iic_handle,dev_addr,&temp,len,10);
  598. if(num != len) {
  599. return -1;
  600. }
  601. num = csi_iic_master_receive(iic_handle,dev_addr,&temp[0],1,10);
  602. if(num != 1) {
  603. return -1;
  604. }
  605. *val = temp[0];
  606. return 0;
  607. }
  608. static int _pmic_ddr_regu_init(uint32_t idx)
  609. {
  610. int ret;
  611. csi_iic_t *handle = pmic_get_iic_handle(idx);
  612. if ( handle == NULL)
  613. return -1;
  614. ret = csi_iic_init(handle,idx);
  615. if (ret)
  616. return ret;
  617. ret = csi_iic_mode(handle, IIC_MODE_MASTER);
  618. if( ret )
  619. return ret;
  620. ret = csi_iic_addr_mode(handle,IIC_ADDRESS_7BIT);
  621. if( ret )
  622. return ret;
  623. ret = csi_iic_speed(handle,IIC_BUS_SPEED_FAST);
  624. if(ret)
  625. return ret;
  626. return ret;
  627. }
  628. static const struct light_iopmp_list {
  629. int iopmp_type;
  630. u64 reg;
  631. } light_iopmp_lists[] = {
  632. {IOPMP_EMMC, 0xFFFC028000},
  633. {IOPMP_SDIO0, 0xFFFC029000},
  634. {IOPMP_SDIO1, 0xFFFC02A000},
  635. {IOPMP_USB0, 0xFFFC02E000},
  636. {IOPMP_AO, 0xFFFFC21000},
  637. {IOPMP_AUD, 0xFFFFC22000},
  638. {IOPMP_CHIP_DBG, 0xFFFFC37000},
  639. {IOPMP_EIP120I, 0xFFFF220000},
  640. {IOPMP_EIP120II, 0xFFFF230000},
  641. {IOPMP_EIP120III, 0xFFFF240000},
  642. {IOPMP_ISP0, 0xFFF4080000},
  643. {IOPMP_ISP1, 0xFFF4081000},
  644. {IOPMP_DW200, 0xFFF4082000},
  645. {IOPMP_VIPRE, 0xFFF4083000},
  646. {IOPMP_VENC, 0xFFFCC60000},
  647. {IOPMP_VDEC, 0xFFFCC61000},
  648. {IOPMP_G2D, 0xFFFCC62000},
  649. {IOPMP_FCE, 0xFFFCC63000},
  650. {IOPMP_NPU, 0xFFFF01C000},
  651. {IOPMP0_DPU, 0xFFFF520000},
  652. {IOPMP1_DPU, 0xFFFF521000},
  653. {IOPMP_GPU, 0xFFFF522000},
  654. {IOPMP_GMAC1, 0xFFFC001000},
  655. {IOPMP_GMAC2, 0xFFFC002000},
  656. {IOPMP_DMAC, 0xFFFFC20000},
  657. {IOPMP_TEE_DMAC, 0xFFFF250000},
  658. {IOPMP_DSP0, 0xFFFF058000},
  659. {IOPMP_DSP1, 0xFFFF059000},
  660. };
  661. static void light_iopmp_config(void)
  662. {
  663. int i = 0;
  664. int entry_size;
  665. entry_size = ARRAY_SIZE(light_iopmp_lists);
  666. while (i < entry_size) {
  667. writel(0xffffffff, (void *)(light_iopmp_lists[i].reg) + 0xc0);
  668. i++;
  669. }
  670. }
  671. int pmic_ddr_regu_init(void)
  672. {
  673. #define AON_PADMUX_BASE (0xfffff4a000)
  674. int ret;
  675. uint32_t val;
  676. /*init iopmp */
  677. light_iopmp_config();
  678. /*init aon-iic pad*/
  679. val = readl((void *)(AON_PADMUX_BASE + 0x10));
  680. val &=~0xffff0000;
  681. val |=0x208<<16;
  682. writel( val, (void *)(AON_PADMUX_BASE + 0x10));
  683. val = readl((void *)(AON_PADMUX_BASE + 0x14));
  684. val &=~0xffff;
  685. val |=0x208;
  686. writel( val, (void *)(AON_PADMUX_BASE + 0x14));
  687. /*init iic device*/
  688. ret = _pmic_ddr_regu_init(IIC_IDX_AONIIC);
  689. if(ret)
  690. return ret;
  691. ret = _pmic_ddr_regu_init(IIC_IDX_APIIC);
  692. if(ret)
  693. return ret;
  694. return ret;
  695. }
  696. int pmic_ddr_set_voltage(void)
  697. {
  698. int ret = 0;
  699. uint32_t val = 0;
  700. uint32_t regu_num = ARRAY_SIZE(g_regu_id_list);
  701. uint32_t i;
  702. struct regulator_t *pregu;
  703. csi_iic_t *dev_handle;
  704. #if 0 //currently,no need to modify ddr regulator voltage
  705. pregu = (struct regulator_t*)g_regu_id_list;
  706. for (i = 0; i < regu_num; i++, pregu++) {
  707. if (pregu->regu_vol_target < pregu->regu_vol_min || pregu->regu_vol_target > pregu->regu_vol_max)
  708. continue;
  709. val = (pregu->regu_vol_target - pregu->regu_vol_min)/pregu->regu_vol_step;
  710. dev_handle = pmic_get_iic_handle(pregu->iic_id);
  711. ret = pmic_write_reg(dev_handle,pregu->dev_addr, pregu->reg_addr,val);
  712. if (ret)
  713. return ret;
  714. }
  715. #endif
  716. #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
  717. /*enable lcd0_en ldo*/
  718. pregu = (struct regulator_t*)&g_regu_id_list[LCD0_EN];
  719. dev_handle = pmic_get_iic_handle(pregu->iic_id);
  720. ret = pmic_read_reg_sr(dev_handle,pregu->dev_addr,0x44,&val);
  721. if(ret)
  722. return ret;
  723. val |=(1<<4);
  724. ret = pmic_write_reg(dev_handle,pregu->dev_addr,0x44,val);
  725. #endif
  726. return ret;
  727. }
  728. struct regulator_t* pmic_get_regu_by_reguid(const struct regulator_t *regu_dsc_list,uint32_t regu_dsc_list_size, uint32_t regu_id)
  729. {
  730. uint32_t i;
  731. struct regulator_t *pregu = NULL;
  732. if(regu_dsc_list == NULL)
  733. return NULL;
  734. for(i = 0; i < regu_dsc_list_size; i++) {
  735. if (regu_dsc_list[i].regu_id == regu_id) {
  736. pregu = (struct regulator_t*)&regu_dsc_list[i];
  737. break;
  738. }
  739. }
  740. return pregu;
  741. }
  742. #if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_A) ||defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
  743. int pmic_reset_apcpu_voltage(void)
  744. {
  745. csi_iic_t *dev_handle;
  746. struct regulator_t *regu_vdd,*regu_vddm;
  747. uint32_t cur_target1,cur_target2;
  748. uint32_t target_uv1,target_uv2,val;
  749. int ret;
  750. int32_t nstep1,nstep2;
  751. regu_vdd = pmic_get_regu_by_reguid(g_apcpu_regu_id_list, ARRAY_SIZE(g_apcpu_regu_id_list), APCPU_REGU_VDD);
  752. regu_vddm = pmic_get_regu_by_reguid(g_apcpu_regu_id_list, ARRAY_SIZE(g_apcpu_regu_id_list), APCPU_REGU_VDDM);
  753. dev_handle = pmic_get_iic_handle(regu_vdd->iic_id);
  754. if (!dev_handle || !regu_vdd || !regu_vddm)
  755. return -1;
  756. /*get cur_target uv*/
  757. ret = pmic_read_reg_sr(dev_handle,regu_vdd->dev_addr,regu_vdd->reg_addr,&cur_target1);
  758. if(ret)
  759. return ret;
  760. ret = pmic_read_reg_sr(dev_handle,regu_vddm->dev_addr,regu_vddm->reg_addr,&cur_target2);
  761. if(ret)
  762. return ret;
  763. target_uv1 = (regu_vdd->regu_vol_target-regu_vdd->regu_vol_min)/regu_vdd->regu_vol_step;
  764. target_uv2 = (regu_vddm->regu_vol_target-regu_vdd->regu_vol_min)/regu_vddm->regu_vol_step;
  765. /*calculate nsteps for each regu_id*/
  766. nstep1 = (target_uv1-cur_target1);
  767. nstep2 = (target_uv2-cur_target2);
  768. /*do adjusting voltage step by step */
  769. while(nstep1 || nstep2) {
  770. if(nstep1 > 0 ) {
  771. cur_target1 +=1;
  772. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,regu_vdd->reg_addr,cur_target1);
  773. if (ret )
  774. return ret;
  775. nstep1--;
  776. }else if (nstep1 < 0 ){
  777. cur_target1 -=1;
  778. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,regu_vdd->reg_addr,cur_target1);
  779. if (ret )
  780. return ret;
  781. nstep1++;
  782. }
  783. if(nstep2 > 0 ) {
  784. cur_target2 +=1;
  785. ret = pmic_write_reg(dev_handle,regu_vddm->dev_addr,regu_vddm->reg_addr,cur_target2);
  786. if (ret )
  787. return ret;
  788. nstep2--;
  789. }else if (nstep2 < 0 ){
  790. cur_target2 -=1;
  791. ret = pmic_write_reg(dev_handle,regu_vddm->dev_addr,regu_vddm->reg_addr,cur_target2);
  792. if (ret )
  793. return ret;
  794. nstep2++;
  795. }
  796. }
  797. mdelay(2);
  798. /*disable watchdog*/
  799. ret = pmic_read_reg_sr(dev_handle,0x31,0x0B,&val);
  800. if (ret)
  801. return ret;
  802. val &=~(1<<2);
  803. ret = pmic_write_reg(dev_handle,0x31,0x0B,val);
  804. if (ret)
  805. return ret;
  806. return 0;
  807. }
  808. #elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
  809. int pmic_reset_apcpu_voltage(void)
  810. {
  811. int ret = -1;
  812. csi_iic_t *dev_handle;
  813. struct regulator_t *regu_vdd,*regu_vdd1,*regu_vddm;
  814. uint32_t val,dvc,dvc1;
  815. regu_vdd = pmic_get_regu_by_reguid(g_apcpu_regu_id_list, ARRAY_SIZE(g_apcpu_regu_id_list), APCPU_REGU_VDD);
  816. regu_vdd1 = pmic_get_regu_by_reguid(g_apcpu_regu_id_list, ARRAY_SIZE(g_apcpu_regu_id_list), APCPU_REGU_VDD1);
  817. regu_vddm = pmic_get_regu_by_reguid(g_apcpu_regu_id_list, ARRAY_SIZE(g_apcpu_regu_id_list), APCPU_REGU_VDDM);
  818. dev_handle = pmic_get_iic_handle(regu_vdd->iic_id);
  819. if (!dev_handle || !regu_vdd || !regu_vdd1 || !regu_vddm)
  820. return -1;
  821. /* get current regulator rail */
  822. ret = pmic_read_reg(dev_handle,regu_vdd->dev_addr,0x32,&dvc);
  823. if (ret)
  824. return ret;
  825. ret = pmic_read_reg(dev_handle,regu_vdd->dev_addr,0x33,&dvc1);
  826. if (ret)
  827. return ret;
  828. /*bcore1 and bcore2 should use the same rail(both rail-a or both rail-b */
  829. if (!((dvc & 0x3) == 0 || (dvc & 0x3) == 3) )
  830. return -1;
  831. /* cur-rail is rail-a, then copy current voltage to rail-b*/
  832. if ( (dvc & 0x3) == 0 ) {
  833. ret = pmic_read_reg(dev_handle,regu_vdd->dev_addr,regu_vdd->reg_addr,&val);
  834. if (ret)
  835. return ret;
  836. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,regu_vdd->reg_addr1,val);
  837. if (ret)
  838. return ret;
  839. ret = pmic_read_reg(dev_handle,regu_vdd1->dev_addr,regu_vdd1->reg_addr,&val);
  840. if (ret)
  841. return ret;
  842. ret = pmic_write_reg(dev_handle,regu_vdd1->dev_addr,regu_vdd1->reg_addr1,val);
  843. if (ret)
  844. return ret;
  845. ret = pmic_read_reg(dev_handle,regu_vddm->dev_addr,regu_vddm->reg_addr,&val);
  846. if (ret)
  847. return ret;
  848. ret = pmic_write_reg(dev_handle,regu_vddm->dev_addr,regu_vddm->reg_addr1,val);
  849. if (ret)
  850. return ret;
  851. /*select rail-b*/
  852. dvc |=0x3;
  853. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,0x32,dvc);
  854. if (ret)
  855. return ret;
  856. dvc1 |=0x1;
  857. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,0x33,dvc1);
  858. if (ret)
  859. return ret;
  860. mdelay(1);
  861. }
  862. /*modify rail-a voltate, then select rail-a */
  863. val = (regu_vdd->regu_vol_target - regu_vdd->regu_vol_min)/regu_vdd->regu_vol_step;
  864. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,regu_vdd->reg_addr,val);
  865. if (ret)
  866. return ret;
  867. val = (regu_vdd1->regu_vol_target - regu_vdd1->regu_vol_min)/regu_vdd1->regu_vol_step;
  868. ret = pmic_write_reg(dev_handle,regu_vdd1->dev_addr,regu_vdd1->reg_addr,val);
  869. if (ret)
  870. return ret;
  871. val = (regu_vddm->regu_vol_target - regu_vddm->regu_vol_min)/regu_vddm->regu_vol_step;
  872. ret = pmic_write_reg(dev_handle,regu_vddm->dev_addr,regu_vddm->reg_addr,val);
  873. if (ret)
  874. return ret;
  875. /*select rail-a*/
  876. dvc &=~0x3;
  877. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,0x32,dvc);
  878. if (ret)
  879. return ret;
  880. dvc1 &=~0x1;
  881. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,0x33,dvc1);
  882. if (ret)
  883. return ret;
  884. mdelay(1);
  885. /*disable watchdog*/
  886. ret = pmic_read_reg(dev_handle,regu_vdd->dev_addr,0x11,&val);
  887. if (ret)
  888. return ret;
  889. val &=~0x7;
  890. pmic_write_reg(dev_handle,regu_vdd->dev_addr,0x11,val);
  891. return 0;
  892. }
  893. #else
  894. int pmic_reset_apcpu_voltage(void)
  895. {
  896. int ret = -1;
  897. csi_iic_t *dev_handle;
  898. struct regulator_t *regu_vdd,*regu_vddm;
  899. uint32_t val,dvc;
  900. regu_vdd = pmic_get_regu_by_reguid(g_apcpu_regu_id_list, ARRAY_SIZE(g_apcpu_regu_id_list), APCPU_REGU_VDD);
  901. regu_vddm = pmic_get_regu_by_reguid(g_apcpu_regu_id_list, ARRAY_SIZE(g_apcpu_regu_id_list), APCPU_REGU_VDDM);
  902. dev_handle = pmic_get_iic_handle(regu_vdd->iic_id);
  903. if (!dev_handle || !regu_vdd || !regu_vddm)
  904. return -1;
  905. /* get current regulator rail */
  906. ret = pmic_read_reg(dev_handle,regu_vdd->dev_addr,0x32,&dvc);
  907. if (ret)
  908. return ret;
  909. /*bcore1 and bcore2 should use the same rail(both rail-a or both rail-b */
  910. if (!((dvc & 0x3) == 0 || (dvc & 0x3) == 3) )
  911. return -1;
  912. /* cur-rail is rail-a, then copy current voltage to rail-b*/
  913. if ( (dvc & 0x3) == 0 ) {
  914. ret = pmic_read_reg(dev_handle,regu_vdd->dev_addr,regu_vdd->reg_addr,&val);
  915. if (ret)
  916. return ret;
  917. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,regu_vdd->reg_addr1,val);
  918. if (ret)
  919. return ret;
  920. ret = pmic_read_reg(dev_handle,regu_vddm->dev_addr,regu_vddm->reg_addr,&val);
  921. if (ret)
  922. return ret;
  923. ret = pmic_write_reg(dev_handle,regu_vddm->dev_addr,regu_vddm->reg_addr1,val);
  924. if (ret)
  925. return ret;
  926. /*select rail-b*/
  927. dvc |=0x3;
  928. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,0x32,dvc);
  929. if (ret)
  930. return ret;
  931. mdelay(1);
  932. }
  933. /*modify rail-a voltate, then select rail-a */
  934. val = (regu_vdd->regu_vol_target - regu_vdd->regu_vol_min)/regu_vdd->regu_vol_step;
  935. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,regu_vdd->reg_addr,val);
  936. if (ret)
  937. return ret;
  938. val = (regu_vddm->regu_vol_target - regu_vddm->regu_vol_min)/regu_vddm->regu_vol_step;
  939. ret = pmic_write_reg(dev_handle,regu_vddm->dev_addr,regu_vddm->reg_addr,val);
  940. if (ret)
  941. return ret;
  942. /*select rail-a*/
  943. dvc &=~0x3;
  944. ret = pmic_write_reg(dev_handle,regu_vdd->dev_addr,0x32,dvc);
  945. if (ret)
  946. return ret;
  947. mdelay(1);
  948. /*disable watchdog*/
  949. ret = pmic_read_reg(dev_handle,regu_vdd->dev_addr,0x11,&val);
  950. if (ret)
  951. return ret;
  952. val &=~0x7;
  953. pmic_write_reg(dev_handle,regu_vdd->dev_addr,0x11,val);
  954. return 0;
  955. }
  956. #endif