board.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <dwc3-uboot.h>
  9. #include <usb.h>
  10. #include <cpu_func.h>
  11. #ifdef CONFIG_USB_DWC3
  12. static struct dwc3_device dwc3_device_data = {
  13. .maximum_speed = USB_SPEED_HIGH,
  14. .dr_mode = USB_DR_MODE_PERIPHERAL,
  15. .index = 0,
  16. };
  17. int usb_gadget_handle_interrupts(int index)
  18. {
  19. dwc3_uboot_handle_interrupt(index);
  20. return 0;
  21. }
  22. int board_usb_init(int index, enum usb_init_type init)
  23. {
  24. dwc3_device_data.base = 0xFFE7040000UL;
  25. return dwc3_uboot_init(&dwc3_device_data);
  26. }
  27. int board_usb_cleanup(int index, enum usb_init_type init)
  28. {
  29. dwc3_uboot_exit(index);
  30. return 0;
  31. }
  32. int g_dnl_board_usb_cable_connected(void)
  33. {
  34. return 1;
  35. }
  36. #endif
  37. #ifdef CONFIG_CMD_BOOT_SLAVE
  38. #define E902_SYSREG_START 0xfffff48044
  39. #define E902_SYSREG_RESET 0xfffff44024
  40. #define E902_START_ADDRESS 0xFFEF8000
  41. #define C910_E902_START_ADDRESS 0xFFFFEF8000
  42. #define E902_IOPMP_BASE 0xFFFFC21000
  43. #define C906_RST_ADDR_L 0xfffff48048
  44. #define C906_RST_ADDR_H 0xfffff4804C
  45. #define C906_START_ADDRESS_L 0xc0000000
  46. #define C906_START_ADDRESS_H 0xff
  47. #define C910_C906_START_ADDRESS 0xffc0000000
  48. #define C906_CPR_IPCG_ADDRESS 0xFFCB000010
  49. #define C906_IOCTL_GPIO_SEL_ADDRESS 0xFFCB01D000
  50. #define C906_IOCTL_AF_SELH_ADDRESS 0xFFCB01D008
  51. #define C906_RESET_REG 0xfffff4403c
  52. void set_slave_cpu_entry(phys_addr_t entry)
  53. {
  54. writel(entry, (void *)E902_SYSREG_START);
  55. }
  56. void disable_slave_cpu(void)
  57. {
  58. writel(0x0, (void *)E902_SYSREG_RESET);
  59. }
  60. void enable_slave_cpu(void)
  61. {
  62. writel(0x3, (void *)E902_SYSREG_RESET);
  63. }
  64. void set_c906_cpu_entry(phys_addr_t entry_h, phys_addr_t entry_l)
  65. {
  66. writel(entry_h, (volatile void *)C906_RST_ADDR_H);
  67. writel(entry_l, (volatile void *)C906_RST_ADDR_L);
  68. }
  69. void boot_audio(void)
  70. {
  71. writel(0x37, (volatile void *)C906_RESET_REG);
  72. set_c906_cpu_entry(C906_START_ADDRESS_H, C906_START_ADDRESS_L);
  73. flush_cache((uintptr_t)C910_C906_START_ADDRESS, 0x20000);
  74. writel(0x7ffff1f, (volatile void *)C906_CPR_IPCG_ADDRESS);
  75. writel((1<<23) | (1<<24), (volatile void *)C906_IOCTL_GPIO_SEL_ADDRESS);
  76. writel(0, (volatile void *)C906_IOCTL_AF_SELH_ADDRESS);
  77. writel(0x3f, (volatile void *)C906_RESET_REG);
  78. }
  79. void boot_aon(void)
  80. {
  81. writel(0xffffffff, (void *)(E902_IOPMP_BASE + 0xc0));
  82. disable_slave_cpu();
  83. set_slave_cpu_entry(E902_START_ADDRESS);
  84. flush_cache((uintptr_t)C910_E902_START_ADDRESS, 0x10000);
  85. enable_slave_cpu();
  86. }
  87. int do_bootslave(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
  88. {
  89. boot_aon();
  90. mdelay(100);
  91. boot_audio();
  92. return 0;
  93. }
  94. #endif