Kconfig 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262
  1. #
  2. # Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. #
  4. # SPDX-License-Identifier: GPL-2.0+
  5. #
  6. if TARGET_LIGHT_C910
  7. config PMIC_VOL_INIT
  8. bool "tuning light-ddr regulators"
  9. default n
  10. config DDR_REGU_0V6
  11. int "uint in uv"
  12. default 600000
  13. config DDR_REGU_0V8
  14. int "uint in uv"
  15. default 800000
  16. config DDR_REGU_1V1
  17. int "uint in uv"
  18. default 1100000
  19. config SYS_CPU
  20. default "c9xx"
  21. config SYS_VENDOR
  22. default "thead"
  23. config SYS_BOARD
  24. default "light-c910"
  25. config SYS_CONFIG_NAME
  26. default "light-c910"
  27. config LIGHT_SEC_UPGRADE
  28. bool "light secure upgrade"
  29. default n
  30. config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A
  31. bool "light board-a security boot with verification"
  32. default n
  33. config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B
  34. bool "light board-b security boot with verification"
  35. config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
  36. bool "light ant ref security boot with verification"
  37. config TARGET_LIGHT_FPGA_FM_C910
  38. bool "light fullmask FPGA board"
  39. default n
  40. config TARGET_LIGHT_FM_C910_VAL_SV
  41. bool "light fullmask VAL board for system validation"
  42. default n
  43. config TARGET_LIGHT_FM_C910_VAL_A
  44. bool "light fullmask VAL board-a for system validation"
  45. default n
  46. config TARGET_LIGHT_FM_C910_A_REF
  47. bool "light fullmask reference A board"
  48. default n
  49. config TARGET_LIGHT_FM_C910_VAL_B
  50. bool "light fullmask VAL board-b for system validation"
  51. default n
  52. config TARGET_LIGHT_FM_C910_B_REF
  53. bool "light fullmask reference B board"
  54. default n
  55. config TARGET_LIGHT_FM_C910_VAL_ANT_REF
  56. bool "light fullmask for ant-ref board "
  57. default n
  58. config TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE
  59. bool "light fullmask for ant-discrete board "
  60. default n
  61. config TARGET_LIGHT_FM_C910_BEAGLE
  62. bool "light fullmask for beagle board "
  63. default n
  64. config TARGET_LIGHT_FM_C910_B_POWER
  65. bool "light fullmask for light-b-power board "
  66. default n
  67. config SYS_TEXT_BASE
  68. default 0xc0000000 if RISCV_MMODE
  69. default 0x00200000 if RISCV_SMODE
  70. config SPL_TEXT_BASE
  71. hex
  72. default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
  73. default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
  74. config SPL_MAX_SIZE
  75. hex
  76. default 0x2f000
  77. config THEAD_PLIC
  78. bool "Light PLIC Setting"
  79. depends on RISCV_MMODE || SPL_RISCV_MMODE
  80. select REGMAP
  81. select SYSCON
  82. default n
  83. help
  84. The Thead PLIC block holds memory-mapped claim and pending registers
  85. associated with software interrupt.
  86. config THEAD_LIGHT_TIMER
  87. bool "Light TIMER0 driver and test"
  88. depends on THEAD_PLIC
  89. default n
  90. help
  91. The timer driver to verify the plic interrupt framework is ready
  92. config THEAD_LIGHT_DIGITAL_SENSOR
  93. bool "Light Digital Sensor Setting"
  94. depends on THEAD_PLIC
  95. default n
  96. help
  97. The security digital sensor driver
  98. config BOARD_SPECIFIC_OPTIONS
  99. def_bool y
  100. select RISCV_THEAD
  101. imply CMD_NET
  102. imply CMD_PING
  103. imply CMD_MEMINFO
  104. imply MII
  105. imply NET_RANDOM_ETHADDR
  106. imply PHY_LIB
  107. imply PHY_MSCC
  108. imply MMC
  109. imply MMC_SPI
  110. imply MMC_BROKEN_CD
  111. imply CMD_MMC
  112. if !TARGET_LIGHT_FPGA_FM_C910
  113. config DDR_LP4X_4266_DUALRANK
  114. bool "LPDDR4X 4266 dualrank configuration"
  115. help
  116. Enabling this will support lpddr4x 4266 dualrank configuration.
  117. config DDR_LP4X_4266_SINGLERANK
  118. bool "LPDDR4X 4266 singlerank configuration"
  119. help
  120. Enabling this will support lpddr4x 4266 singlerank configuration.
  121. config DDR_LP4X_3733_DUALRANK
  122. bool "LPDDR4X 3733 dualrank configuration"
  123. help
  124. Enabling this will support lpddr4x 3733 dualrank configuration.
  125. config DDR_LP4X_3733_SINGLERANK
  126. bool "LPDDR4X 3733 singlerank configuration"
  127. help
  128. Enabling this will support lpddr4x 3733 singlerank configuration.
  129. config DDR_LP4X_3200_DUALRANK
  130. bool "LPDDR4X 3200 dualrank configuration"
  131. help
  132. Enabling this will support lpddr4x 3200 dualrank configuration.
  133. config DDR_LP4X_3200_SINGLERANK
  134. bool "LPDDR4X 3200 singlerank configuration"
  135. help
  136. Enabling this will support lpddr4x 3200 singlerank configuration.
  137. config DDR_LP4X_2133_DUALRANK
  138. bool "LPDDR4X 2133 dualrank configuration"
  139. help
  140. Enabling this will support lpddr4x 2133 dualrank configuration.
  141. config DDR_LP4X_2133_SINGLERANK
  142. bool "LPDDR4X 2133 singlerank configuration"
  143. help
  144. Enabling this will support lpddr4x 2133 singlerank configuration.
  145. config DDR_LP4_4266_DUALRANK
  146. bool "LPDDR4 4266 dualrank configuration"
  147. help
  148. Enabling this will support lpddr4 4266 dualrank configuration.
  149. config DDR_LP4_4266_SINGLERANK
  150. bool "LPDDR4 4266 singlerank configuration"
  151. help
  152. Enabling this will support lpddr4 4266 singlerank configuration.
  153. config DDR_LP4_3733_DUALRANK
  154. bool "LPDDR4 3733 dualrank configuration"
  155. help
  156. Enabling this will support lpddr4 3733 dualrank configuration.
  157. config DDR_LP4_3733_SINGLERANK
  158. bool "LPDDR4 3733 singlerank configuration"
  159. help
  160. Enabling this will support lpddr4 3733 singlerank configuration.
  161. config DDR_LP4_3200_DUALRANK
  162. bool "LPDDR4 3200 dualrank configuration"
  163. help
  164. Enabling this will support lpddr4 3200 dualrank configuration.
  165. config DDR_LP4_3200_SINGLERANK
  166. bool "LPDDR4 3200 singlerank configuration"
  167. help
  168. Enabling this will support lpddr4 3200 singlerank configuration.
  169. config DDR_LP4_2133_DUALRANK
  170. bool "LPDDR4 2133 dualrank configuration"
  171. help
  172. Enabling this will support lpddr4 2133 dualrank configuration.
  173. config DDR_LP4_2133_SINGLERANK
  174. bool "LPDDR4 2133 singlerank configuration"
  175. help
  176. Enabling this will support lpddr4 2133 singlerank configuration.
  177. config DDR_H32_MODE
  178. bool "LPDDR4/4X 32bit mode configuration"
  179. help
  180. Enabling this will support ddr 32bit mode configuration.
  181. config LPDDR4X
  182. def_bool y if DDR_LP4X_4266_DUALRANK || DDR_LP4X_4266_SINGLERANK || DDR_LP4X_3733_DUALRANK || DDR_LP4X_3733_SINGLERANK \
  183. || DDR_LP4X_3200_DUALRANK || DDR_LP4X_3200_SINGLERANK || DDR_LP4X_2133_DUALRANK || DDR_LP4X_2133_SINGLERANK
  184. config LPDDR4
  185. def_bool y if !LPDDR4X && (DDR_LP4_4266_DUALRANK || DDR_LP4_4266_SINGLERANK || DDR_LP4_3733_DUALRANK || DDR_LP4_3733_SINGLERANK \
  186. || DDR_LP4_3200_DUALRANK || DDR_LP4_3200_SINGLERANK || DDR_LP4_2133_DUALRANK || DDR_LP4_2133_SINGLERANK)
  187. config LPDDR
  188. def_bool y if LPDDR4X || LPDDR4
  189. config DDR_4266
  190. def_bool y if DDR_LP4X_4266_DUALRANK || DDR_LP4X_4266_SINGLERANK || DDR_LP4_4266_DUALRANK || DDR_LP4_4266_SINGLERANK
  191. config DDR_3733
  192. def_bool y if DDR_LP4X_3733_DUALRANK || DDR_LP4X_3733_SINGLERANK || DDR_LP4_3733_DUALRANK || DDR_LP4_3733_SINGLERANK
  193. config DDR_3200
  194. def_bool y if DDR_LP4X_3200_DUALRANK || DDR_LP4X_3200_SINGLERANK || DDR_LP4_3200_DUALRANK || DDR_LP4_3200_SINGLERANK
  195. config DDR_2133
  196. def_bool y if DDR_LP4X_2133_DUALRANK || DDR_LP4X_2133_SINGLERANK || DDR_LP4_2133_DUALRANK || DDR_LP4_2133_SINGLERANK
  197. config FW_MSG_L3
  198. def_bool n
  199. config FW_MSG_L2
  200. def_bool n if !FW_MSG_L3
  201. config FW_MSG_L1
  202. def_bool n if !FW_MSG_L3 && !FW_MSG_L2
  203. config FW_MSG_TRAIN_1D
  204. def_bool n if FW_MSG_L2
  205. config DDR_MSG
  206. def_bool y if FW_MSG_L1 || FW_MSG_L2 || FW_MSG_L3
  207. config DDR_HARD_2D
  208. def_bool n
  209. config DDR_DUAL_RANK
  210. def_bool y if DDR_LP4X_4266_DUALRANK || DDR_LP4X_3733_DUALRANK || DDR_LP4X_3200_DUALRANK || DDR_LP4X_2133_DUALRANK \
  211. || DDR_LP4_4266_DUALRANK || DDR_LP4_3733_DUALRANK || DDR_LP4_3200_DUALRANK || DDR_LP4_2133_DUALRANK
  212. config DDR_CHBIT_256B
  213. def_bool y if !DDR_H32_MODE
  214. config DDR_DBI_OFF
  215. def_bool n
  216. config LPDDR_EYE
  217. def_bool n
  218. config LPDDR_TXEYE
  219. def_bool n if LPDDR_EYE
  220. endif
  221. endif