csr.h 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2015 Regents of the University of California
  4. *
  5. * Taken from Linux arch/riscv/include/asm/csr.h
  6. */
  7. #ifndef _ASM_RISCV_CSR_H
  8. #define _ASM_RISCV_CSR_H
  9. #include <asm/asm.h>
  10. #include <linux/const.h>
  11. /* Status register flags */
  12. #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
  13. #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
  14. #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
  15. #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
  16. #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
  17. #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
  18. #define SR_FS_OFF _AC(0x00000000, UL)
  19. #define SR_FS_INITIAL _AC(0x00002000, UL)
  20. #define SR_FS_CLEAN _AC(0x00004000, UL)
  21. #define SR_FS_DIRTY _AC(0x00006000, UL)
  22. #define SR_XS _AC(0x00018000, UL) /* Extension Status */
  23. #define SR_XS_OFF _AC(0x00000000, UL)
  24. #define SR_XS_INITIAL _AC(0x00008000, UL)
  25. #define SR_XS_CLEAN _AC(0x00010000, UL)
  26. #define SR_XS_DIRTY _AC(0x00018000, UL)
  27. #ifndef CONFIG_64BIT
  28. #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
  29. #else
  30. #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
  31. #endif
  32. /* SATP flags */
  33. #ifndef CONFIG_64BIT
  34. #define SATP_PPN _AC(0x003FFFFF, UL)
  35. #define SATP_MODE_32 _AC(0x80000000, UL)
  36. #define SATP_MODE SATP_MODE_32
  37. #else
  38. #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
  39. #define SATP_MODE_39 _AC(0x8000000000000000, UL)
  40. #define SATP_MODE SATP_MODE_39
  41. #endif
  42. /* SCAUSE */
  43. #define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
  44. #define IRQ_U_SOFT 0
  45. #define IRQ_S_SOFT 1
  46. #define IRQ_M_SOFT 3
  47. #define IRQ_U_TIMER 4
  48. #define IRQ_S_TIMER 5
  49. #define IRQ_M_TIMER 7
  50. #define IRQ_U_EXT 8
  51. #define IRQ_S_EXT 9
  52. #define IRQ_M_EXT 11
  53. #define EXC_INST_MISALIGNED 0
  54. #define EXC_INST_ACCESS 1
  55. #define EXC_BREAKPOINT 3
  56. #define EXC_LOAD_ACCESS 5
  57. #define EXC_STORE_ACCESS 7
  58. #define EXC_SYSCALL 8
  59. #define EXC_INST_PAGE_FAULT 12
  60. #define EXC_LOAD_PAGE_FAULT 13
  61. #define EXC_STORE_PAGE_FAULT 15
  62. /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
  63. #define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT)
  64. #define MIE_MEIE (_AC(0x1, UL) << IRQ_M_EXT)
  65. #define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
  66. #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER)
  67. #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT)
  68. #define CSR_FCSR 0x003
  69. #define CSR_CYCLE 0xc00
  70. #define CSR_TIME 0xc01
  71. #define CSR_INSTRET 0xc02
  72. #define CSR_SSTATUS 0x100
  73. #define CSR_SIE 0x104
  74. #define CSR_STVEC 0x105
  75. #define CSR_SCOUNTEREN 0x106
  76. #define CSR_SSCRATCH 0x140
  77. #define CSR_SEPC 0x141
  78. #define CSR_SCAUSE 0x142
  79. #define CSR_STVAL 0x143
  80. #define CSR_SIP 0x144
  81. #define CSR_SATP 0x180
  82. #define CSR_MSTATUS 0x300
  83. #define CSR_MISA 0x301
  84. #define CSR_MIE 0x304
  85. #define CSR_MTVEC 0x305
  86. #define CSR_MCOUNTEREN 0x306
  87. #define CSR_MSCRATCH 0x340
  88. #define CSR_MEPC 0x341
  89. #define CSR_MCAUSE 0x342
  90. #define CSR_MTVAL 0x343
  91. #define CSR_MIP 0x344
  92. #define CSR_CYCLEH 0xc80
  93. #define CSR_TIMEH 0xc81
  94. #define CSR_INSTRETH 0xc82
  95. #define CSR_MHARTID 0xf14
  96. #define CSR_SMPEN 0x7f3
  97. #define CSR_MTEE 0x7f4
  98. #define CSR_MCOR 0x7c2
  99. #define CSR_MHCR 0x7c1
  100. #define CSR_MCCR2 0x7c3
  101. #define CSR_MHINT 0x7c5
  102. #define CSR_MXSTATUS 0x7c0
  103. #define CSR_PLIC_BASE 0xfc1
  104. #define sync_is() asm volatile (".long 0x01b0000b")
  105. #ifndef __ASSEMBLY__
  106. #define csr_swap(csr, val) \
  107. ({ \
  108. unsigned long __v = (unsigned long)(val); \
  109. __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
  110. : "=r" (__v) : "rK" (__v) \
  111. : "memory"); \
  112. __v; \
  113. })
  114. #define csr_read(csr) \
  115. ({ \
  116. register unsigned long __v; \
  117. __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
  118. : "=r" (__v) : \
  119. : "memory"); \
  120. __v; \
  121. })
  122. #define csr_write(csr, val) \
  123. ({ \
  124. unsigned long __v = (unsigned long)(val); \
  125. __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
  126. : : "rK" (__v) \
  127. : "memory"); \
  128. })
  129. #define csr_read_set(csr, val) \
  130. ({ \
  131. unsigned long __v = (unsigned long)(val); \
  132. __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
  133. : "=r" (__v) : "rK" (__v) \
  134. : "memory"); \
  135. __v; \
  136. })
  137. #define csr_set(csr, val) \
  138. ({ \
  139. unsigned long __v = (unsigned long)(val); \
  140. __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
  141. : : "rK" (__v) \
  142. : "memory"); \
  143. })
  144. #define csr_read_clear(csr, val) \
  145. ({ \
  146. unsigned long __v = (unsigned long)(val); \
  147. __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
  148. : "=r" (__v) : "rK" (__v) \
  149. : "memory"); \
  150. __v; \
  151. })
  152. #define csr_clear(csr, val) \
  153. ({ \
  154. unsigned long __v = (unsigned long)(val); \
  155. __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
  156. : : "rK" (__v) \
  157. : "memory"); \
  158. })
  159. #endif /* __ASSEMBLY__ */
  160. #endif /* _ASM_RISCV_CSR_H */