light-fpga-fm-c910.dts 3.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184
  1. /dts-v1/;
  2. / {
  3. model = "T-HEAD c910 light";
  4. compatible = "thead,c910_light";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. memory@0 {
  8. device_type = "memory";
  9. reg = <0x0 0x0 0x1 0x0>;
  10. };
  11. aliases {
  12. spi0 = &spi0;
  13. spi1 = &qspi0;
  14. };
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. timebase-frequency = <3000000>;
  19. u-boot,dm-pre-reloc;
  20. cpu@0 {
  21. device_type = "cpu";
  22. reg = <0>;
  23. status = "okay";
  24. compatible = "riscv";
  25. riscv,isa = "rv64imafdcvsu";
  26. mmu-type = "riscv,sv39";
  27. u-boot,dm-pre-reloc;
  28. };
  29. };
  30. soc {
  31. #address-cells = <2>;
  32. #size-cells = <2>;
  33. compatible = "simple-bus";
  34. ranges;
  35. u-boot,dm-pre-reloc;
  36. dummy_apb: apb-clock {
  37. compatible = "fixed-clock";
  38. clock-frequency = <50000000>;
  39. clock-output-names = "dummy_apb";
  40. #clock-cells = <0>;
  41. u-boot,dm-pre-reloc;
  42. };
  43. dummy_ahb: ahb-clock {
  44. compatible = "fixed-clock";
  45. clock-frequency = <50000000>;
  46. clock-output-names = "core";
  47. #clock-cells = <0>;
  48. u-boot,dm-pre-reloc;
  49. };
  50. i2c0: i2c@ffe7f20000 {
  51. compatible = "snps,designware-i2c";
  52. reg = <0xff 0xe7f20000 0x0 0x4000>;
  53. clocks = <&dummy_apb>;
  54. clock-frequency = <100000>;
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. };
  58. serial@ffe7014000 {
  59. compatible = "snps,dw-apb-uart";
  60. reg = <0xff 0xe7014000 0x0 0x400>;
  61. clocks = <&dummy_apb>;
  62. clock-frequency = <50000000>;
  63. clock-names = "baudclk";
  64. reg-shift = <2>;
  65. reg-io-width = <4>;
  66. u-boot,dm-pre-reloc;
  67. };
  68. gmac: ethernet@ffe7070000 {
  69. compatible = "snps,dwmac";
  70. reg = <0xff 0xe7070000 0x0 0x2000>;
  71. clocks = <&dummy_apb>;
  72. clock-names = "stmmaceth";
  73. snps,pbl = <32>;
  74. snps,fixed-burst;
  75. max-speed = <100>;
  76. phy-mode = "mii";
  77. phy-handle = <&phy_88E1111>;
  78. mdio0 {
  79. #address-cells = <1>;
  80. #size-cells = <0>;
  81. compatible = "snps,dwmac-mdio";
  82. phy_88E1111: ethernet-phy@0 {
  83. reg = <0x0 0x0>;
  84. };
  85. };
  86. };
  87. emmc: sdhci@ffe7080000 {
  88. compatible = "snps,dwcmshc-sdhci";
  89. reg = <0xff 0xe7080000 0x0 0x10000>;
  90. index = <0x0>;
  91. clocks = <&dummy_ahb>;
  92. clock-frequency = <50000000>;
  93. clock-names = "core";
  94. max-frequency = <20000000>;
  95. sdhci-caps-mask = <0x0 0x1000000>;
  96. non-removable;
  97. no-sdio;
  98. no-sd;
  99. bus-width = <8>;
  100. fifo-mode;
  101. u-boot,dm-pre-reloc;
  102. };
  103. sdhci0: sd@ffe7090000 {
  104. compatible = "snps,dwcmshc-sdhci";
  105. reg = <0xff 0xe7090000 0x0 0x10000>;
  106. index = <0x1>;
  107. clocks = <&dummy_ahb>;
  108. clock-frequency = <50000000>;
  109. max-frequency = <20000000>;
  110. //sd-uhs-sdr104 = "true";
  111. clock-names = "core";
  112. bus-width = <4>;
  113. voltage= "3.3v";
  114. };
  115. qspi0: spi@ffea000000 {
  116. compatible = "snps,dw-apb-ssi-quad";
  117. reg = <0xff 0xea000000 0x0 0x1000>;
  118. clocks = <&dummy_apb>;
  119. num-cs = <1>;
  120. cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
  121. spi-max-frequency = <3125000>;
  122. #address-cells = <1>;
  123. #size-cells =<0>;
  124. spi-flash@0 {
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. compatible = "spi-nand";
  128. spi-tx-bus-width = <4>;
  129. spi-rx-bus-width = <4>;
  130. reg = <0>;
  131. };
  132. };
  133. spi0: spi@ffe700c000 {
  134. compatible = "snps,dw-apb-ssi";
  135. reg = <0xff 0xe700c000 0x0 0x1000>;
  136. clocks = <&dummy_apb>;
  137. cs-gpio = <&gpio2_porta 15 0>;
  138. spi-max-frequency = <12500000>;
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. flash@0 {
  142. compatible = "jedec,spi-nor";
  143. reg = <0>;
  144. spi-max-frequency = <12500000>;
  145. };
  146. };
  147. gpio2: gpio@ffe7f34000 {
  148. compatible = "snps,dw-apb-gpio";
  149. reg = <0xff 0xe7f34000 0x0 0x1000>;
  150. clocks = <&dummy_apb>;
  151. #address-cells = <1>;
  152. #size-cells = <0>;
  153. gpio2_porta: gpio-controller@0 {
  154. compatible = "snps,dw-apb-gpio-port";
  155. gpio-controller;
  156. #gpio-cells = <2>;
  157. snps,nr-gpios = <32>;
  158. reg = <0>;
  159. };
  160. };
  161. };
  162. chosen {
  163. bootargs = "console=ttyS0,115200";
  164. stdout-path = "/soc/serial@ffe7014000:115200";
  165. };
  166. };