light-beagle.dts 11 KB

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  1. /dts-v1/;
  2. / {
  3. model = "T-HEAD c910 light";
  4. compatible = "thead,c910_light";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. memory@0 {
  8. device_type = "memory";
  9. reg = <0x0 0xc0000000 0x0 0x40000000>;
  10. };
  11. aliases {
  12. spi0 = &spi0;
  13. spi1 = &qspi0;
  14. spi2 = &qspi1;
  15. };
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. timebase-frequency = <3000000>;
  20. u-boot,dm-pre-reloc;
  21. cpu@0 {
  22. device_type = "cpu";
  23. reg = <0>;
  24. status = "okay";
  25. compatible = "riscv";
  26. riscv,isa = "rv64imafdcvsu";
  27. mmu-type = "riscv,sv39";
  28. u-boot,dm-pre-reloc;
  29. };
  30. };
  31. soc {
  32. #address-cells = <2>;
  33. #size-cells = <2>;
  34. compatible = "simple-bus";
  35. ranges;
  36. u-boot,dm-pre-reloc;
  37. intc: interrupt-controller@ffd8000000 {
  38. compatible = "riscv,plic0";
  39. reg = <0xff 0xd8000000 0x0 0x04000000>;
  40. status = "disabled";
  41. };
  42. dummy_apb: apb-clock {
  43. compatible = "fixed-clock";
  44. clock-frequency = <62500000>;
  45. clock-output-names = "dummy_apb";
  46. #clock-cells = <0>;
  47. u-boot,dm-pre-reloc;
  48. };
  49. dummy_ahb: ahb-clock {
  50. compatible = "fixed-clock";
  51. clock-frequency = <250000000>;
  52. clock-output-names = "core";
  53. #clock-cells = <0>;
  54. u-boot,dm-pre-reloc;
  55. };
  56. dummy_spi: spi-clock {
  57. compatible = "fixed-clock";
  58. clock-frequency = <396000000>;
  59. clock-output-names = "dummy_spi";
  60. #clock-cells = <0>;
  61. u-boot,dm-pre-reloc;
  62. };
  63. dummy_qspi0: qspi0-clock {
  64. compatible = "fixed-clock";
  65. clock-frequency = <792000000>;
  66. clock-output-names = "dummy_qspi0";
  67. #clock-cells = <0>;
  68. u-boot,dm-pre-reloc;
  69. };
  70. dummy_uart_sclk: uart-sclk-clock {
  71. compatible = "fixed-clock";
  72. clock-frequency = <100000000>;
  73. clock-output-names = "dummy_uart_sclk";
  74. #clock-cells = <0>;
  75. u-boot,dm-pre-reloc;
  76. };
  77. dummy_i2c_icclk: i2c-icclk-clock {
  78. compatible = "fixed-clock";
  79. clock-frequency = <50000000>;
  80. clock-output-names = "dummy_i2c_icclk";
  81. #clock-cells = <0>;
  82. u-boot,dm-pre-reloc;
  83. };
  84. dummy_dpu_pixclk: dpu-pix-clock {
  85. compatible = "fixed-clock";
  86. clock-frequency = <74250000>;
  87. clock-output-names = "dummy_dpu_pixclk";
  88. #clock-cells = <0>;
  89. u-boot,dm-pre-reloc;
  90. };
  91. dummy_dphy_refclk: dphy-ref-clock {
  92. compatible = "fixed-clock";
  93. clock-frequency = <24000000>;
  94. clock-output-names = "dummy_dpu_refclk";
  95. #clock-cells = <0>;
  96. u-boot,dm-pre-reloc;
  97. };
  98. i2c0: i2c@ffe7f20000 {
  99. compatible = "snps,designware-i2c";
  100. reg = <0xff 0xe7f20000 0x0 0x4000>;
  101. clocks = <&dummy_i2c_icclk>;
  102. clock-frequency = <100000>;
  103. #address-cells = <1>;
  104. #size-cells = <0>;
  105. };
  106. i2c1: i2c@ffe7f24000{
  107. compatible = "snps,designware-i2c";
  108. reg = <0xff 0xe7f24000 0x0 0x4000>;
  109. clocks = <&dummy_i2c_icclk>;
  110. clock-frequency = <100000>;
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. };
  114. i2c2: i2c@ffec00c000{
  115. compatible = "snps,designware-i2c";
  116. reg = <0xff 0xec00c000 0x0 0x4000>;
  117. clocks = <&dummy_i2c_icclk>;
  118. clock-frequency = <100000>;
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. };
  122. i2c3: i2c@ffec014000{
  123. compatible = "snps,designware-i2c";
  124. reg = <0xff 0xec014000 0x0 0x4000>;
  125. clocks = <&dummy_i2c_icclk>;
  126. clock-frequency = <100000>;
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. };
  130. i2c4: i2c@ffe7f28000{
  131. compatible = "snps,designware-i2c";
  132. reg = <0xff 0xe7f28000 0x0 0x4000>;
  133. clocks = <&dummy_i2c_icclk>;
  134. clock-frequency = <100000>;
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. pcal6408ahk_a: gpio@20 {
  138. compatible = "nxp,pca9554";
  139. reg = <0x20>;
  140. gpio-controller;
  141. #gpio-cells = <2>;
  142. };
  143. };
  144. i2c5: i2c@fff7f2c000{
  145. compatible = "snps,designware-i2c";
  146. reg = <0xff 0xf7f2c000 0x0 0x4000>;
  147. clocks = <&dummy_i2c_icclk>;
  148. clock-frequency = <100000>;
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. };
  152. serial@ffe7014000 {
  153. compatible = "snps,dw-apb-uart";
  154. reg = <0xff 0xe7014000 0x0 0x400>;
  155. clocks = <&dummy_uart_sclk>;
  156. clock-frequency = <100000000>;
  157. clock-names = "baudclk";
  158. reg-shift = <2>;
  159. reg-io-width = <4>;
  160. u-boot,dm-pre-reloc;
  161. };
  162. gmac0: ethernet@ffe7070000 {
  163. compatible = "snps,dwmac";
  164. reg = <0xff 0xe7070000 0x0 0x2000>;
  165. clocks = <&dummy_apb>;
  166. clock-names = "stmmaceth";
  167. snps,pbl = <32>;
  168. snps,fixed-burst;
  169. phy-mode = "rgmii-id";
  170. phy-handle = <&phy_88E1111_a>;
  171. status = "okay";
  172. mdio0 {
  173. #address-cells = <1>;
  174. #size-cells = <0>;
  175. compatible = "snps,dwmac-mdio";
  176. phy_88E1111_a: ethernet-phy@1 {
  177. reg = <0x1>;
  178. };
  179. phy_88E1111_b: ethernet-phy@2 {
  180. reg = <0x2>;
  181. };
  182. };
  183. };
  184. gmac1: ethernet@ffe7060000 {
  185. compatible = "snps,dwmac";
  186. reg = <0xff 0xe7060000 0x0 0x2000>;
  187. clocks = <&dummy_apb>;
  188. clock-names = "stmmaceth";
  189. snps,pbl = <32>;
  190. snps,fixed-burst;
  191. phy-mode = "rgmii-id";
  192. phy-handle = <&phy_88E1111_b>;
  193. status = "okay";
  194. };
  195. emmc: sdhci@ffe7080000 {
  196. compatible = "snps,dwcmshc-sdhci";
  197. reg = <0xff 0xe7080000 0x0 0x10000>;
  198. index = <0x0>;
  199. clocks = <&dummy_ahb>;
  200. clock-frequency = <198000000>;
  201. clock-names = "core";
  202. max-frequency = <198000000>;
  203. sdhci-caps-mask = <0x0 0x1000000>;
  204. mmc-hs400-1_8v;
  205. non-removable;
  206. no-sdio;
  207. no-sd;
  208. bus-width = <8>;
  209. voltage= "1.8v";
  210. pull_up;
  211. io_fixed_1v8;
  212. fifo-mode;
  213. u-boot,dm-pre-reloc;
  214. };
  215. sdhci0: sd@ffe7090000 {
  216. compatible = "snps,dwcmshc-sdhci";
  217. reg = <0xff 0xe7090000 0x0 0x10000>;
  218. index = <0x1>;
  219. clocks = <&dummy_ahb>;
  220. clock-frequency = <198000000>;
  221. max-frequency = <198000000>;
  222. sd-uhs-sdr104;
  223. pull_up;
  224. clock-names = "core";
  225. bus-width = <4>;
  226. voltage= "3.3v";
  227. };
  228. qspi0: spi@ffea000000 {
  229. compatible = "snps,dw-apb-ssi-quad";
  230. reg = <0xff 0xea000000 0x0 0x1000>;
  231. clocks = <&dummy_qspi0>;
  232. num-cs = <1>;
  233. cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
  234. spi-max-frequency = <100000000>;
  235. #address-cells = <1>;
  236. #size-cells =<0>;
  237. spi-flash@0 {
  238. #address-cells = <1>;
  239. #size-cells = <1>;
  240. compatible = "spi-nand";
  241. spi-tx-bus-width = <4>;
  242. spi-rx-bus-width = <4>;
  243. reg = <0>;
  244. };
  245. };
  246. qspi1: spi@fff8000000 {
  247. compatible = "snps,dw-apb-ssi-quad";
  248. reg = <0xff 0xf8000000 0x0 0x1000>;
  249. clocks = <&dummy_spi>;
  250. num-cs = <1>;
  251. cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
  252. spi-max-frequency = <66000000>;
  253. #address-cells = <1>;
  254. #size-cells =<0>;
  255. spi-flash@0 {
  256. #address-cells = <1>;
  257. #size-cells = <1>;
  258. compatible = "spi-nand";
  259. spi-tx-bus-width = <4>;
  260. spi-rx-bus-width = <4>;
  261. reg = <0>;
  262. };
  263. };
  264. spi0: spi@ffe700c000 {
  265. compatible = "snps,dw-apb-ssi";
  266. reg = <0xff 0xe700c000 0x0 0x1000>;
  267. clocks = <&dummy_spi>;
  268. cs-gpio = <&gpio2_porta 15 0>;
  269. spi-max-frequency = <100000000>;
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. flash@0 {
  273. compatible = "jedec,spi-nor";
  274. reg = <0>;
  275. spi-max-frequency = <40000000>;
  276. };
  277. };
  278. gpio2: gpio@ffe7f34000 {
  279. compatible = "snps,dw-apb-gpio";
  280. reg = <0xff 0xe7f34000 0x0 0x1000>;
  281. clocks = <&dummy_apb>;
  282. #address-cells = <1>;
  283. #size-cells = <0>;
  284. gpio2_porta: gpio-controller@0 {
  285. compatible = "snps,dw-apb-gpio-port";
  286. gpio-controller;
  287. #gpio-cells = <2>;
  288. snps,nr-gpios = <32>;
  289. reg = <0>;
  290. };
  291. };
  292. gpio0: gpio@ffec005000 {
  293. compatible = "snps,dw-apb-gpio";
  294. reg = <0xff 0xec005000 0x0 0x1000>;
  295. clocks = <&dummy_apb>;
  296. #address-cells = <1>;
  297. #size-cells = <0>;
  298. gpio0_porta: gpio-controller@0 {
  299. compatible = "snps,dw-apb-gpio-port";
  300. gpio-controller;
  301. #gpio-cells = <2>;
  302. snps,nr-gpios = <32>;
  303. reg = <0>;
  304. };
  305. };
  306. gpio1: gpio@ffec006000 {
  307. compatible = "snps,dw-apb-gpio";
  308. reg = <0xff 0xec006000 0x0 0x1000>;
  309. clocks = <&dummy_apb>;
  310. #address-cells = <1>;
  311. #size-cells = <0>;
  312. gpio1_porta: gpio-controller@0 {
  313. compatible = "snps,dw-apb-gpio-port";
  314. gpio-controller;
  315. #gpio-cells = <2>;
  316. snps,nr-gpios = <32>;
  317. reg = <0>;
  318. };
  319. };
  320. pwm: pwm@ffec01c000 {
  321. compatible = "thead,pwm-light";
  322. reg = <0xff 0xec01c000 0x0 0x4000>;
  323. #pwm-cells = <2>;
  324. };
  325. dsi_regs: dsi-controller@ffef500000 {
  326. compatible = "thead,light-dsi-regs", "syscon";
  327. reg = <0xff 0xef500000 0x0 0x10000>;
  328. status = "okay";
  329. };
  330. vosys_regs: vosys@ffef528000 {
  331. compatible = "thead,light-vo-subsys", "syscon";
  332. reg = <0xff 0xef528000 0x0 0x1000>;
  333. status = "okay";
  334. };
  335. dpu: dc8200@ffef600000 {
  336. compatible = "verisilicon,dc8200";
  337. reg = <0xff 0xef600000 0x0 0x100>;
  338. };
  339. axiscr {
  340. compatible = "thead,axiscr";
  341. reg = <0xff 0xff004000 0x0 0x1000>;
  342. lock-read = "okay";
  343. lock-write = "okay";
  344. #address-cells = <2>;
  345. #size-cells = <2>;
  346. u-boot,dm-pre-reloc;
  347. axiscr0: axisrc@0 {
  348. device_type = "axiscr";
  349. region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
  350. status = "disabled";
  351. #address-cells = <2>;
  352. #size-cells = <2>;
  353. u-boot,dm-pre-reloc;
  354. };
  355. axiscr1: axisrc@1 {
  356. device_type = "axiscr";
  357. region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
  358. status = "disabled";
  359. #address-cells = <2>;
  360. #size-cells = <2>;
  361. u-boot,dm-pre-reloc;
  362. };
  363. axiscr2: axisrc@2 {
  364. device_type = "axiscr";
  365. region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
  366. status = "disabled";
  367. #address-cells = <2>;
  368. #size-cells = <2>;
  369. u-boot,dm-pre-reloc;
  370. };
  371. };
  372. axiparity {
  373. compatible = "thead,axiparity";
  374. reg = <0xff 0xff00c000 0x0 0x1000>;
  375. lock = "okay";
  376. #address-cells = <2>;
  377. #size-cells = <2>;
  378. u-boot,dm-pre-reloc;
  379. axiparity0: axiparity@0 {
  380. device_type = "axiparity";
  381. region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
  382. status = "disabled";
  383. #address-cells = <2>;
  384. #size-cells = <2>;
  385. u-boot,dm-pre-reloc;
  386. };
  387. axiparity1: axiparity@1 {
  388. device_type = "axiparity";
  389. region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
  390. status = "disabled";
  391. #address-cells = <2>;
  392. #size-cells = <2>;
  393. u-boot,dm-pre-reloc;
  394. };
  395. };
  396. dsi_bridge: dsi-bridge {
  397. compatible = "thead,light-dsi-bridge";
  398. clocks = <&dummy_dpu_pixclk>;
  399. clock-names = "pix-clk";
  400. phys = <&dsi_dphy>;
  401. phy-names = "dphy";
  402. };
  403. dsi_host: dsi-host {
  404. compatible = "synopsys,dw-mipi-dsi";
  405. regmap = <&dsi_regs>;
  406. status = "okay";
  407. };
  408. dsi_dphy: dsi-dphy {
  409. compatible = "synopsys,dw-dphy";
  410. regmap = <&dsi_regs>;
  411. vosys-regmap = <&vosys_regs>;
  412. clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
  413. clock-names = "pix-clk", "ref-clk";
  414. #phy-cells = <0>;
  415. status = "okay";
  416. };
  417. lcd_backlight: pwm-backlight {
  418. compatible = "pwm-backlight";
  419. pwms = <&pwm 0 5000000>;
  420. brightness-levels = <0 4 8 16 32 64 128 255>;
  421. default-brightness-level = <7>;
  422. };
  423. ili9881c_panel {
  424. compatible = "ilitek,ili9881c";
  425. backlight = <&lcd_backlight>;
  426. reset-gpios = <&gpio1_porta 5 1>; /* active low */
  427. lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
  428. lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
  429. };
  430. };
  431. chosen {
  432. bootargs = "console=ttyS0,115200";
  433. stdout-path = "/soc/serial@ffe7014000:115200";
  434. };
  435. };