light-b-product.dts 11 KB

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  1. /dts-v1/;
  2. / {
  3. model = "T-HEAD c910 light";
  4. compatible = "thead,c910_light";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. memory@0 {
  8. device_type = "memory";
  9. reg = <0x0 0xc0000000 0x0 0x40000000>;
  10. };
  11. aliases {
  12. spi0 = &spi0;
  13. spi1 = &qspi0;
  14. spi2 = &qspi1;
  15. };
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. timebase-frequency = <3000000>;
  20. u-boot,dm-pre-reloc;
  21. cpu@0 {
  22. device_type = "cpu";
  23. reg = <0>;
  24. status = "okay";
  25. compatible = "riscv";
  26. riscv,isa = "rv64imafdcvsu";
  27. mmu-type = "riscv,sv39";
  28. u-boot,dm-pre-reloc;
  29. };
  30. };
  31. soc {
  32. #address-cells = <2>;
  33. #size-cells = <2>;
  34. compatible = "simple-bus";
  35. ranges;
  36. u-boot,dm-pre-reloc;
  37. dummy_apb: apb-clock {
  38. compatible = "fixed-clock";
  39. clock-frequency = <62500000>;
  40. clock-output-names = "dummy_apb";
  41. #clock-cells = <0>;
  42. u-boot,dm-pre-reloc;
  43. };
  44. dummy_ahb: ahb-clock {
  45. compatible = "fixed-clock";
  46. clock-frequency = <250000000>;
  47. clock-output-names = "core";
  48. #clock-cells = <0>;
  49. u-boot,dm-pre-reloc;
  50. };
  51. dummy_spi: spi-clock {
  52. compatible = "fixed-clock";
  53. clock-frequency = <396000000>;
  54. clock-output-names = "dummy_spi";
  55. #clock-cells = <0>;
  56. u-boot,dm-pre-reloc;
  57. };
  58. dummy_qspi0: qspi0-clock {
  59. compatible = "fixed-clock";
  60. clock-frequency = <792000000>;
  61. clock-output-names = "dummy_qspi0";
  62. #clock-cells = <0>;
  63. u-boot,dm-pre-reloc;
  64. };
  65. dummy_uart_sclk: uart-sclk-clock {
  66. compatible = "fixed-clock";
  67. clock-frequency = <100000000>;
  68. clock-output-names = "dummy_uart_sclk";
  69. #clock-cells = <0>;
  70. u-boot,dm-pre-reloc;
  71. };
  72. dummy_i2c_icclk: i2c-icclk-clock {
  73. compatible = "fixed-clock";
  74. clock-frequency = <50000000>;
  75. clock-output-names = "dummy_i2c_icclk";
  76. #clock-cells = <0>;
  77. u-boot,dm-pre-reloc;
  78. };
  79. dummy_dpu_pixclk: dpu-pix-clock {
  80. compatible = "fixed-clock";
  81. clock-frequency = <74250000>;
  82. clock-output-names = "dummy_dpu_pixclk";
  83. #clock-cells = <0>;
  84. u-boot,dm-pre-reloc;
  85. };
  86. dummy_dphy_refclk: dphy-ref-clock {
  87. compatible = "fixed-clock";
  88. clock-frequency = <24000000>;
  89. clock-output-names = "dummy_dpu_refclk";
  90. #clock-cells = <0>;
  91. u-boot,dm-pre-reloc;
  92. };
  93. i2c0: i2c@ffe7f20000 {
  94. compatible = "snps,designware-i2c";
  95. reg = <0xff 0xe7f20000 0x0 0x4000>;
  96. clocks = <&dummy_i2c_icclk>;
  97. clock-frequency = <100000>;
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. };
  101. i2c1: i2c@ffe7f24000{
  102. compatible = "snps,designware-i2c";
  103. reg = <0xff 0xe7f24000 0x0 0x4000>;
  104. clocks = <&dummy_i2c_icclk>;
  105. clock-frequency = <100000>;
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. };
  109. i2c2: i2c@ffec00c000{
  110. compatible = "snps,designware-i2c";
  111. reg = <0xff 0xec00c000 0x0 0x4000>;
  112. clocks = <&dummy_i2c_icclk>;
  113. clock-frequency = <100000>;
  114. #address-cells = <1>;
  115. #size-cells = <0>;
  116. };
  117. i2c3: i2c@ffec014000{
  118. compatible = "snps,designware-i2c";
  119. reg = <0xff 0xec014000 0x0 0x4000>;
  120. clocks = <&dummy_i2c_icclk>;
  121. clock-frequency = <100000>;
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. };
  125. i2c4: i2c@ffe7f28000{
  126. compatible = "snps,designware-i2c";
  127. reg = <0xff 0xe7f28000 0x0 0x4000>;
  128. clocks = <&dummy_i2c_icclk>;
  129. clock-frequency = <100000>;
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. };
  133. i2c5: i2c@fff7f2c000{
  134. compatible = "snps,designware-i2c";
  135. reg = <0xff 0xf7f2c000 0x0 0x4000>;
  136. clocks = <&dummy_i2c_icclk>;
  137. clock-frequency = <100000>;
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. };
  141. serial@ffe7014000 {
  142. compatible = "snps,dw-apb-uart";
  143. reg = <0xff 0xe7014000 0x0 0x400>;
  144. clocks = <&dummy_uart_sclk>;
  145. clock-frequency = <100000000>;
  146. clock-names = "baudclk";
  147. reg-shift = <2>;
  148. reg-io-width = <4>;
  149. u-boot,dm-pre-reloc;
  150. };
  151. gmac0: ethernet@ffe7070000 {
  152. compatible = "snps,dwmac";
  153. reg = <0xff 0xe7070000 0x0 0x2000>;
  154. clocks = <&dummy_apb>;
  155. clock-names = "stmmaceth";
  156. snps,pbl = <32>;
  157. snps,fixed-burst;
  158. phy-mode = "rgmii-id";
  159. phy-handle = <&phy_88E1111_a>;
  160. status = "okay";
  161. mdio0 {
  162. #address-cells = <1>;
  163. #size-cells = <0>;
  164. compatible = "snps,dwmac-mdio";
  165. phy_88E1111_a: ethernet-phy@1 {
  166. reg = <0x1>;
  167. };
  168. phy_88E1111_b: ethernet-phy@2 {
  169. reg = <0x2>;
  170. };
  171. };
  172. };
  173. gmac1: ethernet@ffe7060000 {
  174. compatible = "snps,dwmac";
  175. reg = <0xff 0xe7060000 0x0 0x2000>;
  176. clocks = <&dummy_apb>;
  177. clock-names = "stmmaceth";
  178. snps,pbl = <32>;
  179. snps,fixed-burst;
  180. phy-mode = "rgmii-id";
  181. phy-handle = <&phy_88E1111_b>;
  182. status = "disabled";
  183. };
  184. emmc: sdhci@ffe7080000 {
  185. compatible = "snps,dwcmshc-sdhci";
  186. reg = <0xff 0xe7080000 0x0 0x10000>;
  187. index = <0x0>;
  188. clocks = <&dummy_ahb>;
  189. clock-frequency = <198000000>;
  190. clock-names = "core";
  191. max-frequency = <198000000>;
  192. sdhci-caps-mask = <0x0 0x1000000>;
  193. mmc-hs400-1_8v;
  194. non-removable;
  195. no-sdio;
  196. no-sd;
  197. bus-width = <8>;
  198. voltage= "1.8v";
  199. pull_up;
  200. io_fixed_1v8;
  201. fifo-mode;
  202. u-boot,dm-pre-reloc;
  203. };
  204. sdhci0: sd@ffe7090000 {
  205. compatible = "snps,dwcmshc-sdhci";
  206. reg = <0xff 0xe7090000 0x0 0x10000>;
  207. index = <0x1>;
  208. clocks = <&dummy_ahb>;
  209. clock-frequency = <198000000>;
  210. max-frequency = <198000000>;
  211. sd-uhs-sdr104;
  212. pull_up;
  213. clock-names = "core";
  214. bus-width = <4>;
  215. voltage= "3.3v";
  216. };
  217. qspi0: spi@ffea000000 {
  218. compatible = "snps,dw-apb-ssi-quad";
  219. reg = <0xff 0xea000000 0x0 0x1000>;
  220. clocks = <&dummy_qspi0>;
  221. num-cs = <1>;
  222. cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
  223. spi-max-frequency = <100000000>;
  224. #address-cells = <1>;
  225. #size-cells =<0>;
  226. status = "disabled";
  227. spi-flash@0 {
  228. #address-cells = <1>;
  229. #size-cells = <1>;
  230. compatible = "spi-nand";
  231. spi-tx-bus-width = <4>;
  232. spi-rx-bus-width = <4>;
  233. reg = <0>;
  234. };
  235. };
  236. qspi1: spi@fff8000000 {
  237. compatible = "snps,dw-apb-ssi-quad";
  238. reg = <0xff 0xf8000000 0x0 0x1000>;
  239. clocks = <&dummy_spi>;
  240. num-cs = <1>;
  241. cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
  242. spi-max-frequency = <66000000>;
  243. #address-cells = <1>;
  244. #size-cells =<0>;
  245. status = "disabled";
  246. spi-flash@0 {
  247. #address-cells = <1>;
  248. #size-cells = <1>;
  249. compatible = "spi-nand";
  250. spi-tx-bus-width = <4>;
  251. spi-rx-bus-width = <4>;
  252. reg = <0>;
  253. };
  254. };
  255. spi0: spi@ffe700c000 {
  256. compatible = "snps,dw-apb-ssi";
  257. reg = <0xff 0xe700c000 0x0 0x1000>;
  258. clocks = <&dummy_spi>;
  259. cs-gpio = <&gpio2_porta 15 0>;
  260. spi-max-frequency = <100000000>;
  261. #address-cells = <1>;
  262. #size-cells = <0>;
  263. status = "disabled";
  264. flash@0 {
  265. compatible = "jedec,spi-nor";
  266. reg = <0>;
  267. spi-max-frequency = <40000000>;
  268. };
  269. };
  270. gpio2: gpio@ffe7f34000 {
  271. compatible = "snps,dw-apb-gpio";
  272. reg = <0xff 0xe7f34000 0x0 0x1000>;
  273. clocks = <&dummy_apb>;
  274. #address-cells = <1>;
  275. #size-cells = <0>;
  276. gpio2_porta: gpio-controller@0 {
  277. compatible = "snps,dw-apb-gpio-port";
  278. gpio-controller;
  279. #gpio-cells = <2>;
  280. snps,nr-gpios = <32>;
  281. reg = <0>;
  282. };
  283. };
  284. gpio0: gpio@ffec005000 {
  285. compatible = "snps,dw-apb-gpio";
  286. reg = <0xff 0xec005000 0x0 0x1000>;
  287. clocks = <&dummy_apb>;
  288. #address-cells = <1>;
  289. #size-cells = <0>;
  290. gpio0_porta: gpio-controller@0 {
  291. compatible = "snps,dw-apb-gpio-port";
  292. gpio-controller;
  293. #gpio-cells = <2>;
  294. snps,nr-gpios = <32>;
  295. reg = <0>;
  296. };
  297. };
  298. gpio1: gpio@ffec006000 {
  299. compatible = "snps,dw-apb-gpio";
  300. reg = <0xff 0xec006000 0x0 0x1000>;
  301. clocks = <&dummy_apb>;
  302. #address-cells = <1>;
  303. #size-cells = <0>;
  304. gpio1_porta: gpio-controller@0 {
  305. compatible = "snps,dw-apb-gpio-port";
  306. gpio-controller;
  307. #gpio-cells = <2>;
  308. snps,nr-gpios = <32>;
  309. reg = <0>;
  310. };
  311. };
  312. pwm: pwm@ffec01c000 {
  313. compatible = "thead,pwm-light";
  314. reg = <0xff 0xec01c000 0x0 0x4000>;
  315. #pwm-cells = <2>;
  316. };
  317. dsi_regs: dsi-controller@ffef500000 {
  318. compatible = "thead,light-dsi-regs", "syscon";
  319. reg = <0xff 0xef500000 0x0 0x10000>;
  320. status = "okay";
  321. };
  322. vosys_regs: vosys@ffef528000 {
  323. compatible = "thead,light-vo-subsys", "syscon";
  324. reg = <0xff 0xef528000 0x0 0x1000>;
  325. status = "okay";
  326. };
  327. dpu: dc8200@ffef600000 {
  328. compatible = "verisilicon,dc8200";
  329. reg = <0xff 0xef600000 0x0 0x100>;
  330. };
  331. axiscr {
  332. compatible = "thead,axiscr";
  333. reg = <0xff 0xff004000 0x0 0x1000>;
  334. lock-read = "okay";
  335. lock-write = "okay";
  336. #address-cells = <2>;
  337. #size-cells = <2>;
  338. u-boot,dm-pre-reloc;
  339. axiscr0: axisrc@0 {
  340. device_type = "axiscr";
  341. region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
  342. status = "disabled";
  343. #address-cells = <2>;
  344. #size-cells = <2>;
  345. u-boot,dm-pre-reloc;
  346. };
  347. axiscr1: axisrc@1 {
  348. device_type = "axiscr";
  349. region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
  350. status = "disabled";
  351. #address-cells = <2>;
  352. #size-cells = <2>;
  353. u-boot,dm-pre-reloc;
  354. };
  355. axiscr2: axisrc@2 {
  356. device_type = "axiscr";
  357. region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
  358. status = "disabled";
  359. #address-cells = <2>;
  360. #size-cells = <2>;
  361. u-boot,dm-pre-reloc;
  362. };
  363. };
  364. axiparity {
  365. compatible = "thead,axiparity";
  366. reg = <0xff 0xff00c000 0x0 0x1000>;
  367. lock = "okay";
  368. #address-cells = <2>;
  369. #size-cells = <2>;
  370. u-boot,dm-pre-reloc;
  371. axiparity0: axiparity@0 {
  372. device_type = "axiparity";
  373. region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
  374. status = "disabled";
  375. #address-cells = <2>;
  376. #size-cells = <2>;
  377. u-boot,dm-pre-reloc;
  378. };
  379. axiparity1: axiparity@1 {
  380. device_type = "axiparity";
  381. region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
  382. status = "disabled";
  383. #address-cells = <2>;
  384. #size-cells = <2>;
  385. u-boot,dm-pre-reloc;
  386. };
  387. };
  388. dsi_bridge: dsi-bridge {
  389. compatible = "thead,light-dsi-bridge";
  390. clocks = <&dummy_dpu_pixclk>;
  391. clock-names = "pix-clk";
  392. phys = <&dsi_dphy>;
  393. phy-names = "dphy";
  394. };
  395. dsi_host: dsi-host {
  396. compatible = "synopsys,dw-mipi-dsi";
  397. regmap = <&dsi_regs>;
  398. status = "okay";
  399. };
  400. dsi_dphy: dsi-dphy {
  401. compatible = "synopsys,dw-dphy";
  402. regmap = <&dsi_regs>;
  403. vosys-regmap = <&vosys_regs>;
  404. clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
  405. clock-names = "pix-clk", "ref-clk";
  406. #phy-cells = <0>;
  407. status = "okay";
  408. };
  409. lcd_backlight: pwm-backlight {
  410. compatible = "pwm-backlight";
  411. pwms = <&pwm 0 5000000>;
  412. brightness-levels = <0 4 8 16 32 64 128 255>;
  413. default-brightness-level = <7>;
  414. };
  415. ili9881c_panel {
  416. compatible = "ilitek,ili9881c";
  417. backlight = <&lcd_backlight>;
  418. reset-gpios = <&gpio1_porta 5 1>; /* active low */
  419. lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
  420. lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
  421. };
  422. };
  423. chosen {
  424. bootargs = "console=ttyS0,115200";
  425. stdout-path = "/soc/serial@ffe7014000:115200";
  426. };
  427. };