light-ant-ref.dts 11 KB

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  1. /dts-v1/;
  2. / {
  3. model = "T-HEAD c910 light";
  4. compatible = "thead,c910_light";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. memory@0 {
  8. device_type = "memory";
  9. reg = <0x0 0xc0000000 0x0 0x40000000>;
  10. };
  11. aliases {
  12. spi0 = &spi0;
  13. spi1 = &qspi0;
  14. spi2 = &qspi1;
  15. };
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. timebase-frequency = <3000000>;
  20. u-boot,dm-pre-reloc;
  21. cpu@0 {
  22. device_type = "cpu";
  23. reg = <0>;
  24. status = "okay";
  25. compatible = "riscv";
  26. riscv,isa = "rv64imafdcvsu";
  27. mmu-type = "riscv,sv39";
  28. u-boot,dm-pre-reloc;
  29. };
  30. };
  31. soc {
  32. #address-cells = <2>;
  33. #size-cells = <2>;
  34. compatible = "simple-bus";
  35. ranges;
  36. u-boot,dm-pre-reloc;
  37. dummy_apb: apb-clock {
  38. compatible = "fixed-clock";
  39. clock-frequency = <62500000>;
  40. clock-output-names = "dummy_apb";
  41. #clock-cells = <0>;
  42. u-boot,dm-pre-reloc;
  43. };
  44. dummy_ahb: ahb-clock {
  45. compatible = "fixed-clock";
  46. clock-frequency = <250000000>;
  47. clock-output-names = "core";
  48. #clock-cells = <0>;
  49. u-boot,dm-pre-reloc;
  50. };
  51. dummy_spi: spi-clock {
  52. compatible = "fixed-clock";
  53. clock-frequency = <396000000>;
  54. clock-output-names = "dummy_spi";
  55. #clock-cells = <0>;
  56. u-boot,dm-pre-reloc;
  57. };
  58. dummy_qspi0: qspi0-clock {
  59. compatible = "fixed-clock";
  60. clock-frequency = <792000000>;
  61. clock-output-names = "dummy_qspi0";
  62. #clock-cells = <0>;
  63. u-boot,dm-pre-reloc;
  64. };
  65. dummy_uart_sclk: uart-sclk-clock {
  66. compatible = "fixed-clock";
  67. clock-frequency = <100000000>;
  68. clock-output-names = "dummy_uart_sclk";
  69. #clock-cells = <0>;
  70. u-boot,dm-pre-reloc;
  71. };
  72. dummy_i2c_icclk: i2c-icclk-clock {
  73. compatible = "fixed-clock";
  74. clock-frequency = <50000000>;
  75. clock-output-names = "dummy_i2c_icclk";
  76. #clock-cells = <0>;
  77. u-boot,dm-pre-reloc;
  78. };
  79. dummy_dpu_pixclk: dpu-pix-clock {
  80. compatible = "fixed-clock";
  81. clock-frequency = <74250000>;
  82. clock-output-names = "dummy_dpu_pixclk";
  83. #clock-cells = <0>;
  84. u-boot,dm-pre-reloc;
  85. };
  86. dummy_dphy_refclk: dphy-ref-clock {
  87. compatible = "fixed-clock";
  88. clock-frequency = <24000000>;
  89. clock-output-names = "dummy_dpu_refclk";
  90. #clock-cells = <0>;
  91. u-boot,dm-pre-reloc;
  92. };
  93. i2c0: i2c@ffe7f20000 {
  94. compatible = "snps,designware-i2c";
  95. reg = <0xff 0xe7f20000 0x0 0x4000>;
  96. clocks = <&dummy_i2c_icclk>;
  97. clock-frequency = <100000>;
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. };
  101. i2c1: i2c@ffe7f24000{
  102. compatible = "snps,designware-i2c";
  103. reg = <0xff 0xe7f24000 0x0 0x4000>;
  104. clocks = <&dummy_i2c_icclk>;
  105. clock-frequency = <100000>;
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. };
  109. i2c2: i2c@ffec00c000{
  110. compatible = "snps,designware-i2c";
  111. reg = <0xff 0xec00c000 0x0 0x4000>;
  112. clocks = <&dummy_i2c_icclk>;
  113. clock-frequency = <100000>;
  114. #address-cells = <1>;
  115. #size-cells = <0>;
  116. };
  117. i2c3: i2c@ffec014000{
  118. compatible = "snps,designware-i2c";
  119. reg = <0xff 0xec014000 0x0 0x4000>;
  120. clocks = <&dummy_i2c_icclk>;
  121. clock-frequency = <100000>;
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. };
  125. i2c4: i2c@ffe7f28000{
  126. compatible = "snps,designware-i2c";
  127. reg = <0xff 0xe7f28000 0x0 0x4000>;
  128. clocks = <&dummy_i2c_icclk>;
  129. clock-frequency = <100000>;
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. pcal6408ahk_a: gpio@20 {
  133. compatible = "nxp,pca9554";
  134. reg = <0x20>;
  135. gpio-controller;
  136. #gpio-cells = <2>;
  137. };
  138. };
  139. i2c5: i2c@fff7f2c000{
  140. compatible = "snps,designware-i2c";
  141. reg = <0xff 0xf7f2c000 0x0 0x4000>;
  142. clocks = <&dummy_i2c_icclk>;
  143. clock-frequency = <100000>;
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. };
  147. serial@ffe7014000 {
  148. compatible = "snps,dw-apb-uart";
  149. reg = <0xff 0xe7014000 0x0 0x400>;
  150. clocks = <&dummy_uart_sclk>;
  151. clock-frequency = <100000000>;
  152. clock-names = "baudclk";
  153. reg-shift = <2>;
  154. reg-io-width = <4>;
  155. u-boot,dm-pre-reloc;
  156. };
  157. gmac0: ethernet@ffe7070000 {
  158. compatible = "snps,dwmac";
  159. reg = <0xff 0xe7070000 0x0 0x2000>;
  160. clocks = <&dummy_apb>;
  161. clock-names = "stmmaceth";
  162. snps,pbl = <32>;
  163. snps,fixed-burst;
  164. phy-mode = "rgmii-id";
  165. phy-handle = <&phy_88E1111_a>;
  166. status = "okay";
  167. mdio0 {
  168. #address-cells = <1>;
  169. #size-cells = <0>;
  170. compatible = "snps,dwmac-mdio";
  171. phy_88E1111_a: ethernet-phy@1 {
  172. reg = <0x1>;
  173. };
  174. phy_88E1111_b: ethernet-phy@2 {
  175. reg = <0x2>;
  176. };
  177. };
  178. };
  179. gmac1: ethernet@ffe7060000 {
  180. compatible = "snps,dwmac";
  181. reg = <0xff 0xe7060000 0x0 0x2000>;
  182. clocks = <&dummy_apb>;
  183. clock-names = "stmmaceth";
  184. snps,pbl = <32>;
  185. snps,fixed-burst;
  186. phy-mode = "rgmii-id";
  187. phy-handle = <&phy_88E1111_b>;
  188. status = "disabled";
  189. };
  190. emmc: sdhci@ffe7080000 {
  191. compatible = "snps,dwcmshc-sdhci";
  192. reg = <0xff 0xe7080000 0x0 0x10000>;
  193. index = <0x0>;
  194. clocks = <&dummy_ahb>;
  195. clock-frequency = <198000000>;
  196. clock-names = "core";
  197. max-frequency = <198000000>;
  198. sdhci-caps-mask = <0x0 0x1000000>;
  199. mmc-hs400-1_8v;
  200. non-removable;
  201. no-sdio;
  202. no-sd;
  203. bus-width = <8>;
  204. voltage= "1.8v";
  205. pull_up;
  206. io_fixed_1v8;
  207. fifo-mode;
  208. u-boot,dm-pre-reloc;
  209. };
  210. sdhci0: sd@ffe7090000 {
  211. compatible = "snps,dwcmshc-sdhci";
  212. reg = <0xff 0xe7090000 0x0 0x10000>;
  213. index = <0x1>;
  214. clocks = <&dummy_ahb>;
  215. clock-frequency = <198000000>;
  216. max-frequency = <198000000>;
  217. sd-uhs-sdr104;
  218. pull_up;
  219. clock-names = "core";
  220. bus-width = <4>;
  221. voltage= "3.3v";
  222. };
  223. qspi0: spi@ffea000000 {
  224. compatible = "snps,dw-apb-ssi-quad";
  225. reg = <0xff 0xea000000 0x0 0x1000>;
  226. clocks = <&dummy_qspi0>;
  227. num-cs = <1>;
  228. cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
  229. spi-max-frequency = <100000000>;
  230. #address-cells = <1>;
  231. #size-cells =<0>;
  232. status = "disabled";
  233. spi-flash@0 {
  234. #address-cells = <1>;
  235. #size-cells = <1>;
  236. compatible = "spi-nand";
  237. spi-tx-bus-width = <4>;
  238. spi-rx-bus-width = <4>;
  239. reg = <0>;
  240. };
  241. };
  242. qspi1: spi@fff8000000 {
  243. compatible = "snps,dw-apb-ssi-quad";
  244. reg = <0xff 0xf8000000 0x0 0x1000>;
  245. clocks = <&dummy_spi>;
  246. num-cs = <1>;
  247. cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
  248. spi-max-frequency = <66000000>;
  249. #address-cells = <1>;
  250. #size-cells =<0>;
  251. status = "disabled";
  252. spi-flash@0 {
  253. #address-cells = <1>;
  254. #size-cells = <1>;
  255. compatible = "spi-nand";
  256. spi-tx-bus-width = <4>;
  257. spi-rx-bus-width = <4>;
  258. reg = <0>;
  259. };
  260. };
  261. spi0: spi@ffe700c000 {
  262. compatible = "snps,dw-apb-ssi";
  263. reg = <0xff 0xe700c000 0x0 0x1000>;
  264. clocks = <&dummy_spi>;
  265. cs-gpio = <&gpio2_porta 15 0>;
  266. spi-max-frequency = <100000000>;
  267. #address-cells = <1>;
  268. #size-cells = <0>;
  269. status = "disabled";
  270. flash@0 {
  271. compatible = "jedec,spi-nor";
  272. reg = <0>;
  273. spi-max-frequency = <40000000>;
  274. };
  275. };
  276. gpio2: gpio@ffe7f34000 {
  277. compatible = "snps,dw-apb-gpio";
  278. reg = <0xff 0xe7f34000 0x0 0x1000>;
  279. clocks = <&dummy_apb>;
  280. #address-cells = <1>;
  281. #size-cells = <0>;
  282. gpio2_porta: gpio-controller@0 {
  283. compatible = "snps,dw-apb-gpio-port";
  284. gpio-controller;
  285. #gpio-cells = <2>;
  286. snps,nr-gpios = <32>;
  287. reg = <0>;
  288. };
  289. };
  290. gpio0: gpio@ffec005000 {
  291. compatible = "snps,dw-apb-gpio";
  292. reg = <0xff 0xec005000 0x0 0x1000>;
  293. clocks = <&dummy_apb>;
  294. #address-cells = <1>;
  295. #size-cells = <0>;
  296. gpio0_porta: gpio-controller@0 {
  297. compatible = "snps,dw-apb-gpio-port";
  298. gpio-controller;
  299. #gpio-cells = <2>;
  300. snps,nr-gpios = <32>;
  301. reg = <0>;
  302. };
  303. };
  304. gpio1: gpio@ffec006000 {
  305. compatible = "snps,dw-apb-gpio";
  306. reg = <0xff 0xec006000 0x0 0x1000>;
  307. clocks = <&dummy_apb>;
  308. #address-cells = <1>;
  309. #size-cells = <0>;
  310. gpio1_porta: gpio-controller@0 {
  311. compatible = "snps,dw-apb-gpio-port";
  312. gpio-controller;
  313. #gpio-cells = <2>;
  314. snps,nr-gpios = <32>;
  315. reg = <0>;
  316. };
  317. };
  318. pwm: pwm@ffec01c000 {
  319. compatible = "thead,pwm-light";
  320. reg = <0xff 0xec01c000 0x0 0x4000>;
  321. #pwm-cells = <2>;
  322. };
  323. dsi_regs: dsi-controller@ffef500000 {
  324. compatible = "thead,light-dsi-regs", "syscon";
  325. reg = <0xff 0xef500000 0x0 0x10000>;
  326. status = "okay";
  327. };
  328. vosys_regs: vosys@ffef528000 {
  329. compatible = "thead,light-vo-subsys", "syscon";
  330. reg = <0xff 0xef528000 0x0 0x1000>;
  331. status = "okay";
  332. };
  333. dpu: dc8200@ffef600000 {
  334. compatible = "verisilicon,dc8200";
  335. reg = <0xff 0xef600000 0x0 0x100>;
  336. };
  337. axiscr {
  338. compatible = "thead,axiscr";
  339. reg = <0xff 0xff004000 0x0 0x1000>;
  340. lock-read = "okay";
  341. lock-write = "okay";
  342. #address-cells = <2>;
  343. #size-cells = <2>;
  344. u-boot,dm-pre-reloc;
  345. axiscr0: axisrc@0 {
  346. device_type = "axiscr";
  347. region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
  348. status = "disabled";
  349. #address-cells = <2>;
  350. #size-cells = <2>;
  351. u-boot,dm-pre-reloc;
  352. };
  353. axiscr1: axisrc@1 {
  354. device_type = "axiscr";
  355. region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
  356. status = "disabled";
  357. #address-cells = <2>;
  358. #size-cells = <2>;
  359. u-boot,dm-pre-reloc;
  360. };
  361. axiscr2: axisrc@2 {
  362. device_type = "axiscr";
  363. region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
  364. status = "disabled";
  365. #address-cells = <2>;
  366. #size-cells = <2>;
  367. u-boot,dm-pre-reloc;
  368. };
  369. };
  370. axiparity {
  371. compatible = "thead,axiparity";
  372. reg = <0xff 0xff00c000 0x0 0x1000>;
  373. lock = "okay";
  374. #address-cells = <2>;
  375. #size-cells = <2>;
  376. u-boot,dm-pre-reloc;
  377. axiparity0: axiparity@0 {
  378. device_type = "axiparity";
  379. region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
  380. status = "disabled";
  381. #address-cells = <2>;
  382. #size-cells = <2>;
  383. u-boot,dm-pre-reloc;
  384. };
  385. axiparity1: axiparity@1 {
  386. device_type = "axiparity";
  387. region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
  388. status = "disabled";
  389. #address-cells = <2>;
  390. #size-cells = <2>;
  391. u-boot,dm-pre-reloc;
  392. };
  393. };
  394. dsi_bridge: dsi-bridge {
  395. compatible = "thead,light-dsi-bridge";
  396. clocks = <&dummy_dpu_pixclk>;
  397. clock-names = "pix-clk";
  398. phys = <&dsi_dphy>;
  399. phy-names = "dphy";
  400. };
  401. dsi_host: dsi-host {
  402. compatible = "synopsys,dw-mipi-dsi";
  403. regmap = <&dsi_regs>;
  404. status = "okay";
  405. };
  406. dsi_dphy: dsi-dphy {
  407. compatible = "synopsys,dw-dphy";
  408. regmap = <&dsi_regs>;
  409. vosys-regmap = <&vosys_regs>;
  410. clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
  411. clock-names = "pix-clk", "ref-clk";
  412. #phy-cells = <0>;
  413. status = "okay";
  414. };
  415. lcd_backlight: pwm-backlight {
  416. compatible = "pwm-backlight";
  417. pwms = <&pwm 0 5000000>;
  418. brightness-levels = <0 4 8 16 32 64 128 255>;
  419. default-brightness-level = <7>;
  420. };
  421. ili9881c_panel {
  422. compatible = "ilitek,ili9881c";
  423. backlight = <&lcd_backlight>;
  424. reset-gpios = <&gpio1_porta 5 1>; /* active low */
  425. lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
  426. lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
  427. };
  428. };
  429. chosen {
  430. bootargs = "console=ttyS0,115200";
  431. stdout-path = "/soc/serial@ffe7014000:115200";
  432. };
  433. };