light-a-product.dts 9.2 KB

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  1. /dts-v1/;
  2. / {
  3. model = "T-HEAD c910 light";
  4. compatible = "thead,c910_light";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. memory@0 {
  8. device_type = "memory";
  9. reg = <0x0 0xc0000000 0x0 0x40000000>;
  10. };
  11. aliases {
  12. };
  13. cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. timebase-frequency = <3000000>;
  17. u-boot,dm-pre-reloc;
  18. cpu@0 {
  19. device_type = "cpu";
  20. reg = <0>;
  21. status = "okay";
  22. compatible = "riscv";
  23. riscv,isa = "rv64imafdcvsu";
  24. mmu-type = "riscv,sv39";
  25. u-boot,dm-pre-reloc;
  26. };
  27. };
  28. soc {
  29. #address-cells = <2>;
  30. #size-cells = <2>;
  31. compatible = "simple-bus";
  32. ranges;
  33. u-boot,dm-pre-reloc;
  34. dummy_apb: apb-clock {
  35. compatible = "fixed-clock";
  36. clock-frequency = <62500000>;
  37. clock-output-names = "dummy_apb";
  38. #clock-cells = <0>;
  39. u-boot,dm-pre-reloc;
  40. };
  41. dummy_ahb: ahb-clock {
  42. compatible = "fixed-clock";
  43. clock-frequency = <250000000>;
  44. clock-output-names = "core";
  45. #clock-cells = <0>;
  46. u-boot,dm-pre-reloc;
  47. };
  48. dummy_spi: spi-clock {
  49. compatible = "fixed-clock";
  50. clock-frequency = <396000000>;
  51. clock-output-names = "dummy_spi";
  52. #clock-cells = <0>;
  53. u-boot,dm-pre-reloc;
  54. };
  55. dummy_qspi0: qspi0-clock {
  56. compatible = "fixed-clock";
  57. clock-frequency = <792000000>;
  58. clock-output-names = "dummy_qspi0";
  59. #clock-cells = <0>;
  60. u-boot,dm-pre-reloc;
  61. };
  62. dummy_uart_sclk: uart-sclk-clock {
  63. compatible = "fixed-clock";
  64. clock-frequency = <100000000>;
  65. clock-output-names = "dummy_uart_sclk";
  66. #clock-cells = <0>;
  67. u-boot,dm-pre-reloc;
  68. };
  69. dummy_i2c_icclk: i2c-icclk-clock {
  70. compatible = "fixed-clock";
  71. clock-frequency = <50000000>;
  72. clock-output-names = "dummy_i2c_icclk";
  73. #clock-cells = <0>;
  74. u-boot,dm-pre-reloc;
  75. };
  76. dummy_dpu_pixclk: dpu-pix-clock {
  77. compatible = "fixed-clock";
  78. clock-frequency = <74250000>;
  79. clock-output-names = "dummy_dpu_pixclk";
  80. #clock-cells = <0>;
  81. u-boot,dm-pre-reloc;
  82. };
  83. dummy_dphy_refclk: dphy-ref-clock {
  84. compatible = "fixed-clock";
  85. clock-frequency = <24000000>;
  86. clock-output-names = "dummy_dpu_refclk";
  87. #clock-cells = <0>;
  88. u-boot,dm-pre-reloc;
  89. };
  90. i2c0: i2c@ffe7f20000 {
  91. compatible = "snps,designware-i2c";
  92. reg = <0xff 0xe7f20000 0x0 0x4000>;
  93. clocks = <&dummy_i2c_icclk>;
  94. clock-frequency = <100000>;
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. };
  98. i2c1: i2c@ffe7f24000{
  99. compatible = "snps,designware-i2c";
  100. reg = <0xff 0xe7f24000 0x0 0x4000>;
  101. clocks = <&dummy_i2c_icclk>;
  102. clock-frequency = <100000>;
  103. #address-cells = <1>;
  104. #size-cells = <0>;
  105. };
  106. i2c2: i2c@ffec00c000{
  107. compatible = "snps,designware-i2c";
  108. reg = <0xff 0xec00c000 0x0 0x4000>;
  109. clocks = <&dummy_i2c_icclk>;
  110. clock-frequency = <100000>;
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. };
  114. i2c3: i2c@ffec014000{
  115. compatible = "snps,designware-i2c";
  116. reg = <0xff 0xec014000 0x0 0x4000>;
  117. clocks = <&dummy_i2c_icclk>;
  118. clock-frequency = <100000>;
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. };
  122. i2c4: i2c@ffe7f28000{
  123. compatible = "snps,designware-i2c";
  124. reg = <0xff 0xe7f28000 0x0 0x4000>;
  125. clocks = <&dummy_i2c_icclk>;
  126. clock-frequency = <100000>;
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. pcal6408ahk_a: gpio@20 {
  130. compatible = "nxp,pca9554";
  131. reg = <0x20>;
  132. gpio-controller;
  133. #gpio-cells = <2>;
  134. };
  135. };
  136. serial@ffe7014000 {
  137. compatible = "snps,dw-apb-uart";
  138. reg = <0xff 0xe7014000 0x0 0x400>;
  139. clocks = <&dummy_uart_sclk>;
  140. clock-frequency = <100000000>;
  141. clock-names = "baudclk";
  142. reg-shift = <2>;
  143. reg-io-width = <4>;
  144. u-boot,dm-pre-reloc;
  145. };
  146. gmac0: ethernet@ffe7070000 {
  147. compatible = "snps,dwmac";
  148. reg = <0xff 0xe7070000 0x0 0x2000>;
  149. clocks = <&dummy_apb>;
  150. clock-names = "stmmaceth";
  151. snps,pbl = <32>;
  152. snps,fixed-burst;
  153. phy-mode = "rgmii-id";
  154. phy-handle = <&phy_88E1111_a>;
  155. status = "okay";
  156. mdio0 {
  157. #address-cells = <1>;
  158. #size-cells = <0>;
  159. compatible = "snps,dwmac-mdio";
  160. phy_88E1111_a: ethernet-phy@1 {
  161. reg = <0x1>;
  162. };
  163. phy_88E1111_b: ethernet-phy@2 {
  164. reg = <0x2>;
  165. };
  166. };
  167. };
  168. gmac1: ethernet@ffe7060000 {
  169. compatible = "snps,dwmac";
  170. reg = <0xff 0xe7060000 0x0 0x2000>;
  171. clocks = <&dummy_apb>;
  172. clock-names = "stmmaceth";
  173. snps,pbl = <32>;
  174. snps,fixed-burst;
  175. phy-mode = "rgmii-id";
  176. phy-handle = <&phy_88E1111_b>;
  177. status = "disabled";
  178. };
  179. emmc: sdhci@ffe7080000 {
  180. compatible = "snps,dwcmshc-sdhci";
  181. reg = <0xff 0xe7080000 0x0 0x10000>;
  182. index = <0x0>;
  183. clocks = <&dummy_ahb>;
  184. clock-frequency = <198000000>;
  185. clock-names = "core";
  186. max-frequency = <198000000>;
  187. sdhci-caps-mask = <0x0 0x1000000>;
  188. mmc-hs400-1_8v;
  189. non-removable;
  190. no-sdio;
  191. no-sd;
  192. bus-width = <8>;
  193. voltage= "1.8v";
  194. pull_up;
  195. io_fixed_1v8;
  196. fifo-mode;
  197. u-boot,dm-pre-reloc;
  198. };
  199. sdhci0: sd@ffe7090000 {
  200. compatible = "snps,dwcmshc-sdhci";
  201. reg = <0xff 0xe7090000 0x0 0x10000>;
  202. index = <0x1>;
  203. clocks = <&dummy_ahb>;
  204. clock-frequency = <198000000>;
  205. max-frequency = <198000000>;
  206. sd-uhs-sdr104;
  207. pull_up;
  208. clock-names = "core";
  209. bus-width = <4>;
  210. voltage= "3.3v";
  211. };
  212. gpio2: gpio@ffe7f34000 {
  213. compatible = "snps,dw-apb-gpio";
  214. reg = <0xff 0xe7f34000 0x0 0x1000>;
  215. clocks = <&dummy_apb>;
  216. #address-cells = <1>;
  217. #size-cells = <0>;
  218. gpio2_porta: gpio-controller@0 {
  219. compatible = "snps,dw-apb-gpio-port";
  220. gpio-controller;
  221. #gpio-cells = <2>;
  222. snps,nr-gpios = <32>;
  223. reg = <0>;
  224. };
  225. };
  226. gpio0: gpio@ffec005000 {
  227. compatible = "snps,dw-apb-gpio";
  228. reg = <0xff 0xec005000 0x0 0x1000>;
  229. clocks = <&dummy_apb>;
  230. #address-cells = <1>;
  231. #size-cells = <0>;
  232. gpio0_porta: gpio-controller@0 {
  233. compatible = "snps,dw-apb-gpio-port";
  234. gpio-controller;
  235. #gpio-cells = <2>;
  236. snps,nr-gpios = <32>;
  237. reg = <0>;
  238. };
  239. };
  240. gpio1: gpio@ffec006000 {
  241. compatible = "snps,dw-apb-gpio";
  242. reg = <0xff 0xec006000 0x0 0x1000>;
  243. clocks = <&dummy_apb>;
  244. #address-cells = <1>;
  245. #size-cells = <0>;
  246. gpio1_porta: gpio-controller@0 {
  247. compatible = "snps,dw-apb-gpio-port";
  248. gpio-controller;
  249. #gpio-cells = <2>;
  250. snps,nr-gpios = <32>;
  251. reg = <0>;
  252. };
  253. };
  254. pwm: pwm@ffec01c000 {
  255. compatible = "thead,pwm-light";
  256. reg = <0xff 0xec01c000 0x0 0x4000>;
  257. #pwm-cells = <2>;
  258. };
  259. dsi_regs: dsi-controller@ffef500000 {
  260. compatible = "thead,light-dsi-regs", "syscon";
  261. reg = <0xff 0xef500000 0x0 0x10000>;
  262. status = "okay";
  263. };
  264. vosys_regs: vosys@ffef528000 {
  265. compatible = "thead,light-vo-subsys", "syscon";
  266. reg = <0xff 0xef528000 0x0 0x1000>;
  267. status = "okay";
  268. };
  269. dpu: dc8200@ffef600000 {
  270. compatible = "verisilicon,dc8200";
  271. reg = <0xff 0xef600000 0x0 0x100>;
  272. };
  273. axiscr {
  274. compatible = "thead,axiscr";
  275. reg = <0xff 0xff004000 0x0 0x1000>;
  276. lock-read = "okay";
  277. lock-write = "okay";
  278. #address-cells = <2>;
  279. #size-cells = <2>;
  280. u-boot,dm-pre-reloc;
  281. axiscr0: axisrc@0 {
  282. device_type = "axiscr";
  283. region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
  284. status = "disabled";
  285. #address-cells = <2>;
  286. #size-cells = <2>;
  287. u-boot,dm-pre-reloc;
  288. };
  289. axiscr1: axisrc@1 {
  290. device_type = "axiscr";
  291. region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
  292. status = "disabled";
  293. #address-cells = <2>;
  294. #size-cells = <2>;
  295. u-boot,dm-pre-reloc;
  296. };
  297. axiscr2: axisrc@2 {
  298. device_type = "axiscr";
  299. region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
  300. status = "disabled";
  301. #address-cells = <2>;
  302. #size-cells = <2>;
  303. u-boot,dm-pre-reloc;
  304. };
  305. };
  306. axiparity {
  307. compatible = "thead,axiparity";
  308. reg = <0xff 0xff00c000 0x0 0x1000>;
  309. lock = "okay";
  310. #address-cells = <2>;
  311. #size-cells = <2>;
  312. u-boot,dm-pre-reloc;
  313. axiparity0: axiparity@0 {
  314. device_type = "axiparity";
  315. region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
  316. status = "disabled";
  317. #address-cells = <2>;
  318. #size-cells = <2>;
  319. u-boot,dm-pre-reloc;
  320. };
  321. axiparity1: axiparity@1 {
  322. device_type = "axiparity";
  323. region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
  324. status = "disabled";
  325. #address-cells = <2>;
  326. #size-cells = <2>;
  327. u-boot,dm-pre-reloc;
  328. };
  329. };
  330. dsi_bridge: dsi-bridge {
  331. compatible = "thead,light-dsi-bridge";
  332. clocks = <&dummy_dpu_pixclk>;
  333. clock-names = "pix-clk";
  334. phys = <&dsi_dphy>;
  335. phy-names = "dphy";
  336. };
  337. dsi_host: dsi-host {
  338. compatible = "synopsys,dw-mipi-dsi";
  339. regmap = <&dsi_regs>;
  340. status = "okay";
  341. };
  342. dsi_dphy: dsi-dphy {
  343. compatible = "synopsys,dw-dphy";
  344. regmap = <&dsi_regs>;
  345. vosys-regmap = <&vosys_regs>;
  346. clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
  347. clock-names = "pix-clk", "ref-clk";
  348. #phy-cells = <0>;
  349. status = "okay";
  350. };
  351. lcd_backlight: pwm-backlight {
  352. compatible = "pwm-backlight";
  353. pwms = <&pwm 1 5000000>;
  354. brightness-levels = <0 4 8 16 32 64 128 255>;
  355. default-brightness-level = <7>;
  356. };
  357. ili9881c_panel {
  358. compatible = "ilitek,ili9881c";
  359. backlight = <&lcd_backlight>;
  360. reset-gpios = <&gpio1_porta 10 1>; /* active low */
  361. lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
  362. lcd-bias-en-gpios = <&gpio1_porta 8 0>;/* active high */
  363. };
  364. };
  365. chosen {
  366. bootargs = "console=ttyS0,115200";
  367. stdout-path = "/soc/serial@ffe7014000:115200";
  368. };
  369. };