hifive-unleashed-a00.dts 1.5 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2018-2019 SiFive, Inc */
  3. #include "fu540-c000.dtsi"
  4. /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
  5. #define RTCCLK_FREQ 1000000
  6. / {
  7. #address-cells = <2>;
  8. #size-cells = <2>;
  9. model = "SiFive HiFive Unleashed A00";
  10. compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
  11. chosen {
  12. stdout-path = "serial0";
  13. };
  14. cpus {
  15. timebase-frequency = <RTCCLK_FREQ>;
  16. };
  17. memory@80000000 {
  18. device_type = "memory";
  19. reg = <0x0 0x80000000 0x2 0x00000000>;
  20. };
  21. soc {
  22. };
  23. hfclk: hfclk {
  24. #clock-cells = <0>;
  25. compatible = "fixed-clock";
  26. clock-frequency = <33333333>;
  27. clock-output-names = "hfclk";
  28. };
  29. rtcclk: rtcclk {
  30. #clock-cells = <0>;
  31. compatible = "fixed-clock";
  32. clock-frequency = <RTCCLK_FREQ>;
  33. clock-output-names = "rtcclk";
  34. };
  35. };
  36. &uart0 {
  37. status = "okay";
  38. };
  39. &uart1 {
  40. status = "okay";
  41. };
  42. &i2c0 {
  43. status = "okay";
  44. };
  45. &qspi0 {
  46. status = "okay";
  47. flash@0 {
  48. compatible = "issi,is25wp256", "jedec,spi-nor";
  49. reg = <0>;
  50. spi-max-frequency = <50000000>;
  51. m25p,fast-read;
  52. spi-tx-bus-width = <4>;
  53. spi-rx-bus-width = <4>;
  54. };
  55. };
  56. &qspi2 {
  57. status = "okay";
  58. mmc@0 {
  59. compatible = "mmc-spi-slot";
  60. reg = <0>;
  61. spi-max-frequency = <20000000>;
  62. voltage-ranges = <3300 3300>;
  63. disable-wp;
  64. };
  65. };
  66. &eth0 {
  67. status = "okay";
  68. phy-mode = "gmii";
  69. phy-handle = <&phy0>;
  70. phy0: ethernet-phy@0 {
  71. reg = <0>;
  72. };
  73. };
  74. &pwm0 {
  75. status = "okay";
  76. };
  77. &pwm1 {
  78. status = "okay";
  79. };