ae350_64.dts 7.1 KB

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  1. /dts-v1/;
  2. / {
  3. #address-cells = <2>;
  4. #size-cells = <2>;
  5. compatible = "andestech,ax25";
  6. model = "andestech,ax25";
  7. aliases {
  8. uart0 = &serial0;
  9. spi0 = &spi;
  10. };
  11. chosen {
  12. bootargs = "console=ttyS0,38400n8 debug loglevel=7";
  13. stdout-path = "uart0:38400n8";
  14. };
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. timebase-frequency = <60000000>;
  19. CPU0: cpu@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. status = "okay";
  23. compatible = "riscv";
  24. riscv,isa = "rv64imafdc";
  25. riscv,priv-major = <1>;
  26. riscv,priv-minor = <10>;
  27. mmu-type = "riscv,sv39";
  28. clock-frequency = <60000000>;
  29. i-cache-size = <0x8000>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <0x8000>;
  32. d-cache-line-size = <32>;
  33. next-level-cache = <&L2>;
  34. CPU0_intc: interrupt-controller {
  35. #interrupt-cells = <1>;
  36. interrupt-controller;
  37. compatible = "riscv,cpu-intc";
  38. };
  39. };
  40. CPU1: cpu@1 {
  41. device_type = "cpu";
  42. reg = <1>;
  43. status = "okay";
  44. compatible = "riscv";
  45. riscv,isa = "rv64imafdc";
  46. riscv,priv-major = <1>;
  47. riscv,priv-minor = <10>;
  48. mmu-type = "riscv,sv39";
  49. clock-frequency = <60000000>;
  50. i-cache-size = <0x8000>;
  51. i-cache-line-size = <32>;
  52. d-cache-size = <0x8000>;
  53. d-cache-line-size = <32>;
  54. next-level-cache = <&L2>;
  55. CPU1_intc: interrupt-controller {
  56. #interrupt-cells = <1>;
  57. interrupt-controller;
  58. compatible = "riscv,cpu-intc";
  59. };
  60. };
  61. CPU2: cpu@2 {
  62. device_type = "cpu";
  63. reg = <2>;
  64. status = "okay";
  65. compatible = "riscv";
  66. riscv,isa = "rv64imafdc";
  67. riscv,priv-major = <1>;
  68. riscv,priv-minor = <10>;
  69. mmu-type = "riscv,sv39";
  70. clock-frequency = <60000000>;
  71. i-cache-size = <0x8000>;
  72. i-cache-line-size = <32>;
  73. d-cache-size = <0x8000>;
  74. d-cache-line-size = <32>;
  75. next-level-cache = <&L2>;
  76. CPU2_intc: interrupt-controller {
  77. #interrupt-cells = <1>;
  78. interrupt-controller;
  79. compatible = "riscv,cpu-intc";
  80. };
  81. };
  82. CPU3: cpu@3 {
  83. device_type = "cpu";
  84. reg = <3>;
  85. status = "okay";
  86. compatible = "riscv";
  87. riscv,isa = "rv64imafdc";
  88. riscv,priv-major = <1>;
  89. riscv,priv-minor = <10>;
  90. mmu-type = "riscv,sv39";
  91. clock-frequency = <60000000>;
  92. i-cache-size = <0x8000>;
  93. i-cache-line-size = <32>;
  94. d-cache-size = <0x8000>;
  95. d-cache-line-size = <32>;
  96. next-level-cache = <&L2>;
  97. CPU3_intc: interrupt-controller {
  98. #interrupt-cells = <1>;
  99. interrupt-controller;
  100. compatible = "riscv,cpu-intc";
  101. };
  102. };
  103. };
  104. L2: l2-cache@e0500000 {
  105. compatible = "v5l2cache";
  106. cache-level = <2>;
  107. cache-size = <0x40000>;
  108. reg = <0x0 0xe0500000 0x0 0x40000>;
  109. andes,inst-prefetch = <3>;
  110. andes,data-prefetch = <3>;
  111. /* The value format is <XRAMOCTL XRAMICTL> */
  112. andes,tag-ram-ctl = <0 0>;
  113. andes,data-ram-ctl = <0 0>;
  114. };
  115. memory@0 {
  116. device_type = "memory";
  117. reg = <0x0 0x00000000 0x0 0x40000000>;
  118. };
  119. soc {
  120. #address-cells = <2>;
  121. #size-cells = <2>;
  122. compatible = "simple-bus";
  123. ranges;
  124. plic0: interrupt-controller@e4000000 {
  125. compatible = "riscv,plic0";
  126. #address-cells = <2>;
  127. #interrupt-cells = <2>;
  128. interrupt-controller;
  129. reg = <0x0 0xe4000000 0x0 0x2000000>;
  130. riscv,ndev=<71>;
  131. interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
  132. &CPU1_intc 11 &CPU1_intc 9
  133. &CPU2_intc 11 &CPU2_intc 9
  134. &CPU3_intc 11 &CPU3_intc 9>;
  135. };
  136. plic1: interrupt-controller@e6400000 {
  137. compatible = "riscv,plic1";
  138. #address-cells = <2>;
  139. #interrupt-cells = <2>;
  140. interrupt-controller;
  141. reg = <0x0 0xe6400000 0x0 0x400000>;
  142. riscv,ndev=<2>;
  143. interrupts-extended = <&CPU0_intc 3
  144. &CPU1_intc 3
  145. &CPU2_intc 3
  146. &CPU3_intc 3>;
  147. };
  148. plmt0@e6000000 {
  149. compatible = "riscv,plmt0";
  150. interrupts-extended = <&CPU0_intc 7
  151. &CPU1_intc 7
  152. &CPU2_intc 7
  153. &CPU3_intc 7>;
  154. reg = <0x0 0xe6000000 0x0 0x100000>;
  155. };
  156. };
  157. spiclk: virt_100mhz {
  158. #clock-cells = <0>;
  159. compatible = "fixed-clock";
  160. clock-frequency = <100000000>;
  161. };
  162. timer0: timer@f0400000 {
  163. compatible = "andestech,atcpit100";
  164. reg = <0x0 0xf0400000 0x0 0x1000>;
  165. clock-frequency = <60000000>;
  166. interrupts = <3 4>;
  167. interrupt-parent = <&plic0>;
  168. };
  169. serial0: serial@f0300000 {
  170. compatible = "andestech,uart16550", "ns16550a";
  171. reg = <0x0 0xf0300000 0x0 0x1000>;
  172. interrupts = <9 4>;
  173. clock-frequency = <19660800>;
  174. reg-shift = <2>;
  175. reg-offset = <32>;
  176. no-loopback-test = <1>;
  177. interrupt-parent = <&plic0>;
  178. };
  179. mac0: mac@e0100000 {
  180. compatible = "andestech,atmac100";
  181. reg = <0x0 0xe0100000 0x0 0x1000>;
  182. interrupts = <19 4>;
  183. interrupt-parent = <&plic0>;
  184. };
  185. mmc0: mmc@f0e00000 {
  186. compatible = "andestech,atfsdc010";
  187. max-frequency = <100000000>;
  188. clock-freq-min-max = <400000 100000000>;
  189. fifo-depth = <0x10>;
  190. reg = <0x0 0xf0e00000 0x0 0x1000>;
  191. interrupts = <18 4>;
  192. cap-sd-highspeed;
  193. interrupt-parent = <&plic0>;
  194. };
  195. dma0: dma@f0c00000 {
  196. compatible = "andestech,atcdmac300";
  197. reg = <0x0 0xf0c00000 0x0 0x1000>;
  198. interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
  199. dma-channels = <8>;
  200. interrupt-parent = <&plic0>;
  201. };
  202. lcd0: lcd@e0200000 {
  203. compatible = "andestech,atflcdc100";
  204. reg = <0x0 0xe0200000 0x0 0x1000>;
  205. interrupts = <20 4>;
  206. interrupt-parent = <&plic0>;
  207. };
  208. smc0: smc@e0400000 {
  209. compatible = "andestech,atfsmc020";
  210. reg = <0x0 0xe0400000 0x0 0x1000>;
  211. };
  212. snd0: snd@f0d00000 {
  213. compatible = "andestech,atfac97";
  214. reg = <0x0 0xf0d00000 0x0 0x1000>;
  215. interrupts = <17 4>;
  216. interrupt-parent = <&plic0>;
  217. };
  218. pmu {
  219. compatible = "riscv,base-pmu";
  220. };
  221. virtio_mmio@fe007000 {
  222. interrupts = <0x17 0x4>;
  223. interrupt-parent = <0x2>;
  224. reg = <0x0 0xfe007000 0x0 0x1000>;
  225. compatible = "virtio,mmio";
  226. };
  227. virtio_mmio@fe006000 {
  228. interrupts = <0x16 0x4>;
  229. interrupt-parent = <0x2>;
  230. reg = <0x0 0xfe006000 0x0 0x1000>;
  231. compatible = "virtio,mmio";
  232. };
  233. virtio_mmio@fe005000 {
  234. interrupts = <0x15 0x4>;
  235. interrupt-parent = <0x2>;
  236. reg = <0x0 0xfe005000 0x0 0x1000>;
  237. compatible = "virtio,mmio";
  238. };
  239. virtio_mmio@fe004000 {
  240. interrupts = <0x14 0x4>;
  241. interrupt-parent = <0x2>;
  242. reg = <0x0 0xfe004000 0x0 0x1000>;
  243. compatible = "virtio,mmio";
  244. };
  245. virtio_mmio@fe003000 {
  246. interrupts = <0x13 0x4>;
  247. interrupt-parent = <0x2>;
  248. reg = <0x0 0xfe003000 0x0 0x1000>;
  249. compatible = "virtio,mmio";
  250. };
  251. virtio_mmio@fe002000 {
  252. interrupts = <0x12 0x4>;
  253. interrupt-parent = <0x2>;
  254. reg = <0x0 0xfe002000 0x0 0x1000>;
  255. compatible = "virtio,mmio";
  256. };
  257. virtio_mmio@fe001000 {
  258. interrupts = <0x11 0x4>;
  259. interrupt-parent = <0x2>;
  260. reg = <0x0 0xfe001000 0x0 0x1000>;
  261. compatible = "virtio,mmio";
  262. };
  263. virtio_mmio@fe000000 {
  264. interrupts = <0x10 0x4>;
  265. interrupt-parent = <0x2>;
  266. reg = <0x0 0xfe000000 0x0 0x1000>;
  267. compatible = "virtio,mmio";
  268. };
  269. nor@0,0 {
  270. #address-cells = <2>;
  271. #size-cells = <2>;
  272. compatible = "cfi-flash";
  273. reg = <0x0 0x88000000 0x0 0x4000000>;
  274. bank-width = <2>;
  275. device-width = <1>;
  276. };
  277. spi: spi@f0b00000 {
  278. compatible = "andestech,atcspi200";
  279. reg = <0x0 0xf0b00000 0x0 0x1000>;
  280. #address-cells = <1>;
  281. #size-cells = <0>;
  282. num-cs = <1>;
  283. clocks = <&spiclk>;
  284. interrupts = <4 4>;
  285. interrupt-parent = <&plic0>;
  286. flash@0 {
  287. compatible = "jedec,spi-nor";
  288. spi-max-frequency = <50000000>;
  289. reg = <0>;
  290. spi-cpol;
  291. spi-cpha;
  292. };
  293. };
  294. };