mtrap.S 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * M-mode Trap Handler Code for RISC-V Core
  4. *
  5. * Copyright (c) 2017 Microsemi Corporation.
  6. * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
  7. *
  8. * Copyright (C) 2017 Andes Technology Corporation
  9. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  10. *
  11. * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  12. */
  13. #include <common.h>
  14. #include <asm/encoding.h>
  15. #ifdef CONFIG_32BIT
  16. #define LREG lw
  17. #define SREG sw
  18. #define REGBYTES 4
  19. #else
  20. #define LREG ld
  21. #define SREG sd
  22. #define REGBYTES 8
  23. #endif
  24. .text
  25. /* trap entry */
  26. .align 2
  27. .global trap_entry
  28. trap_entry:
  29. #ifndef CONFIG_THEAD_PLIC
  30. ebreak
  31. #endif
  32. addi sp, sp, -32 * REGBYTES
  33. SREG x1, 1 * REGBYTES(sp)
  34. SREG x2, 2 * REGBYTES(sp)
  35. SREG x3, 3 * REGBYTES(sp)
  36. SREG x4, 4 * REGBYTES(sp)
  37. SREG x5, 5 * REGBYTES(sp)
  38. SREG x6, 6 * REGBYTES(sp)
  39. SREG x7, 7 * REGBYTES(sp)
  40. SREG x8, 8 * REGBYTES(sp)
  41. SREG x9, 9 * REGBYTES(sp)
  42. SREG x10, 10 * REGBYTES(sp)
  43. SREG x11, 11 * REGBYTES(sp)
  44. SREG x12, 12 * REGBYTES(sp)
  45. SREG x13, 13 * REGBYTES(sp)
  46. SREG x14, 14 * REGBYTES(sp)
  47. SREG x15, 15 * REGBYTES(sp)
  48. SREG x16, 16 * REGBYTES(sp)
  49. SREG x17, 17 * REGBYTES(sp)
  50. SREG x18, 18 * REGBYTES(sp)
  51. SREG x19, 19 * REGBYTES(sp)
  52. SREG x20, 20 * REGBYTES(sp)
  53. SREG x21, 21 * REGBYTES(sp)
  54. SREG x22, 22 * REGBYTES(sp)
  55. SREG x23, 23 * REGBYTES(sp)
  56. SREG x24, 24 * REGBYTES(sp)
  57. SREG x25, 25 * REGBYTES(sp)
  58. SREG x26, 26 * REGBYTES(sp)
  59. SREG x27, 27 * REGBYTES(sp)
  60. SREG x28, 28 * REGBYTES(sp)
  61. SREG x29, 29 * REGBYTES(sp)
  62. SREG x30, 30 * REGBYTES(sp)
  63. SREG x31, 31 * REGBYTES(sp)
  64. csrr a0, MODE_PREFIX(cause)
  65. csrr a1, MODE_PREFIX(epc)
  66. mv a2, sp
  67. jal handle_trap
  68. csrw MODE_PREFIX(epc), a0
  69. LREG x1, 1 * REGBYTES(sp)
  70. LREG x3, 3 * REGBYTES(sp)
  71. LREG x4, 4 * REGBYTES(sp)
  72. LREG x5, 5 * REGBYTES(sp)
  73. LREG x6, 6 * REGBYTES(sp)
  74. LREG x7, 7 * REGBYTES(sp)
  75. LREG x8, 8 * REGBYTES(sp)
  76. LREG x9, 9 * REGBYTES(sp)
  77. LREG x10, 10 * REGBYTES(sp)
  78. LREG x11, 11 * REGBYTES(sp)
  79. LREG x12, 12 * REGBYTES(sp)
  80. LREG x13, 13 * REGBYTES(sp)
  81. LREG x14, 14 * REGBYTES(sp)
  82. LREG x15, 15 * REGBYTES(sp)
  83. LREG x16, 16 * REGBYTES(sp)
  84. LREG x17, 17 * REGBYTES(sp)
  85. LREG x18, 18 * REGBYTES(sp)
  86. LREG x19, 19 * REGBYTES(sp)
  87. LREG x20, 20 * REGBYTES(sp)
  88. LREG x21, 21 * REGBYTES(sp)
  89. LREG x22, 22 * REGBYTES(sp)
  90. LREG x23, 23 * REGBYTES(sp)
  91. LREG x24, 24 * REGBYTES(sp)
  92. LREG x25, 25 * REGBYTES(sp)
  93. LREG x26, 26 * REGBYTES(sp)
  94. LREG x27, 27 * REGBYTES(sp)
  95. LREG x28, 28 * REGBYTES(sp)
  96. LREG x29, 29 * REGBYTES(sp)
  97. LREG x30, 30 * REGBYTES(sp)
  98. LREG x31, 31 * REGBYTES(sp)
  99. LREG x2, 2 * REGBYTES(sp)
  100. addi sp, sp, 32 * REGBYTES
  101. MODE_PREFIX(ret)