cpu.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <cpu.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <asm/encoding.h>
  10. #include <dm/uclass-internal.h>
  11. /*
  12. * The variables here must be stored in the data section since they are used
  13. * before the bss section is available.
  14. */
  15. #ifdef CONFIG_OF_PRIOR_STAGE
  16. phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
  17. #endif
  18. #ifndef CONFIG_XIP
  19. u32 hart_lottery __attribute__((section(".data"))) = 0;
  20. /*
  21. * The main hart running U-Boot has acquired available_harts_lock until it has
  22. * finished initialization of global data.
  23. */
  24. u32 available_harts_lock = 1;
  25. #endif
  26. static inline bool supports_extension(char ext)
  27. {
  28. #ifdef CONFIG_CPU
  29. struct udevice *dev;
  30. char desc[32];
  31. uclass_find_first_device(UCLASS_CPU, &dev);
  32. if (!dev) {
  33. debug("unable to find the RISC-V cpu device\n");
  34. return false;
  35. }
  36. if (!cpu_get_desc(dev, desc, sizeof(desc))) {
  37. /* skip the first 4 characters (rv32|rv64) */
  38. if (strchr(desc + 4, ext))
  39. return true;
  40. }
  41. return false;
  42. #else /* !CONFIG_CPU */
  43. #if CONFIG_IS_ENABLED(RISCV_MMODE)
  44. return csr_read(CSR_MISA) & (1 << (ext - 'a'));
  45. #else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
  46. #warning "There is no way to determine the available extensions in S-mode."
  47. #warning "Please convert your board to use the RISC-V CPU driver."
  48. return false;
  49. #endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
  50. #endif /* CONFIG_CPU */
  51. }
  52. static int riscv_cpu_probe(void)
  53. {
  54. #ifdef CONFIG_CPU
  55. int ret;
  56. /* probe cpus so that RISC-V timer can be bound */
  57. ret = cpu_probe_all();
  58. if (ret)
  59. return log_msg_ret("RISC-V cpus probe failed\n", ret);
  60. #endif
  61. return 0;
  62. }
  63. int arch_cpu_init_dm(void)
  64. {
  65. int ret;
  66. ret = riscv_cpu_probe();
  67. if (ret)
  68. return ret;
  69. /* Enable FPU */
  70. if (supports_extension('d') || supports_extension('f')) {
  71. csr_set(MODE_PREFIX(status), MSTATUS_FS);
  72. csr_write(CSR_FCSR, 0);
  73. }
  74. if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
  75. /*
  76. * Enable perf counters for cycle, time,
  77. * and instret counters only
  78. */
  79. csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
  80. /* Disable paging */
  81. if (supports_extension('s'))
  82. csr_write(CSR_SATP, 0);
  83. }
  84. return 0;
  85. }
  86. int arch_early_init_r(void)
  87. {
  88. return riscv_cpu_probe();
  89. }