cpu.c 3.3 KB

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  1. /*
  2. * Copyright (C) 2017-2020 Alibaba Group Holding Limited
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/types.h>
  8. #include <asm/asm.h>
  9. #include <asm/csr.h>
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <fdt_support.h>
  13. #ifdef CONFIG_TARGET_ICE_C910
  14. static phys_addr_t opensbi_addr, dtb_addr;
  15. void (*image_entry)(u32, phys_addr_t);
  16. extern bootm_headers_t images;
  17. static inline void boot_core_vector(void)
  18. {
  19. /* Set pmp regs */
  20. csr_write(pmpaddr0, 0x0 >> 2 | ((0x100000000 - 1) >> 3));
  21. csr_write(pmpaddr1, 0x3f0000000 >> 2 | ((0x10000000 - 1) >> 3));
  22. csr_write(pmpaddr6, 0x00000000 >> 2 | ((0x10000000 - 1) >> 3));
  23. csr_write(pmpaddr7, 0xffffffffff >> 2);
  24. csr_write(pmpcfg0, 0x8898000000001b1f);
  25. /* Set cpu regs */
  26. csr_write(CSR_MCOR, 0x70013);
  27. csr_write(CSR_MCCR2, 0xe0410009);
  28. csr_write(CSR_MHCR, 0x11ff);
  29. csr_write(CSR_MXSTATUS, 0x638000);
  30. csr_write(CSR_MHINT, 0x16e30c);
  31. image_entry(0xdeadbeef, dtb_addr);
  32. }
  33. static void set_vector_cpu(void)
  34. {
  35. int node, cpu;
  36. const void *blob = (const void *)dtb_addr;
  37. node = fdt_path_offset(blob, "/cpus");
  38. if (node < 0)
  39. return;
  40. for (cpu = fdt_first_subnode(blob, node);
  41. cpu >= 0; cpu = fdt_next_subnode(blob, cpu)) {
  42. if (!strcmp("okay", fdt_getprop(blob, cpu, "status", NULL)))
  43. fdt_status_fail((void *)blob, cpu);
  44. else if (!strcmp("fail", fdt_getprop(blob, cpu, "status", NULL)))
  45. fdt_status_okay((void *)blob, cpu);
  46. }
  47. }
  48. static void prep_core_vector(void)
  49. {
  50. printf("Boot vector core(cpu2) only\n");
  51. dtb_addr = (phys_addr_t)images.ft_addr;
  52. opensbi_addr = simple_strtol(env_get("opensbi_addr"), NULL, 0);
  53. image_entry = (void (*)(u32, phys_addr_t))(opensbi_addr);
  54. set_vector_cpu();
  55. csr_write(mrvbr, &boot_core_vector);
  56. csr_write(mrmr, 0x5);
  57. while (1);
  58. }
  59. #endif
  60. /*
  61. * cleanup_before_linux() is called just before we call linux
  62. * it prepares the processor for linux
  63. *
  64. * we disable interrupt and caches.
  65. */
  66. int cleanup_before_linux(void)
  67. {
  68. cache_flush();
  69. #ifdef CONFIG_TARGET_ICE_C910
  70. if ((simple_strtol(env_get("boot_vector"), NULL, 0)) == 1)
  71. prep_core_vector();
  72. #endif
  73. return 0;
  74. }
  75. void flush_dcache_range(unsigned long start, unsigned long end)
  76. {
  77. register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  78. for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
  79. asm volatile(".long 0x0295000b"); /* dcache.cpa a0 */
  80. sync_is();
  81. }
  82. void invalidate_dcache_range(unsigned long start, unsigned long end)
  83. {
  84. register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  85. for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
  86. asm volatile(".long 0x02b5000b"); /* dcache.cipa a0 */
  87. sync_is();
  88. }
  89. void invalid_dcache_range(unsigned long start, unsigned long end)
  90. {
  91. register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  92. for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
  93. asm volatile(".long 0x02a5000b"); /* dcache.ipa a0 */
  94. sync_is();
  95. }
  96. void icache_enable(void)
  97. {
  98. #ifdef CONFIG_SPL_BUILD
  99. #ifdef CONFIG_SPL_RISCV_MMODE
  100. #ifdef CONFIG_TARGET_LIGHT_C910
  101. asm volatile (
  102. "csrr x29, mhcr\n\t"
  103. "ori x28, x29, 0x1\n\t"
  104. "csrw mhcr, x28\n\t"
  105. );
  106. #endif
  107. #endif
  108. #endif
  109. }
  110. void dcache_enable(void)
  111. {
  112. #ifdef CONFIG_SPL_BUILD
  113. #ifdef CONFIG_SPL_RISCV_MMODE
  114. #ifdef CONFIG_TARGET_LIGHT_C910
  115. asm volatile (
  116. "li x29, 0x11ff\n\t"
  117. "csrw mhcr, x29\n\t"
  118. );
  119. #endif
  120. #endif
  121. #endif
  122. }