core_rv32_old.h 42 KB

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  1. /*
  2. * Copyright (C) 2017-2019 Alibaba Group Holding Limited
  3. */
  4. /******************************************************************************
  5. * @file core_rv32.h
  6. * @brief CSI RV32 Core Peripheral Access Layer Header File
  7. * @version V1.0
  8. * @date 01. Sep 2018
  9. ******************************************************************************/
  10. #ifndef __CORE_RV32_H_GENERIC
  11. #define __CORE_RV32_H_GENERIC
  12. #include <stdint.h>
  13. #ifdef __cplusplus
  14. extern "C" {
  15. #endif
  16. /*******************************************************************************
  17. * CSI definitions
  18. ******************************************************************************/
  19. /**
  20. \ingroup RV32
  21. @{
  22. */
  23. #ifndef __RV32
  24. #define __RV32 (0x01U)
  25. #endif
  26. /** __FPU_USED indicates whether an FPU is used or not.
  27. This core does not support an FPU at all
  28. */
  29. #define __FPU_USED 0U
  30. #if defined ( __GNUC__ )
  31. #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  32. #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  33. #endif
  34. #endif
  35. #ifdef __cplusplus
  36. }
  37. #endif
  38. #endif /* __CORE_RV32_H_GENERIC */
  39. #ifndef __CSI_GENERIC
  40. #ifndef __CORE_RV32_H_DEPENDANT
  41. #define __CORE_RV32_H_DEPENDANT
  42. #ifdef __cplusplus
  43. extern "C" {
  44. #endif
  45. /* check device defines and use defaults */
  46. #ifndef __RV32_REV
  47. #define __RV32_REV 0x0000U
  48. #endif
  49. #ifndef __VIC_PRIO_BITS
  50. #define __VIC_PRIO_BITS 2U
  51. #endif
  52. #ifndef __Vendor_SysTickConfig
  53. #define __Vendor_SysTickConfig 1U
  54. #endif
  55. #ifndef __MPU_PRESENT
  56. #define __MPU_PRESENT 1U
  57. #endif
  58. #ifndef __ICACHE_PRESENT
  59. #define __ICACHE_PRESENT 1U
  60. #endif
  61. #ifndef __DCACHE_PRESENT
  62. #define __DCACHE_PRESENT 1U
  63. #endif
  64. #include <core/csi_rv32_gcc.h>
  65. /* IO definitions (access restrictions to peripheral registers) */
  66. /**
  67. \defgroup CSI_glob_defs CSI Global Defines
  68. <strong>IO Type Qualifiers</strong> are used
  69. \li to specify the access to peripheral variables.
  70. \li for automatic generation of peripheral register debug information.
  71. */
  72. #ifdef __cplusplus
  73. #define __I volatile /*!< Defines 'read only' permissions */
  74. #else
  75. #define __I volatile const /*!< Defines 'read only' permissions */
  76. #endif
  77. #define __O volatile /*!< Defines 'write only' permissions */
  78. #define __IO volatile /*!< Defines 'read / write' permissions */
  79. /* following defines should be used for structure members */
  80. #define __IM volatile const /*! Defines 'read only' structure member permissions */
  81. #define __OM volatile /*! Defines 'write only' structure member permissions */
  82. #define __IOM volatile /*! Defines 'read / write' structure member permissions */
  83. /*@} end of group CK802 */
  84. /*******************************************************************************
  85. * Register Abstraction
  86. Core Register contain:
  87. - Core Register
  88. - Core CLIC Register
  89. ******************************************************************************/
  90. /**
  91. \defgroup CSI_core_register Defines and Type Definitions
  92. \brief Type definitions and defines for CK80X processor based devices.
  93. */
  94. /**
  95. \ingroup CSI_core_register
  96. \defgroup CSI_CORE Status and Control Registers
  97. \brief Core Register type definitions.
  98. @{
  99. */
  100. /**
  101. \ingroup CSI_core_register
  102. \defgroup CSI_CLIC Core-Local Interrupt Controller (CLIC)
  103. \brief Type definitions for the CLIC Registers
  104. @{
  105. */
  106. /**
  107. \brief Access to the structure of a vector interrupt controller.
  108. */
  109. typedef struct {
  110. __IOM uint8_t INTIP[1024U]; /*!< Offset: 0x000 (R/W) Interrupt set pending register */
  111. __IOM uint8_t INTIE[1024U]; /*!< Offset: 0x000 (R/W) Interrupt set enable register */
  112. __IOM uint8_t INTCFG[768U]; /*!< Offset: 0x000 (R/W) Interrupt configure register */
  113. __IOM uint8_t CLICCFG; /*!< Offset: 0x000 (R/W) CLIC configure register */
  114. } CLIC_Type;
  115. #define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */
  116. #define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */
  117. #define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */
  118. #define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */
  119. #define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */
  120. #define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */
  121. #define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */
  122. #define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */
  123. #define CLIC_INTCFG_PRIO_Pos 6U /*!< CLIC INTCFG: INTCFG Position */
  124. #define CLIC_INTCFG_PRIO_Msk (0x1UL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */
  125. #define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */
  126. #define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */
  127. #define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */
  128. #define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */
  129. #define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */
  130. #define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */
  131. /*@} end of group CSI_CLIC */
  132. /**
  133. \ingroup CSI_core_register
  134. \defgroup CSI_PMP Physical Memory Protection (PMP)
  135. \brief Type definitions for the PMP Registers
  136. @{
  137. */
  138. #define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */
  139. #define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */
  140. #define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */
  141. #define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */
  142. #define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */
  143. #define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */
  144. #define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */
  145. #define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */
  146. #define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */
  147. #define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */
  148. typedef enum {
  149. REGION_SIZE_4B = -1,
  150. REGION_SIZE_8B = 0,
  151. REGION_SIZE_16B = 1,
  152. REGION_SIZE_32B = 2,
  153. REGION_SIZE_64B = 3,
  154. REGION_SIZE_128B = 4,
  155. REGION_SIZE_256B = 5,
  156. REGION_SIZE_512B = 6,
  157. REGION_SIZE_1KB = 7,
  158. REGION_SIZE_2KB = 8,
  159. REGION_SIZE_4KB = 9,
  160. REGION_SIZE_8KB = 10,
  161. REGION_SIZE_16KB = 11,
  162. REGION_SIZE_32KB = 12,
  163. REGION_SIZE_64KB = 13,
  164. REGION_SIZE_128KB = 14,
  165. REGION_SIZE_256KB = 15,
  166. REGION_SIZE_512KB = 16,
  167. REGION_SIZE_1MB = 17,
  168. REGION_SIZE_2MB = 18,
  169. REGION_SIZE_4MB = 19,
  170. REGION_SIZE_8MB = 20,
  171. REGION_SIZE_16MB = 21,
  172. REGION_SIZE_32MB = 22,
  173. REGION_SIZE_64MB = 23,
  174. REGION_SIZE_128MB = 24,
  175. REGION_SIZE_256MB = 25,
  176. REGION_SIZE_512MB = 26,
  177. REGION_SIZE_1GB = 27,
  178. REGION_SIZE_2GB = 28,
  179. REGION_SIZE_4GB = 29,
  180. REGION_SIZE_8GB = 30,
  181. REGION_SIZE_16GB = 31
  182. } region_size_e;
  183. typedef enum {
  184. ADDRESS_MATCHING_TOR = 1,
  185. ADDRESS_MATCHING_NAPOT = 3
  186. } address_matching_e;
  187. typedef struct {
  188. uint32_t r: 1; /* readable enable */
  189. uint32_t w: 1; /* writeable enable */
  190. uint32_t x: 1; /* execable enable */
  191. address_matching_e a: 2; /* address matching mode */
  192. uint32_t reserved: 2; /* reserved */
  193. uint32_t l: 1; /* lock enable */
  194. } mpu_region_attr_t;
  195. /*@} end of group CSI_PMP */
  196. /**
  197. \ingroup CSI_core_register
  198. \defgroup CSI_CACHE
  199. \brief Type definitions for the cache Registers
  200. @{
  201. */
  202. /**
  203. \brief On chip cache structure.
  204. */
  205. typedef struct
  206. {
  207. __IOM uint32_t CER; /*!< Offset: 0x000 (R/W) Cache enable register */
  208. __IOM uint32_t CIR; /*!< Offset: 0x004 (R/W) Cache invalid register */
  209. __IOM uint32_t CRCR[4U]; /*!< Offset: 0x008 (R/W) Cache Configuration register */
  210. uint32_t RSERVED0[1015U];
  211. __IOM uint32_t CPFCR; /*!< Offset: 0xFF4 (R/W) Cache performance analisis control register */
  212. __IOM uint32_t CPFATR; /*!< Offset: 0xFF8 (R/W) Cache access times register */
  213. __IOM uint32_t CPFMTR; /*!< Offset: 0xFFC (R/W) Cache missing times register */
  214. } CACHE_Type;
  215. /* CACHE Register Definitions */
  216. #define CACHE_CER_EN_Pos 0U /*!< CACHE CER: EN Position */
  217. #define CACHE_CER_EN_Msk (0x1UL << CACHE_CER_EN_Pos) /*!< CACHE CER: EN Mask */
  218. #define CACHE_CER_CFIG_Pos 1U /*!< CACHE CER: CFIG Position */
  219. #define CACHE_CER_CFIG_Msk (0x1UL << CACHE_CER_CFIG_Pos) /*!< CACHE CER: CFIG Mask */
  220. #define CACHE_CER_WB_Pos 2U /*!< CACHE CER: WB Position */
  221. #define CACHE_CER_WB_Msk (0x1UL << CACHE_CER_WB_Pos) /*!< CACHE CER: WB Mask */
  222. #define CACHE_CER_WCFIG_Pos 3U /*!< CACHE CER: WCFIG Position */
  223. #define CACHE_CER_WCFIG_Msk (0x1UL << CACHE_CER_WCFIG_Pos) /*!< CACHE CER: WCFIG Mask */
  224. #define CACHE_CER_DCW_Pos 4U /*!< CACHE CER: DCW Position */
  225. #define CACHE_CER_DCW_Msk (0x1UL << CACHE_CER_DCW_Pos) /*!< CACHE CER: DCW Mask */
  226. #define CACHE_CER_CS_Pos 31U /*!< CACHE CER: CS Position */
  227. #define CACHE_CER_CS_Msk (0x1UL << CACHE_CER_CS_Pos) /*!< CACHE CER: CS Mask */
  228. #define CACHE_CIR_INV_ALL_Pos 0U /*!< CACHE CIR: INV_ALL Position */
  229. #define CACHE_CIR_INV_ALL_Msk (0x1UL << CACHE_CIR_INV_ALL_Pos) /*!< CACHE CIR: INV_ALL Mask */
  230. #define CACHE_CIR_INV_ONE_Pos 1U /*!< CACHE CIR: INV_ONE Position */
  231. #define CACHE_CIR_INV_ONE_Msk (0x1UL << CACHE_CIR_INV_ONE_Pos) /*!< CACHE CIR: INV_ONE Mask */
  232. #define CACHE_CIR_CLR_ALL_Pos 2U /*!< CACHE CIR: CLR_ALL Position */
  233. #define CACHE_CIR_CLR_ALL_Msk (0x1UL << CACHE_CIR_CLR_ALL_Pos) /*!< CACHE CIR: CLR_ALL Mask */
  234. #define CACHE_CIR_CLR_ONE_Pos 3U /*!< CACHE CIR: CLR_ONE Position */
  235. #define CACHE_CIR_CLR_ONE_Msk (0x1UL << CACHE_CIR_CLR_ONE_Pos) /*!< CACHE CIR: CLR_ONE Mask */
  236. #define CACHE_CIR_INV_ADDR_Pos 4U /*!< CACHE CIR: INV_ADDR Position */
  237. #define CACHE_CIR_INV_ADDR_Msk (0xFFFFFFFUL << CACHE_CIR_INV_ADDR_Pos) /*!< CACHE CIR: INV_ADDR Mask */
  238. #define CACHE_CRCR_EN_Pos 0U /*!< CACHE CRCR: EN Position */
  239. #define CACHE_CRCR_EN_Msk (0x1UL << CACHE_CRCR_EN_Pos) /*!< CACHE CRCR: EN Mask */
  240. #define CACHE_CRCR_SIZE_Pos 1U /*!< CACHE CRCR: Size Position */
  241. #define CACHE_CRCR_SIZE_Msk (0x1FUL << CACHE_CRCR_SIZE_Pos) /*!< CACHE CRCR: Size Mask */
  242. #define CACHE_CRCR_BASE_ADDR_Pos 10U /*!< CACHE CRCR: base addr Position */
  243. #define CACHE_CRCR_BASE_ADDR_Msk (0x3FFFFFUL << CACHE_CRCR_BASE_ADDR_Pos) /*!< CACHE CRCR: base addr Mask */
  244. #define CACHE_CPFCR_PFEN_Pos 0U /*!< CACHE CPFCR: PFEN Position */
  245. #define CACHE_CPFCR_PFEN_Msk (0x1UL << CACHE_CPFCR_PFEN_Pos) /*!< CACHE CPFCR: PFEN Mask */
  246. #define CACHE_CPFCR_PFRST_Pos 1U /*!< CACHE CPFCR: PFRST Position */
  247. #define CACHE_CPFCR_PFRST_Msk (0x1UL << CACHE_CPFCR_PFRST_Pos) /*!< CACHE CPFCR: PFRST Mask */
  248. #define CACHE_CRCR_4K 0xB /* 01011 */
  249. #define CACHE_CRCR_8K 0xC /* 01100 */
  250. #define CACHE_CRCR_16K 0xD /* 01101 */
  251. #define CACHE_CRCR_32K 0xE /* 01110 */
  252. #define CACHE_CRCR_64K 0xF /* 01111 */
  253. #define CACHE_CRCR_128K 0x10 /* 10000 */
  254. #define CACHE_CRCR_256K 0x11 /* 10001 */
  255. #define CACHE_CRCR_512K 0x12 /* 10010 */
  256. #define CACHE_CRCR_1M 0x13 /* 10011 */
  257. #define CACHE_CRCR_2M 0x14 /* 10100 */
  258. #define CACHE_CRCR_4M 0x15 /* 10101 */
  259. #define CACHE_CRCR_8M 0x16 /* 10110 */
  260. #define CACHE_CRCR_16M 0x17 /* 10111 */
  261. #define CACHE_CRCR_32M 0x18 /* 11000 */
  262. #define CACHE_CRCR_64M 0x19 /* 11001 */
  263. #define CACHE_CRCR_128M 0x1A /* 11010 */
  264. #define CACHE_CRCR_256M 0x1B /* 11011 */
  265. #define CACHE_CRCR_512M 0x1C /* 11100 */
  266. #define CACHE_CRCR_1G 0x1D /* 11101 */
  267. #define CACHE_CRCR_2G 0x1E /* 11110 */
  268. #define CACHE_CRCR_4G 0x1F /* 11111 */
  269. /*@} end of group CSI_CACHE */
  270. /**
  271. \ingroup CSI_core_register
  272. \defgroup CSI_SysTick System Tick Timer (CORET)
  273. \brief Type definitions for the System Timer Registers.
  274. @{
  275. */
  276. /**
  277. \brief The data structure of the access system timer.
  278. */
  279. typedef struct {
  280. __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control register */
  281. __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) Backfill register */
  282. __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) Current register */
  283. __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) Calibration register */
  284. } CORET_Type;
  285. /* CORET Control / Status Register Definitions */
  286. #define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
  287. #define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
  288. #define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
  289. #define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
  290. #define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
  291. #define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
  292. #define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
  293. #define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
  294. /* CORET Reload Register Definitions */
  295. #define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
  296. #define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
  297. /* CORET Current Register Definitions */
  298. #define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
  299. #define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
  300. /* CORET Calibration Register Definitions */
  301. #define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
  302. #define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
  303. #define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
  304. #define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
  305. #define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
  306. #define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
  307. /*@} end of group CSI_SysTick */
  308. /**
  309. \ingroup CSI_core_register
  310. \defgroup CSI_DCC
  311. \brief Type definitions for the DCC.
  312. @{
  313. */
  314. /**
  315. \brief Access to the data structure of DCC.
  316. */
  317. typedef struct {
  318. uint32_t RESERVED0[13U];
  319. __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
  320. __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
  321. uint32_t RESERVED1[6U];
  322. union {
  323. __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) Data exchange register CPU read*/
  324. __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) Data exchange register CPU writer*/
  325. };
  326. } DCC_Type;
  327. #define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
  328. #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
  329. #define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
  330. #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
  331. #define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
  332. #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
  333. #define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
  334. #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
  335. /*@} end of group CSI_DCC */
  336. /**
  337. \ingroup CSI_core_register
  338. \defgroup CSI_core_bitfield Core register bit field macros
  339. \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  340. @{
  341. */
  342. /**
  343. \brief Mask and shift a bit field value for use in a register bit range.
  344. \param[in] field Name of the register bit field.
  345. \param[in] value Value of the bit field.
  346. \return Masked and shifted value.
  347. */
  348. #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
  349. /**
  350. \brief Mask and shift a register value to extract a bit filed value.
  351. \param[in] field Name of the register bit field.
  352. \param[in] value Value of register.
  353. \return Masked and shifted bit field value.
  354. */
  355. #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
  356. /*@} end of group CSI_core_bitfield */
  357. /**
  358. \ingroup CSI_core_register
  359. \defgroup CSI_core_base Core Definitions
  360. \brief Definitions for base addresses, unions, and structures.
  361. @{
  362. */
  363. /* Memory mapping of CK802 Hardware */
  364. #define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
  365. #define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
  366. #define CLIC_BASE (TCIP_BASE + 0x0100UL) /*!< CLIC Base Address */
  367. #define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
  368. #define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
  369. #define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
  370. #define CLIC ((CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */
  371. #define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
  372. #define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
  373. /*@} */
  374. /*******************************************************************************
  375. * Hardware Abstraction Layer
  376. Core Function Interface contains:
  377. - Core VIC Functions
  378. - Core CORET Functions
  379. - Core Register Access Functions
  380. ******************************************************************************/
  381. /**
  382. \defgroup CSI_Core_FunctionInterface Functions and Instructions Reference
  383. */
  384. /* ########################## VIC functions #################################### */
  385. /**
  386. \ingroup CSI_Core_FunctionInterface
  387. \defgroup CSI_Core_VICFunctions VIC Functions
  388. \brief Functions that manage interrupts and exceptions via the VIC.
  389. @{
  390. */
  391. /* The following MACROS handle generation of the register offset and byte masks */
  392. #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
  393. #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 5UL) )
  394. #define _IP2_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
  395. /**
  396. \brief Enable External Interrupt
  397. \details Enable a device-specific interrupt in the VIC interrupt controller.
  398. \param [in] IRQn External interrupt number. Value cannot be negative.
  399. */
  400. __STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
  401. {
  402. CLIC->INTIE[IRQn] |= CLIC_INTIE_IE_Msk;
  403. }
  404. /**
  405. \brief Disable External Interrupt
  406. \details Disable a device-specific interrupt in the VIC interrupt controller.
  407. \param [in] IRQn External interrupt number. Value cannot be negative.
  408. */
  409. __STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
  410. {
  411. CLIC->INTIE[IRQn] &= ~CLIC_INTIE_IE_Msk;
  412. }
  413. /**
  414. \brief Enable External Secure Interrupt
  415. \details Enable a secure device-specific interrupt in the VIC interrupt controller.
  416. \param [in] IRQn External interrupt number. Value cannot be negative.
  417. */
  418. __STATIC_INLINE void csi_vic_enable_sirq(int32_t IRQn)
  419. {
  420. CLIC->INTIE[IRQn] |= (CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
  421. }
  422. /**
  423. \brief Disable External Secure Interrupt
  424. \details Disable a secure device-specific interrupt in the VIC interrupt controller.
  425. \param [in] IRQn External interrupt number. Value cannot be negative.
  426. */
  427. __STATIC_INLINE void csi_vic_disable_sirq(int32_t IRQn)
  428. {
  429. CLIC->INTIE[IRQn] &= ~(CLIC_INTIE_IE_Msk | CLIC_INTIE_T_Msk);
  430. }
  431. /**
  432. \brief Check Interrupt is Enabled or not
  433. \details Read the enabled register in the VIC and returns the pending bit for the specified interrupt.
  434. \param [in] IRQn Interrupt number.
  435. \return 0 Interrupt status is not enabled.
  436. \return 1 Interrupt status is enabled.
  437. */
  438. __STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
  439. {
  440. return (uint32_t)(CLIC->INTIE[IRQn] & CLIC_INTIE_IE_Msk);
  441. }
  442. /**
  443. \brief Check Interrupt is Pending or not
  444. \details Read the pending register in the VIC and returns the pending bit for the specified interrupt.
  445. \param [in] IRQn Interrupt number.
  446. \return 0 Interrupt status is not pending.
  447. \return 1 Interrupt status is pending.
  448. */
  449. __STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
  450. {
  451. return (uint32_t)(CLIC->INTIP[IRQn] & CLIC_INTIP_IP_Msk);
  452. }
  453. /**
  454. \brief Set Pending Interrupt
  455. \details Set the pending bit of an external interrupt.
  456. \param [in] IRQn Interrupt number. Value cannot be negative.
  457. */
  458. __STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
  459. {
  460. CLIC->INTIP[IRQn] |= CLIC_INTIP_IP_Msk;
  461. }
  462. /**
  463. \brief Clear Pending Interrupt
  464. \details Clear the pending bit of an external interrupt.
  465. \param [in] IRQn External interrupt number. Value cannot be negative.
  466. */
  467. __STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
  468. {
  469. CLIC->INTIP[IRQn] &= ~CLIC_INTIP_IP_Msk;
  470. }
  471. /**
  472. \brief Set Interrupt Priority
  473. \details Set the priority of an interrupt.
  474. \note The priority cannot be set for every core interrupt.
  475. \param [in] IRQn Interrupt number.
  476. \param [in] priority Priority to set.
  477. */
  478. __STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
  479. {
  480. CLIC->INTCFG[IRQn] = (CLIC->INTCFG[IRQn] & (~CLIC_INTCFG_PRIO_Msk)) | (priority << CLIC_INTCFG_PRIO_Pos);
  481. }
  482. /**
  483. \brief Get Interrupt Priority
  484. \details Read the priority of an interrupt.
  485. The interrupt number can be positive to specify an external (device specific) interrupt,
  486. or negative to specify an internal (core) interrupt.
  487. \param [in] IRQn Interrupt number.
  488. \return Interrupt Priority.
  489. Value is aligned automatically to the implemented priority bits of the microcontroller.
  490. */
  491. __STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
  492. {
  493. return CLIC->INTCFG[IRQn] >> CLIC_INTCFG_PRIO_Pos;
  494. }
  495. /**
  496. \brief Set interrupt handler
  497. \details Set the interrupt handler according to the interrupt num, the handler will be filled in irq vectors.
  498. \param [in] IRQn Interrupt number.
  499. \param [in] handler Interrupt handler.
  500. */
  501. __STATIC_INLINE void csi_vic_set_vector(int32_t IRQn, uint32_t handler)
  502. {
  503. if (IRQn >= 0 && IRQn < 1024) {
  504. uint32_t *vectors = (uint32_t *)__get_MTVT();
  505. vectors[32 + IRQn] = handler;
  506. }
  507. }
  508. /**
  509. \brief Get interrupt handler
  510. \details Get the address of interrupt handler function.
  511. \param [in] IRQn Interrupt number.
  512. */
  513. __STATIC_INLINE uint32_t csi_vic_get_vector(int32_t IRQn)
  514. {
  515. if (IRQn >= 0 && IRQn < 1024) {
  516. uint32_t *vectors = (uint32_t *)__get_MTVT();
  517. return (uint32_t)vectors[32 + IRQn];
  518. }
  519. return 0;
  520. }
  521. /*@} end of CSI_Core_VICFunctions */
  522. /* ########################## PMP functions #################################### */
  523. /**
  524. \ingroup CSI_Core_FunctionInterface
  525. \defgroup CSI_Core_PMPFunctions PMP Functions
  526. \brief Functions that manage interrupts and exceptions via the VIC.
  527. @{
  528. */
  529. /**
  530. \brief configure memory protected region.
  531. \details
  532. \param [in] idx memory protected region (0, 1, 2, ..., 15).
  533. \param [in] base_addr base address must be aligned with page size.
  534. \param [in] size \ref region_size_e. memory protected region size.
  535. \param [in] attr \ref region_size_t. memory protected region attribute.
  536. \param [in] enable enable or disable memory protected region.
  537. */
  538. __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, region_size_e size,
  539. mpu_region_attr_t attr, uint32_t enable)
  540. {
  541. uint8_t pmpxcfg = 0;
  542. uint32_t addr = 0;
  543. if (idx > 15) {
  544. return;
  545. }
  546. if (!enable) {
  547. attr.a = 0;
  548. }
  549. if (attr.a == ADDRESS_MATCHING_TOR) {
  550. addr = base_addr >> 2;
  551. } else {
  552. if (size == REGION_SIZE_4B) {
  553. addr = base_addr >> 2;
  554. attr.a = 2;
  555. } else {
  556. addr = ((base_addr >> 2) & (0xFFFFFFFFU - ((1 << (size + 1)) - 1))) | ((1 << size) - 1);
  557. }
  558. }
  559. __set_PMPADDRx(idx, addr);
  560. pmpxcfg |= (attr.r << PMP_PMPCFG_R_Pos) | (attr.w << PMP_PMPCFG_W_Pos) |
  561. (attr.x << PMP_PMPCFG_X_Pos) | (attr.a << PMP_PMPCFG_A_Pos) |
  562. (attr.l << PMP_PMPCFG_L_Pos);
  563. __set_PMPxCFG(idx, pmpxcfg);
  564. }
  565. /**
  566. \brief disable mpu region by idx.
  567. \details
  568. \param [in] idx memory protected region (0, 1, 2, ..., 15).
  569. */
  570. __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
  571. {
  572. __set_PMPxCFG(idx, __get_PMPxCFG(idx) & (~PMP_PMPCFG_A_Msk));
  573. }
  574. /*@} end of CSI_Core_PMPFunctions */
  575. /* ################################## SysTick function ############################################ */
  576. /**
  577. \ingroup CSI_Core_FunctionInterface
  578. \defgroup CSI_Core_SysTickFunctions SysTick Functions
  579. \brief Functions that configure the System.
  580. @{
  581. */
  582. /**
  583. \brief CORE timer Configuration
  584. \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
  585. Counter is in free running mode to generate periodic interrupts.
  586. \param [in] ticks Number of ticks between two interrupts.
  587. \param [in] IRQn core timer Interrupt number.
  588. \return 0 Function succeeded.
  589. \return 1 Function failed.
  590. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
  591. function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
  592. must contain a vendor-specific implementation of this function.
  593. */
  594. __STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
  595. {
  596. if ((ticks - 1UL) > CORET_LOAD_RELOAD_Msk) {
  597. return (1UL); /* Reload value impossible */
  598. }
  599. CORET->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
  600. CORET->VAL = 0UL; /* Load the CORET Counter Value */
  601. CORET->CTRL = CORET_CTRL_CLKSOURCE_Msk |
  602. CORET_CTRL_TICKINT_Msk |
  603. CORET_CTRL_ENABLE_Msk; /* Enable CORET IRQ and CORET Timer */
  604. return (0UL); /* Function successful */
  605. }
  606. /**
  607. \brief get CORE timer reload value
  608. \return CORE timer counter value.
  609. */
  610. __STATIC_INLINE uint32_t csi_coret_get_load(void)
  611. {
  612. return CORET->LOAD;
  613. }
  614. /**
  615. \brief get CORE timer counter value
  616. \return CORE timer counter value.
  617. */
  618. __STATIC_INLINE uint32_t csi_coret_get_value(void)
  619. {
  620. return CORET->VAL;
  621. }
  622. /*@} end of CSI_Core_SysTickFunctions */
  623. /* ##################################### DCC function ########################################### */
  624. /**
  625. \ingroup CSI_Core_FunctionInterface
  626. \defgroup CSI_core_DebugFunctions HAD Functions
  627. \brief Functions that access the HAD debug interface.
  628. @{
  629. */
  630. /**
  631. \brief HAD Send Character
  632. \details Transmits a character via the HAD channel 0, and
  633. \li Just returns when no debugger is connected that has booked the output.
  634. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
  635. \param [in] ch Character to transmit.
  636. \returns Character to transmit.
  637. */
  638. __STATIC_INLINE uint32_t csi_had_send_char(uint32_t ch)
  639. {
  640. DCC->DERJR = (uint8_t)ch;
  641. return (ch);
  642. }
  643. /**
  644. \brief HAD Receive Character
  645. \details Inputs a character via the external variable \ref HAD_RxBuffer.
  646. \return Received character.
  647. \return -1 No character pending.
  648. */
  649. __STATIC_INLINE int32_t csi_had_receive_char(void)
  650. {
  651. int32_t ch = -1; /* no character available */
  652. if (_FLD2VAL(DCC_EHSR_JW, DCC->EHSR)) {
  653. ch = DCC->DERJW;
  654. }
  655. return (ch);
  656. }
  657. /**
  658. \brief HAD Check Character
  659. \details Check whether a character is pending for reading in the variable \ref HAD_RxBuffer.
  660. \return 0 No character available.
  661. \return 1 Character available.
  662. */
  663. __STATIC_INLINE int32_t csi_had_check_char(void)
  664. {
  665. return _FLD2VAL(DCC_EHSR_JW, DCC->EHSR); /* no character available */
  666. }
  667. /*@} end of CSI_core_DebugFunctions */
  668. /* ########################## Cache functions #################################### */
  669. /**
  670. \ingroup CSI_Core_FunctionInterface
  671. \defgroup CSI_Core_CacheFunctions Cache Functions
  672. \brief Functions that configure Instruction and Data cache.
  673. @{
  674. */
  675. /**
  676. \brief Enable I-Cache
  677. \details Turns on I-Cache
  678. */
  679. __STATIC_INLINE void csi_icache_enable (void)
  680. {
  681. #if (__ICACHE_PRESENT == 1U)
  682. __DSB();
  683. __ISB();
  684. CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
  685. CACHE->CER |= (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* enable all Cache */
  686. __DSB();
  687. __ISB();
  688. #endif
  689. }
  690. /**
  691. \brief Disable I-Cache
  692. \details Turns off I-Cache
  693. */
  694. __STATIC_INLINE void csi_icache_disable (void)
  695. {
  696. #if (__ICACHE_PRESENT == 1U)
  697. __DSB();
  698. __ISB();
  699. CACHE->CER &= ~(uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_CFIG_Msk); /* disable all Cache */
  700. CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
  701. __DSB();
  702. __ISB();
  703. #endif
  704. }
  705. /**
  706. \brief Invalidate I-Cache
  707. \details Invalidates I-Cache
  708. */
  709. __STATIC_INLINE void csi_icache_invalid (void)
  710. {
  711. #if (__ICACHE_PRESENT == 1U)
  712. __DSB();
  713. __ISB();
  714. CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
  715. __DSB();
  716. __ISB();
  717. #endif
  718. }
  719. /**
  720. \brief Enable D-Cache
  721. \details Turns on D-Cache
  722. \note I-Cache also turns on.
  723. */
  724. __STATIC_INLINE void csi_dcache_enable (void)
  725. {
  726. #if (__DCACHE_PRESENT == 1U)
  727. __DSB();
  728. __ISB();
  729. CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
  730. CACHE->CER = (uint32_t)(CACHE_CER_EN_Msk | CACHE_CER_WB_Msk | CACHE_CER_DCW_Msk) & (~CACHE_CER_CFIG_Msk); /* enable all Cache */
  731. __DSB();
  732. __ISB();
  733. #endif
  734. }
  735. /**
  736. \brief Disable D-Cache
  737. \details Turns off D-Cache
  738. \note I-Cache also turns off.
  739. */
  740. __STATIC_INLINE void csi_dcache_disable (void)
  741. {
  742. #if (__DCACHE_PRESENT == 1U)
  743. __DSB();
  744. __ISB();
  745. CACHE->CER &= ~(uint32_t)CACHE_CER_EN_Msk; /* disable all Cache */
  746. CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
  747. __DSB();
  748. __ISB();
  749. #endif
  750. }
  751. /**
  752. \brief Invalidate D-Cache
  753. \details Invalidates D-Cache
  754. \note I-Cache also invalid
  755. */
  756. __STATIC_INLINE void csi_dcache_invalid (void)
  757. {
  758. #if (__DCACHE_PRESENT == 1U)
  759. __DSB();
  760. __ISB();
  761. CACHE->CIR = CACHE_CIR_INV_ALL_Msk; /* invalidate all Cache */
  762. __DSB();
  763. __ISB();
  764. #endif
  765. }
  766. /**
  767. \brief Clean D-Cache
  768. \details Cleans D-Cache
  769. \note I-Cache also cleans
  770. */
  771. __STATIC_INLINE void csi_dcache_clean (void)
  772. {
  773. #if (__DCACHE_PRESENT == 1U)
  774. __DSB();
  775. __ISB();
  776. CACHE->CIR = _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean all Cache */
  777. __DSB();
  778. __ISB();
  779. #endif
  780. }
  781. /**
  782. \brief Clean & Invalidate D-Cache
  783. \details Cleans and Invalidates D-Cache
  784. \note I-Cache also flush.
  785. */
  786. __STATIC_INLINE void csi_dcache_clean_invalid (void)
  787. {
  788. #if (__DCACHE_PRESENT == 1U)
  789. __DSB();
  790. __ISB();
  791. CACHE->CIR = _VAL2FLD(CACHE_CIR_INV_ALL, 1) | _VAL2FLD(CACHE_CIR_CLR_ALL, 1); /* clean and inv all Cache */
  792. __DSB();
  793. __ISB();
  794. #endif
  795. }
  796. /**
  797. \brief D-Cache Invalidate by address
  798. \details Invalidates D-Cache for the given address
  799. \param[in] addr address (aligned to 16-byte boundary)
  800. \param[in] dsize size of memory block (aligned to 16-byte boundary)
  801. */
  802. __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
  803. {
  804. #if (__DCACHE_PRESENT == 1U)
  805. int32_t op_size = dsize + (uint32_t)addr % 16;
  806. uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
  807. int32_t linesize = 16;
  808. op_addr |= _VAL2FLD(CACHE_CIR_INV_ONE, 1);
  809. while (op_size >= 128) {
  810. CACHE->CIR = op_addr;
  811. op_addr += linesize;
  812. CACHE->CIR = op_addr;
  813. op_addr += linesize;
  814. CACHE->CIR = op_addr;
  815. op_addr += linesize;
  816. CACHE->CIR = op_addr;
  817. op_addr += linesize;
  818. CACHE->CIR = op_addr;
  819. op_addr += linesize;
  820. CACHE->CIR = op_addr;
  821. op_addr += linesize;
  822. CACHE->CIR = op_addr;
  823. op_addr += linesize;
  824. CACHE->CIR = op_addr;
  825. op_addr += linesize;
  826. op_size -= 128;
  827. }
  828. while (op_size > 0) {
  829. CACHE->CIR = op_addr;
  830. op_addr += linesize;
  831. op_size -= linesize;
  832. }
  833. #endif
  834. }
  835. /**
  836. \brief D-Cache Clean by address
  837. \details Cleans D-Cache for the given address
  838. \param[in] addr address (aligned to 16-byte boundary)
  839. \param[in] dsize size of memory block (aligned to 16-byte boundary)
  840. */
  841. __STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
  842. {
  843. #if (__DCACHE_PRESENT == 1)
  844. int32_t op_size = dsize + (uint32_t)addr % 16;
  845. uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
  846. int32_t linesize = 16;
  847. op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1);
  848. while (op_size >= 128) {
  849. CACHE->CIR = op_addr;
  850. op_addr += linesize;
  851. CACHE->CIR = op_addr;
  852. op_addr += linesize;
  853. CACHE->CIR = op_addr;
  854. op_addr += linesize;
  855. CACHE->CIR = op_addr;
  856. op_addr += linesize;
  857. CACHE->CIR = op_addr;
  858. op_addr += linesize;
  859. CACHE->CIR = op_addr;
  860. op_addr += linesize;
  861. CACHE->CIR = op_addr;
  862. op_addr += linesize;
  863. CACHE->CIR = op_addr;
  864. op_addr += linesize;
  865. op_size -= 128;
  866. }
  867. while (op_size > 0) {
  868. CACHE->CIR = op_addr;
  869. op_addr += linesize;
  870. op_size -= linesize;
  871. }
  872. #endif
  873. }
  874. /**
  875. \brief D-Cache Clean and Invalidate by address
  876. \details Cleans and invalidates D_Cache for the given address
  877. \param[in] addr address (aligned to 16-byte boundary)
  878. \param[in] dsize size of memory block (aligned to 16-byte boundary)
  879. */
  880. __STATIC_INLINE void csi_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
  881. {
  882. #if (__DCACHE_PRESENT == 1U)
  883. int32_t op_size = dsize + (uint32_t)addr % 16;
  884. uint32_t op_addr = (uint32_t)addr & CACHE_CIR_INV_ADDR_Msk;
  885. int32_t linesize = 16;
  886. op_addr |= _VAL2FLD(CACHE_CIR_CLR_ONE, 1) | _VAL2FLD(CACHE_CIR_INV_ONE, 1);
  887. while (op_size >= 128) {
  888. CACHE->CIR = op_addr;
  889. op_addr += linesize;
  890. CACHE->CIR = op_addr;
  891. op_addr += linesize;
  892. CACHE->CIR = op_addr;
  893. op_addr += linesize;
  894. CACHE->CIR = op_addr;
  895. op_addr += linesize;
  896. CACHE->CIR = op_addr;
  897. op_addr += linesize;
  898. CACHE->CIR = op_addr;
  899. op_addr += linesize;
  900. CACHE->CIR = op_addr;
  901. op_addr += linesize;
  902. CACHE->CIR = op_addr;
  903. op_addr += linesize;
  904. op_size -= 128;
  905. }
  906. while (op_size > 0) {
  907. CACHE->CIR = op_addr;
  908. op_addr += linesize;
  909. op_size -= linesize;
  910. }
  911. #endif
  912. }
  913. /**
  914. \brief setup cacheable range Cache
  915. \details setup Cache range
  916. */
  917. __STATIC_INLINE void csi_cache_set_range (uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable)
  918. {
  919. CACHE->CRCR[index] = ((baseAddr & CACHE_CRCR_BASE_ADDR_Msk) |
  920. (_VAL2FLD(CACHE_CRCR_SIZE, size)) |
  921. (_VAL2FLD(CACHE_CRCR_EN, enable)));
  922. }
  923. /**
  924. \brief Enable cache profile
  925. \details Turns on Cache profile
  926. */
  927. __STATIC_INLINE void csi_cache_enable_profile (void)
  928. {
  929. CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFEN_Msk;
  930. }
  931. /**
  932. \brief Disable cache profile
  933. \details Turns off Cache profile
  934. */
  935. __STATIC_INLINE void csi_cache_disable_profile (void)
  936. {
  937. CACHE->CPFCR &= ~(uint32_t)CACHE_CPFCR_PFEN_Msk;
  938. }
  939. /**
  940. \brief Reset cache profile
  941. \details Reset Cache profile
  942. */
  943. __STATIC_INLINE void csi_cache_reset_profile (void)
  944. {
  945. CACHE->CPFCR |= (uint32_t)CACHE_CPFCR_PFRST_Msk;
  946. }
  947. /**
  948. \brief cache access times
  949. \details Cache access times
  950. \note every 256 access add 1.
  951. \return cache access times, actual times should be multiplied by 256
  952. */
  953. __STATIC_INLINE uint32_t csi_cache_get_access_time (void)
  954. {
  955. return CACHE->CPFATR;
  956. }
  957. /**
  958. \brief cache miss times
  959. \details Cache miss times
  960. \note every 256 miss add 1.
  961. \return cache miss times, actual times should be multiplied by 256
  962. */
  963. __STATIC_INLINE uint32_t csi_cache_get_miss_time (void)
  964. {
  965. return CACHE->CPFMTR;
  966. }
  967. /*@} end of CSI_Core_CacheFunctions */
  968. /*@} end of CSI_core_DebugFunctions */
  969. /* ################################## IRQ Functions ############################################ */
  970. /**
  971. \brief Save the Irq context
  972. \details save the psr result before disable irq.
  973. */
  974. __STATIC_INLINE uint32_t csi_irq_save(void)
  975. {
  976. uint32_t result;
  977. result = __get_MSTATUS();
  978. __disable_irq();
  979. return(result);
  980. }
  981. /**
  982. \brief Restore the Irq context
  983. \details restore saved primask state.
  984. \param [in] irq_state psr irq state.
  985. */
  986. __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
  987. {
  988. __set_MSTATUS(irq_state);
  989. }
  990. /*@} end of IRQ Functions */
  991. #ifdef __cplusplus
  992. }
  993. #endif
  994. #endif /* __CORE_RV32_H_DEPENDANT */
  995. #endif /* __CSI_GENERIC */