//------------------------------------------------------------
// DONOT MODIFY THIS FILE
// generated by JISHENGJU automatically
//------------------------------------------------------------

#ifndef DWC_DDR_UMCTL2_HEADER_H
#define DWC_DDR_UMCTL2_HEADER_H

#define MSTR             _DDR_CTRL_BADDR+0x0
#define STAT             _DDR_CTRL_BADDR+0x4
#define MRCTRL0          _DDR_CTRL_BADDR+0x10
#define MRCTRL1          _DDR_CTRL_BADDR+0x14
#define MRSTAT           _DDR_CTRL_BADDR+0x18
#define DERATEEN         _DDR_CTRL_BADDR+0x20
#define DERATEINT        _DDR_CTRL_BADDR+0x24
#define DERATECTL        _DDR_CTRL_BADDR+0x2c
#define PWRCTL           _DDR_CTRL_BADDR+0x30
#define PWRTMG           _DDR_CTRL_BADDR+0x34
#define HWLPCTL          _DDR_CTRL_BADDR+0x38
#define RFSHCTL0         _DDR_CTRL_BADDR+0x50
#define RFSHCTL1         _DDR_CTRL_BADDR+0x54
#define RFSHCTL3         _DDR_CTRL_BADDR+0x60
#define RFSHTMG          _DDR_CTRL_BADDR+0x64
#define RFSHTMG1         _DDR_CTRL_BADDR+0x68
#define CRCPARCTL0       _DDR_CTRL_BADDR+0xc0
#define CRCPARSTAT       _DDR_CTRL_BADDR+0xcc
#define INIT0            _DDR_CTRL_BADDR+0xd0
#define INIT1            _DDR_CTRL_BADDR+0xd4
#define INIT2            _DDR_CTRL_BADDR+0xd8
#define INIT3            _DDR_CTRL_BADDR+0xdc
#define INIT4            _DDR_CTRL_BADDR+0xe0
#define INIT5            _DDR_CTRL_BADDR+0xe4
#define INIT6            _DDR_CTRL_BADDR+0xe8
#define INIT7            _DDR_CTRL_BADDR+0xec
#define DIMMCTL          _DDR_CTRL_BADDR+0xf0
#define RANKCTL          _DDR_CTRL_BADDR+0xf4
#define RANKCTL1         _DDR_CTRL_BADDR+0xf8
#define DRAMTMG0         _DDR_CTRL_BADDR+0x100
#define DRAMTMG1         _DDR_CTRL_BADDR+0x104
#define DRAMTMG2         _DDR_CTRL_BADDR+0x108
#define DRAMTMG3         _DDR_CTRL_BADDR+0x10c
#define DRAMTMG4         _DDR_CTRL_BADDR+0x110
#define DRAMTMG5         _DDR_CTRL_BADDR+0x114
#define DRAMTMG6         _DDR_CTRL_BADDR+0x118
#define DRAMTMG7         _DDR_CTRL_BADDR+0x11c
#define DRAMTMG8         _DDR_CTRL_BADDR+0x120
#define DRAMTMG12        _DDR_CTRL_BADDR+0x130
#define DRAMTMG13        _DDR_CTRL_BADDR+0x134
#define DRAMTMG14        _DDR_CTRL_BADDR+0x138
#define DRAMTMG17        _DDR_CTRL_BADDR+0x144
#define ZQCTL0           _DDR_CTRL_BADDR+0x180
#define ZQCTL1           _DDR_CTRL_BADDR+0x184
#define ZQCTL2           _DDR_CTRL_BADDR+0x188
#define ZQSTAT           _DDR_CTRL_BADDR+0x18c
#define DFITMG0          _DDR_CTRL_BADDR+0x190
#define DFITMG1          _DDR_CTRL_BADDR+0x194
#define DFILPCFG0        _DDR_CTRL_BADDR+0x198
#define DFIUPD0          _DDR_CTRL_BADDR+0x1a0
#define DFIUPD1          _DDR_CTRL_BADDR+0x1a4
#define DFIUPD2          _DDR_CTRL_BADDR+0x1a8
#define DFIMISC          _DDR_CTRL_BADDR+0x1b0
#define DFITMG2          _DDR_CTRL_BADDR+0x1b4
#define DFISTAT          _DDR_CTRL_BADDR+0x1bc
#define DBICTL           _DDR_CTRL_BADDR+0x1c0
#define DFIPHYMSTR       _DDR_CTRL_BADDR+0x1c4
#define ADDRMAP0         _DDR_CTRL_BADDR+0x200
#define ADDRMAP1         _DDR_CTRL_BADDR+0x204
#define ADDRMAP2         _DDR_CTRL_BADDR+0x208
#define ADDRMAP3         _DDR_CTRL_BADDR+0x20c
#define ADDRMAP4         _DDR_CTRL_BADDR+0x210
#define ADDRMAP5         _DDR_CTRL_BADDR+0x214
#define ADDRMAP6         _DDR_CTRL_BADDR+0x218
#define ADDRMAP7         _DDR_CTRL_BADDR+0x21c
#define ADDRMAP8         _DDR_CTRL_BADDR+0x220
#define ADDRMAP9         _DDR_CTRL_BADDR+0x224
#define ADDRMAP10        _DDR_CTRL_BADDR+0x228
#define ADDRMAP11        _DDR_CTRL_BADDR+0x22c
#define ODTCFG           _DDR_CTRL_BADDR+0x240
#define ODTMAP           _DDR_CTRL_BADDR+0x244
#define SCHED            _DDR_CTRL_BADDR+0x250
#define SCHED1           _DDR_CTRL_BADDR+0x254
#define PERFHPR1         _DDR_CTRL_BADDR+0x25c
#define PERFLPR1         _DDR_CTRL_BADDR+0x264
#define PERFWR1          _DDR_CTRL_BADDR+0x26c
#define SCHED3           _DDR_CTRL_BADDR+0x270
#define SCHED4           _DDR_CTRL_BADDR+0x274
#define DBG0             _DDR_CTRL_BADDR+0x300
#define DBG1             _DDR_CTRL_BADDR+0x304
#define DBGCAM           _DDR_CTRL_BADDR+0x308
#define DBGCMD           _DDR_CTRL_BADDR+0x30c
#define DBGSTAT          _DDR_CTRL_BADDR+0x310
#define SWCTL            _DDR_CTRL_BADDR+0x320
#define SWSTAT           _DDR_CTRL_BADDR+0x324
#define SWCTLSTATIC      _DDR_CTRL_BADDR+0x328
#define POISONCFG        _DDR_CTRL_BADDR+0x36c
#define POISONSTAT       _DDR_CTRL_BADDR+0x370
#define DERATESTAT       _DDR_CTRL_BADDR+0x3f0
#define PSTAT              _DDR_CTRL_BADDR+0x3fc
#define PCCFG              _DDR_CTRL_BADDR+0x400
#define PCFGR_0            _DDR_CTRL_BADDR+0x404
#define PCFGW_0            _DDR_CTRL_BADDR+0x408
#define PCTRL_0            _DDR_CTRL_BADDR+0x490
#define PCFGQOS0_0         _DDR_CTRL_BADDR+0x494
#define PCFGQOS1_0         _DDR_CTRL_BADDR+0x498
#define PCFGWQOS0_0        _DDR_CTRL_BADDR+0x49c
#define PCFGWQOS1_0        _DDR_CTRL_BADDR+0x4a0
#define PCFGR_1            _DDR_CTRL_BADDR+0x4b4
#define PCFGW_1            _DDR_CTRL_BADDR+0x4b8
#define PCTRL_1            _DDR_CTRL_BADDR+0x540
#define PCFGQOS0_1         _DDR_CTRL_BADDR+0x544
#define PCFGQOS1_1         _DDR_CTRL_BADDR+0x548
#define PCFGWQOS0_1        _DDR_CTRL_BADDR+0x54c
#define PCFGWQOS1_1        _DDR_CTRL_BADDR+0x550
#define PCFGR_2            _DDR_CTRL_BADDR+0x564
#define PCFGW_2            _DDR_CTRL_BADDR+0x568
#define PCTRL_2            _DDR_CTRL_BADDR+0x5f0
#define PCFGQOS0_2         _DDR_CTRL_BADDR+0x5f4
#define PCFGQOS1_2         _DDR_CTRL_BADDR+0x5f8
#define PCFGWQOS0_2        _DDR_CTRL_BADDR+0x5fc
#define PCFGWQOS1_2        _DDR_CTRL_BADDR+0x600
#define PCFGR_3            _DDR_CTRL_BADDR+0x614
#define PCFGW_3            _DDR_CTRL_BADDR+0x618
#define PCTRL_3            _DDR_CTRL_BADDR+0x6a0
#define PCFGQOS0_3         _DDR_CTRL_BADDR+0x6a4
#define PCFGQOS1_3         _DDR_CTRL_BADDR+0x6a8
#define PCFGWQOS0_3        _DDR_CTRL_BADDR+0x6ac
#define PCFGWQOS1_3        _DDR_CTRL_BADDR+0x6b0
#define PCFGR_4            _DDR_CTRL_BADDR+0x6c4
#define PCFGW_4            _DDR_CTRL_BADDR+0x6c8
#define PCTRL_4            _DDR_CTRL_BADDR+0x750
#define PCFGQOS0_4         _DDR_CTRL_BADDR+0x754
#define PCFGQOS1_4         _DDR_CTRL_BADDR+0x758
#define PCFGWQOS0_4        _DDR_CTRL_BADDR+0x75c
#define PCFGWQOS1_4        _DDR_CTRL_BADDR+0x760
#define UMCTL2_VER_NUMBER  _DDR_CTRL_BADDR+0xff0
#define UMCTL2_VER_TYPE    _DDR_CTRL_BADDR+0xff4
#define STAT_DCH1        _DDR_CTRL_BADDR+0x1b04
#define MRCTRL0_DCH1     _DDR_CTRL_BADDR+0x1b10
#define MRCTRL1_DCH1     _DDR_CTRL_BADDR+0x1b14
#define MRSTAT_DCH1      _DDR_CTRL_BADDR+0x1b18
#define DERATECTL_DCH1   _DDR_CTRL_BADDR+0x1b2c
#define PWRCTL_DCH1      _DDR_CTRL_BADDR+0x1b30
#define HWLPCTL_DCH1     _DDR_CTRL_BADDR+0x1b38
#define CRCPARCTL0_DCH1  _DDR_CTRL_BADDR+0x1bc0
#define CRCPARSTAT_DCH1  _DDR_CTRL_BADDR+0x1bcc
#define ZQCTL2_DCH1      _DDR_CTRL_BADDR+0x1c88
#define ZQSTAT_DCH1      _DDR_CTRL_BADDR+0x1c8c
#define DFISTAT_DCH1     _DDR_CTRL_BADDR+0x1cbc
#define ODTMAP_DCH1      _DDR_CTRL_BADDR+0x1d44
#define DBG1_DCH1        _DDR_CTRL_BADDR+0x1e04
#define DBGCAM_DCH1      _DDR_CTRL_BADDR+0x1e08
#define DBGCMD_DCH1      _DDR_CTRL_BADDR+0x1e0c
#define DBGSTAT_DCH1     _DDR_CTRL_BADDR+0x1e10
#define DERATESTAT_DCH1  _DDR_CTRL_BADDR+0x1ef0
#define DERATEEN_FREQ1   _DDR_CTRL_BADDR+0x2020
#define DERATEINT_FREQ1  _DDR_CTRL_BADDR+0x2024
#define PWRTMG_FREQ1     _DDR_CTRL_BADDR+0x2034
#define RFSHCTL0_FREQ1   _DDR_CTRL_BADDR+0x2050
#define RFSHTMG_FREQ1    _DDR_CTRL_BADDR+0x2064
#define RFSHTMG1_FREQ1   _DDR_CTRL_BADDR+0x2068
#define INIT3_FREQ1      _DDR_CTRL_BADDR+0x20dc
#define INIT4_FREQ1      _DDR_CTRL_BADDR+0x20e0
#define INIT6_FREQ1      _DDR_CTRL_BADDR+0x20e8
#define INIT7_FREQ1      _DDR_CTRL_BADDR+0x20ec
#define RANKCTL_FREQ1    _DDR_CTRL_BADDR+0x20f4
#define RANKCTL1_FREQ1   _DDR_CTRL_BADDR+0x20f8
#define DRAMTMG0_FREQ1   _DDR_CTRL_BADDR+0x2100
#define DRAMTMG1_FREQ1   _DDR_CTRL_BADDR+0x2104
#define DRAMTMG2_FREQ1   _DDR_CTRL_BADDR+0x2108
#define DRAMTMG3_FREQ1   _DDR_CTRL_BADDR+0x210c
#define DRAMTMG4_FREQ1   _DDR_CTRL_BADDR+0x2110
#define DRAMTMG5_FREQ1   _DDR_CTRL_BADDR+0x2114
#define DRAMTMG6_FREQ1   _DDR_CTRL_BADDR+0x2118
#define DRAMTMG7_FREQ1   _DDR_CTRL_BADDR+0x211c
#define DRAMTMG8_FREQ1   _DDR_CTRL_BADDR+0x2120
#define DRAMTMG12_FREQ1  _DDR_CTRL_BADDR+0x2130
#define DRAMTMG13_FREQ1  _DDR_CTRL_BADDR+0x2134
#define DRAMTMG14_FREQ1  _DDR_CTRL_BADDR+0x2138
#define ZQCTL0_FREQ1     _DDR_CTRL_BADDR+0x2180
#define DFITMG0_FREQ1    _DDR_CTRL_BADDR+0x2190
#define DFITMG1_FREQ1    _DDR_CTRL_BADDR+0x2194
#define DFITMG2_FREQ1    _DDR_CTRL_BADDR+0x21b4
#define ODTCFG_FREQ1     _DDR_CTRL_BADDR+0x2240


#endif

